/drivers/clk/ux500/ |
D | clk-sysctrl.c | 27 u8 reg_mask[SYSCTRL_MAX_NUM_PARENTS]; member 40 ret = ab8500_sysctrl_write(clk->reg_sel[0], clk->reg_mask[0], in clk_sysctrl_prepare() 53 if (ab8500_sysctrl_clear(clk->reg_sel[0], clk->reg_mask[0])) in clk_sysctrl_unprepare() 73 clk->reg_mask[old_index]); in clk_sysctrl_set_parent() 80 clk->reg_mask[index], in clk_sysctrl_set_parent() 85 clk->reg_mask[old_index], in clk_sysctrl_set_parent() 122 u8 *reg_mask, in clk_reg_sysctrl() argument 149 clk->reg_mask[0] = reg_mask[0]; in clk_reg_sysctrl() 155 clk->reg_mask[i] = reg_mask[i]; in clk_reg_sysctrl() 181 u8 reg_mask, in clk_reg_sysctrl_gate() argument [all …]
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D | clk.h | 66 u8 reg_mask, 75 u8 reg_mask, 86 u8 *reg_mask,
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/drivers/power/reset/ |
D | atc260x-poweroff.c | 29 uint reg_mask, reg_val; in atc2603c_do_poweroff() local 48 reg_mask = ATC2603C_PMU_SYS_CTL3_EN_S2 | ATC2603C_PMU_SYS_CTL3_EN_S3; in atc2603c_do_poweroff() 50 ret = regmap_update_bits(pwrc->regmap, ATC2603C_PMU_SYS_CTL3, reg_mask, in atc2603c_do_poweroff() 58 reg_mask = restart ? ATC2603C_PMU_SYS_CTL0_RESTART_EN in atc2603c_do_poweroff() 64 reg_mask, reg_val); in atc2603c_do_poweroff() 80 uint reg_mask, reg_val; in atc2609a_do_poweroff() local 99 reg_mask = ATC2609A_PMU_SYS_CTL3_EN_S2 | ATC2609A_PMU_SYS_CTL3_EN_S3; in atc2609a_do_poweroff() 101 ret = regmap_update_bits(pwrc->regmap, ATC2609A_PMU_SYS_CTL3, reg_mask, in atc2609a_do_poweroff() 109 reg_mask = restart ? ATC2609A_PMU_SYS_CTL0_RESTART_EN in atc2609a_do_poweroff() 115 reg_mask, reg_val); in atc2609a_do_poweroff()
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/drivers/irqchip/ |
D | irq-mmp.c | 43 void __iomem *reg_mask; member 86 r = readl_relaxed(data->reg_mask) | (1 << hwirq); in icu_mask_ack_irq() 87 writel_relaxed(r, data->reg_mask); in icu_mask_ack_irq() 115 r = readl_relaxed(data->reg_mask) | (1 << hwirq); in icu_mask_irq() 116 writel_relaxed(r, data->reg_mask); in icu_mask_irq() 134 r = readl_relaxed(data->reg_mask) & ~(1 << hwirq); in icu_unmask_irq() 135 writel_relaxed(r, data->reg_mask); in icu_unmask_irq() 169 mask = readl_relaxed(data->reg_mask); in icu_mux_irq_demux() 286 icu_data[1].reg_mask = mmp_icu_base + 0x168; in mmp2_init_icu() 298 icu_data[2].reg_mask = mmp_icu_base + 0x16c; in mmp2_init_icu() [all …]
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/drivers/net/ethernet/broadcom/bnx2x/ |
D | bnx2x_init.h | 569 } reg_mask; /* Register mask (all valid bits) */ member 695 return bnx2x_blocks_parity_data[idx].reg_mask.e1; in bnx2x_parity_reg_mask() 697 return bnx2x_blocks_parity_data[idx].reg_mask.e1h; in bnx2x_parity_reg_mask() 699 return bnx2x_blocks_parity_data[idx].reg_mask.e2; in bnx2x_parity_reg_mask() 701 return bnx2x_blocks_parity_data[idx].reg_mask.e3; in bnx2x_parity_reg_mask() 741 u32 reg_mask = bnx2x_parity_reg_mask(bp, i); in bnx2x_clear_blocks_parity() local 743 if (reg_mask) { in bnx2x_clear_blocks_parity() 746 if (reg_val & reg_mask) in bnx2x_clear_blocks_parity() 750 reg_val & reg_mask); in bnx2x_clear_blocks_parity() 774 u32 reg_mask = bnx2x_parity_reg_mask(bp, i); in bnx2x_enable_blocks_parity() local [all …]
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/drivers/gpio/ |
D | gpio-htc-egpio.c | 38 int reg_mask; member 192 reg, (egpio->cached_values >> shift) & ei->reg_mask); in egpio_set() 199 egpio_writew((egpio->cached_values >> shift) & ei->reg_mask, ei, reg); in egpio_set() 245 if (!((egpio->is_out >> shift) & ei->reg_mask)) in egpio_write_cache() 249 (egpio->cached_values >> shift) & ei->reg_mask, in egpio_write_cache() 253 & ei->reg_mask, ei, reg); in egpio_write_cache() 301 ei->reg_mask = (1 << pdata->reg_width) - 1; in egpio_probe()
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/drivers/pci/controller/dwc/ |
D | pcie-al.c | 126 u8 reg_mask; member 225 unsigned int busnr_reg = busnr & target_bus_cfg->reg_mask; in al_pcie_conf_addr_map_bus() 233 target_bus_cfg->reg_mask); in al_pcie_conf_addr_map_bus() 268 target_bus_cfg->reg_mask = ~target_bus_cfg->ecam_mask; in al_pcie_config_prepare() 269 target_bus_cfg->reg_val = bus->start & target_bus_cfg->reg_mask; in al_pcie_config_prepare() 272 target_bus_cfg->reg_mask); in al_pcie_config_prepare()
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/drivers/net/ethernet/stmicro/stmmac/ |
D | stmmac_mdio.c | 240 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; in stmmac_mdio_read() 247 value &= ~priv->hw->mii.reg_mask; in stmmac_mdio_read() 250 priv->hw->mii.reg_mask; in stmmac_mdio_read() 308 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; in stmmac_mdio_write() 316 value &= ~priv->hw->mii.reg_mask; in stmmac_mdio_write() 319 priv->hw->mii.reg_mask; in stmmac_mdio_write()
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D | common.h | 507 unsigned int reg_mask; /* MII reg mask */ member 539 u32 reg_mask; member
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D | dwmac100_core.c | 196 mac->mii.reg_mask = 0x000007C0; in dwmac100_setup()
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D | dwmac4_core.c | 143 value &= ~route_possibilities[packet - 1].reg_mask; in dwmac4_rx_queue_routing() 145 route_possibilities[packet - 1].reg_mask; in dwmac4_rx_queue_routing() 1329 mac->mii.reg_mask = GENMASK(20, 16); in dwmac4_setup()
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/drivers/memory/ |
D | stm32-fmc2-ebi.c | 167 u32 reg_mask; member 353 regmap_update_bits(ebi->regmap, reg, prop->reg_mask, in stm32_fmc2_ebi_set_bit_field() 354 setup ? prop->reg_mask : 0); in stm32_fmc2_ebi_set_bit_field() 729 .reg_mask = FMC2_BCR1_CCLKEN, 737 .reg_mask = FMC2_BCR_MUXEN, 750 .reg_mask = FMC2_BCR_WAITPOL, 757 .reg_mask = FMC2_BCR_WAITCFG, 765 .reg_mask = FMC2_BCR_WAITEN, 773 .reg_mask = FMC2_BCR_ASYNCWAIT,
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/drivers/pinctrl/ti/ |
D | pinctrl-ti-iodelay.c | 216 u32 reg_mask, reg_val, tmp_val; in ti_iodelay_pinconf_set() local 235 reg_mask = reg->signature_mask; in ti_iodelay_pinconf_set() 238 reg_mask |= reg->binary_data_coarse_mask; in ti_iodelay_pinconf_set() 247 reg_mask |= reg->binary_data_fine_mask; in ti_iodelay_pinconf_set() 262 reg_mask |= reg->lock_mask; in ti_iodelay_pinconf_set() 264 r = regmap_update_bits(iod->regmap, cfg->offset, reg_mask, reg_val); in ti_iodelay_pinconf_set()
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/drivers/soc/qcom/ |
D | cpr.c | 463 u32 val, error_steps, reg_mask; in cpr_scale() local 499 reg_mask = RBCPR_CTL_UP_THRESHOLD_MASK; in cpr_scale() 500 reg_mask <<= RBCPR_CTL_UP_THRESHOLD_SHIFT; in cpr_scale() 501 val = reg_mask; in cpr_scale() 502 cpr_ctl_modify(drv, reg_mask, val); in cpr_scale() 536 reg_mask = RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN; in cpr_scale() 539 cpr_ctl_modify(drv, reg_mask, val); in cpr_scale() 568 reg_mask = RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN; in cpr_scale() 572 reg_mask = RBCPR_CTL_UP_THRESHOLD_MASK; in cpr_scale() 573 reg_mask <<= RBCPR_CTL_UP_THRESHOLD_SHIFT; in cpr_scale() [all …]
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/drivers/pinctrl/samsung/ |
D | pinctrl-exynos.c | 57 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_mask() local 63 mask = readl(bank->eint_base + reg_mask); in exynos_irq_mask() 65 writel(mask, bank->eint_base + reg_mask); in exynos_irq_mask() 85 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_unmask() local 102 mask = readl(bank->eint_base + reg_mask); in exynos_irq_unmask() 104 writel(mask, bank->eint_base + reg_mask); in exynos_irq_unmask()
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/drivers/pinctrl/mvebu/ |
D | pinctrl-armada-37xx.c | 63 u32 reg_mask; member 118 .reg_mask = _mask, \ 128 .reg_mask = _mask, \ 138 .reg_mask = _mask, \ 148 .reg_mask = _mask, \ 159 .reg_mask = _mask, \ 346 unsigned int mask = grp->reg_mask; in armada_37xx_pmx_set_by_name()
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/drivers/media/i2c/ |
D | mt9m111.c | 143 #define reg_mask(reg, val, mask) mt9m111_reg_mask(client, MT9M111_##reg, \ macro 226 unsigned int reg_mask; member 261 .reg_mask = MT9M111_RM_PWR_MASK | MT9M111_RM_SKIP2_MASK, 270 .reg_mask = MT9M111_RM_PWR_MASK | MT9M111_RM_SKIP2_MASK, 280 .reg_mask = MT9M111_RM_PWR_MASK | MT9M111_RM_SKIP2_MASK, 946 mt9m111->current_mode->reg_mask); in mt9m111_restore_state()
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/drivers/phy/broadcom/ |
D | phy-bcm-ns2-usbdrd.c | 88 static inline int pll_lock_stat(u32 usb_reg, int reg_mask, in pll_lock_stat() argument 94 val, (val & reg_mask), 1, in pll_lock_stat()
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/drivers/video/fbdev/via/ |
D | hw.c | 968 int reg_mask; in viafb_load_reg() local 977 reg_mask = 0; in viafb_load_reg() 986 reg_mask = reg_mask | (BIT0 << j); in viafb_load_reg() 993 viafb_write_reg_mask(cr_index, VIACR, data, reg_mask); in viafb_load_reg() 995 viafb_write_reg_mask(cr_index, VIASR, data, reg_mask); in viafb_load_reg()
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/drivers/tty/serial/8250/ |
D | 8250_aspeed_vuart.c | 381 u32 reg_offset, u32 reg_mask) in aspeed_vuart_auto_configure_sirq_polarity() argument 397 aspeed_vuart_set_sirq_polarity(vuart, (value & reg_mask) == 0); in aspeed_vuart_auto_configure_sirq_polarity()
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/drivers/crypto/qat/qat_common/ |
D | qat_hal.c | 1391 unsigned short reg_mask; in qat_hal_put_rel_wr_xfer() local 1409 reg_mask = (unsigned short)~0x1f; in qat_hal_put_rel_wr_xfer() 1411 reg_mask = (unsigned short)~0xf; in qat_hal_put_rel_wr_xfer() 1413 if (reg_num & reg_mask) in qat_hal_put_rel_wr_xfer()
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/drivers/gpu/drm/amd/amdgpu/ |
D | vi.c | 1065 u32 reg_mask; in vi_set_vce_clocks() local 1071 reg_mask = CG_ECLK_CNTL__ECLK_DIVIDER_MASK; in vi_set_vce_clocks() 1076 reg_mask = CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK | CG_ECLK_CNTL__ECLK_DIVIDER_MASK; in vi_set_vce_clocks() 1095 tmp &= ~reg_mask; in vi_set_vce_clocks()
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/drivers/usb/serial/ |
D | f81534.c | 174 const u8 reg_mask; member 1355 pins->pin[i].reg_addr, pins->pin[i].reg_mask, in f81534_set_port_output_pin() 1356 value & BIT(i) ? pins->pin[i].reg_mask : 0); in f81534_set_port_output_pin()
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/drivers/clk/samsung/ |
D | clk-pll.c | 80 unsigned int reg_mask) in samsung_pll_lock_wait() argument 99 if (readl_relaxed(pll->con_reg) & reg_mask) in samsung_pll_lock_wait() 107 val & reg_mask, 0, PLL_TIMEOUT_US); in samsung_pll_lock_wait()
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/drivers/pinctrl/bcm/ |
D | pinctrl-bcm281xx.c | 971 static inline void bcm281xx_pin_update(u32 *reg_val, u32 *reg_mask, in bcm281xx_pin_update() argument 977 *reg_mask |= param_mask; in bcm281xx_pin_update()
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