| /drivers/i2c/busses/ |
| D | i2c-mv64xxx.c | 129 struct mv64xxx_i2c_regs reg_offsets; member
221 writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset); in mv64xxx_i2c_hw_init()
223 drv_data->reg_base + drv_data->reg_offsets.clock); in mv64xxx_i2c_hw_init()
224 writel(0, drv_data->reg_base + drv_data->reg_offsets.addr); in mv64xxx_i2c_hw_init()
225 writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr); in mv64xxx_i2c_hw_init()
227 drv_data->reg_base + drv_data->reg_offsets.control); in mv64xxx_i2c_hw_init()
354 drv_data->reg_base + drv_data->reg_offsets.control); in mv64xxx_i2c_send_start()
382 drv_data->reg_base + drv_data->reg_offsets.control); in mv64xxx_i2c_do_action()
387 drv_data->reg_base + drv_data->reg_offsets.data); in mv64xxx_i2c_do_action()
389 drv_data->reg_base + drv_data->reg_offsets.control); in mv64xxx_i2c_do_action()
[all …]
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| /drivers/spi/ |
| D | spi-bcm63xx.c | 141 const unsigned long *reg_offsets; member
157 return readb(bs->regs + bs->reg_offsets[offset]); in bcm_spi_readb()
164 return ioread16be(bs->regs + bs->reg_offsets[offset]); in bcm_spi_readw()
166 return readw(bs->regs + bs->reg_offsets[offset]); in bcm_spi_readw()
173 writeb(value, bs->regs + bs->reg_offsets[offset]); in bcm_spi_writeb()
180 iowrite16be(value, bs->regs + bs->reg_offsets[offset]); in bcm_spi_writew()
182 writew(value, bs->regs + bs->reg_offsets[offset]); in bcm_spi_writew()
559 bs->reg_offsets = bcm63xx_spireg; in bcm63xx_spi_probe()
560 bs->fifo_size = bs->reg_offsets[SPI_MSG_DATA_SIZE]; in bcm63xx_spi_probe()
578 bs->msg_type_shift = bs->reg_offsets[SPI_MSG_TYPE_SHIFT]; in bcm63xx_spi_probe()
[all …]
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| /drivers/pci/controller/dwc/ |
| D | pcie-al.c | 136 struct al_pcie_reg_offsets reg_offsets; member
188 pcie->reg_offsets.ob_ctrl = OB_CTRL_REV1_2_OFFSET; in al_pcie_reg_offsets_set()
192 pcie->reg_offsets.ob_ctrl = OB_CTRL_REV3_5_OFFSET; in al_pcie_reg_offsets_set()
213 pcie->reg_offsets.ob_ctrl + CFG_TARGET_BUS, in al_pcie_target_bus_set()
278 cfg_control_offset = AXI_BASE_OFFSET + pcie->reg_offsets.ob_ctrl + in al_pcie_config_prepare()
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| /drivers/net/ethernet/8390/ |
| D | xsurf100.c | 254 static u32 reg_offsets[32]; in xsurf100_probe() local
277 reg_offsets[reg] = 4 * reg; in xsurf100_probe()
284 ax88796_data.ax.reg_offsets = reg_offsets; in xsurf100_probe()
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| D | ax88796.c | 95 u32 reg_offsets[0x20]; member
894 if (ax->plat->reg_offsets) in ax_probe()
895 ei_local->reg_offset = ax->plat->reg_offsets; in ax_probe()
897 ei_local->reg_offset = ax->reg_offsets; in ax_probe()
899 ax->reg_offsets[ret] = (mem_size / 0x18) * ret; in ax_probe()
921 if (!ax->plat->reg_offsets) { in ax_probe()
923 ax->reg_offsets[ret] = (mem_size / 0x20) * ret; in ax_probe()
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| /drivers/gpu/drm/amd/display/dc/dce100/ |
| D | dce100_hw_sequencer.c | 43 static const struct dce100_hw_seq_reg_offsets reg_offsets[] = { variable
65 (reg + reg_offsets[id].crtc)
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| /drivers/net/dsa/ |
| D | bcm_sf2.h | 74 const u16 *reg_offsets; member
196 return readl_relaxed(priv->reg + priv->reg_offsets[off]); in reg_readl()
201 writel_relaxed(val, priv->reg + priv->reg_offsets[off]); in reg_writel()
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| D | bcm_sf2.c | 1236 const u16 *reg_offsets; member
1260 .reg_offsets = bcm_sf2_4908_reg_offsets,
1285 .reg_offsets = bcm_sf2_7445_reg_offsets,
1308 .reg_offsets = bcm_sf2_7278_reg_offsets,
1370 priv->reg_offsets = data->reg_offsets; in bcm_sf2_sw_probe()
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| /drivers/gpu/drm/amd/display/dc/dce112/ |
| D | dce112_hw_sequencer.c | 42 static const struct dce112_hw_seq_reg_offsets reg_offsets[] = { variable
63 (reg + reg_offsets[id].crtc)
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| D | dce112_compressor.c | 46 static const struct dce112_compressor_reg_offsets reg_offsets[] = { variable
405 cp110->offsets = reg_offsets[params->inst]; in dce112_compressor_enable_fbc()
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| /drivers/pci/controller/ |
| D | pcie-iproc-msi.c | 95 const u16 (*reg_offsets)[IPROC_MSI_REG_SIZE]; member
134 return readl_relaxed(pcie->base + msi->reg_offsets[eq][reg]); in iproc_msi_read_reg()
143 writel_relaxed(val, pcie->base + msi->reg_offsets[eq][reg]); in iproc_msi_write_reg()
574 msi->reg_offsets = iproc_msi_reg_paxb; in iproc_msi_init()
579 msi->reg_offsets = iproc_msi_reg_paxc; in iproc_msi_init()
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| D | pcie-iproc.c | 413 return pcie->reg_offsets[reg]; in iproc_pcie_reg_offset()
1445 pcie->reg_offsets = devm_kcalloc(dev, IPROC_PCIE_MAX_NUM_REG, in iproc_pcie_rev_init()
1446 sizeof(*pcie->reg_offsets), in iproc_pcie_rev_init()
1448 if (!pcie->reg_offsets) in iproc_pcie_rev_init()
1452 pcie->reg_offsets[0] = (pcie->type == IPROC_PCIE_PAXC_V2) ? in iproc_pcie_rev_init()
1455 pcie->reg_offsets[reg_idx] = regs[reg_idx] ? in iproc_pcie_rev_init()
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| D | pcie-iproc.h | 89 u16 *reg_offsets; member
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| D | pcie-brcmstb.c | 173 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX])
174 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA])
175 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1])
289 const int *reg_offsets; member
1253 pcie->reg_offsets = data->offsets; in brcm_pcie_probe()
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| /drivers/gpu/drm/amd/display/dc/dce120/ |
| D | dce120_hw_sequencer.c | 54 static const struct dce120_hw_seq_reg_offsets reg_offsets[] = {
76 (reg + reg_offsets[id].crtc)
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| /drivers/gpu/drm/amd/display/dc/dce80/ |
| D | dce80_timing_generator.c | 51 static const struct dce110_timing_generator_offsets reg_offsets[] = { variable
234 tg110->derived_offsets = reg_offsets[instance]; in dce80_timing_generator_construct()
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| /drivers/gpu/drm/amd/display/dc/dce60/ |
| D | dce60_timing_generator.c | 51 static const struct dce110_timing_generator_offsets reg_offsets[] = { variable
252 tg110->derived_offsets = reg_offsets[instance]; in dce60_timing_generator_construct()
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| /drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_compressor.c | 47 static const struct dce110_compressor_reg_offsets reg_offsets[] = { variable
81 cp110->offsets = reg_offsets[crtc_inst]; in reset_lb_on_vblank()
307 cp110->offsets = reg_offsets[params->inst]; in dce110_compressor_program_compressed_surface_address_and_pitch()
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| D | dce110_hw_sequencer.c | 99 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = { variable
115 (reg + reg_offsets[id].blnd)
118 (reg + reg_offsets[id].crtc)
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| /drivers/mtd/nand/raw/brcmnand/ |
| D | brcmnand.c | 264 const u16 *reg_offsets; member
669 ctrl->reg_offsets = brcmnand_regs_v72; in brcmnand_revision_init()
671 ctrl->reg_offsets = brcmnand_regs_v71; in brcmnand_revision_init()
673 ctrl->reg_offsets = brcmnand_regs_v60; in brcmnand_revision_init()
675 ctrl->reg_offsets = brcmnand_regs_v50; in brcmnand_revision_init()
677 ctrl->reg_offsets = brcmnand_regs_v33; in brcmnand_revision_init()
679 ctrl->reg_offsets = brcmnand_regs_v21; in brcmnand_revision_init()
787 u16 offs = ctrl->reg_offsets[reg]; in brcmnand_read_reg()
798 u16 offs = ctrl->reg_offsets[reg]; in brcmnand_write_reg()
898 u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE]; in brcmnand_cs_offset()
[all …]
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| /drivers/gpu/drm/i915/gt/ |
| D | intel_lrc.c | 534 static const u8 *reg_offsets(const struct intel_engine_cs *engine) in reg_offsets() function
774 set_offsets(regs, reg_offsets(engine), engine, inhibit); in __lrc_init_regs()
1223 set_offsets(ce->lrc_reg_state, reg_offsets(engine), engine, false); in lrc_update_offsets()
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| /drivers/gpu/drm/msm/adreno/ |
| D | adreno_gpu.h | 115 const unsigned int *reg_offsets; member
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hw_sequencer.c | 878 inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt; in dcn10_enable_stream_timing()
|