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Searched refs:regw (Results 1 – 6 of 6) sorted by relevance

/drivers/media/platform/davinci/
Dvpif.h33 #define regw(value, reg) writel(value, (reg + vpif_base)) macro
139 regw((regr(reg)) | (0x01 << bit), reg); in vpif_set_bit()
144 regw(((regr(reg)) & ~(0x01 << bit)), reg); in vpif_clr_bit()
221 #define channel0_intr_assert() (regw((regr(VPIF_CH0_CTRL)|\
225 #define channel1_intr_assert() (regw((regr(VPIF_CH1_CTRL)|\
229 #define channel2_intr_assert() (regw((regr(VPIF_CH2_CTRL)|\
233 #define channel3_intr_assert() (regw((regr(VPIF_CH3_CTRL)|\
274 regw((regr(VPIF_CH0_CTRL) | (VPIF_CH0_EN)), VPIF_CH0_CTRL); in enable_channel0()
276 regw((regr(VPIF_CH0_CTRL) & (~VPIF_CH0_EN)), VPIF_CH0_CTRL); in enable_channel0()
283 regw((regr(VPIF_CH1_CTRL) | (VPIF_CH1_EN)), VPIF_CH1_CTRL); in enable_channel1()
[all …]
Ddm644x_ccdc.c92 static inline void regw(u32 val, u32 offset) in regw() function
99 regw(flag, CCDC_PCR); in ccdc_enable()
106 regw(CCDC_ENABLE_VIDEO_PORT, CCDC_FMTCFG); in ccdc_enable_vport()
108 regw(CCDC_DISABLE_VIDEO_PORT, CCDC_FMTCFG); in ccdc_enable_vport()
132 regw((horz_start << CCDC_HORZ_INFO_SPH_SHIFT) | horz_nr_pixels, in ccdc_setwin()
144 regw(val, CCDC_VDINT); in ccdc_setwin()
157 regw(val, CCDC_VDINT); in ccdc_setwin()
160 regw((vert_start << CCDC_VERT_START_SLV0_SHIFT) | vert_start, in ccdc_setwin()
162 regw(vert_nr_lines, CCDC_VERT_LINES); in ccdc_setwin()
223 regw(0, i); in ccdc_restore_defaults()
[all …]
Ddm355_ccdc.c114 static inline void regw(u32 val, u32 offset) in regw() function
125 regw(temp, SYNCEN); in ccdc_enable()
134 regw(temp, SYNCEN); in ccdc_enable_output_to_sdram()
140 regw(ccdc_cfg.bayer.gain.r_ye, RYEGAIN); in ccdc_config_gain_offset()
141 regw(ccdc_cfg.bayer.gain.gr_cy, GRCYGAIN); in ccdc_config_gain_offset()
142 regw(ccdc_cfg.bayer.gain.gb_g, GBGGAIN); in ccdc_config_gain_offset()
143 regw(ccdc_cfg.bayer.gain.b_mg, BMGGAIN); in ccdc_config_gain_offset()
145 regw(ccdc_cfg.bayer.ccdc_offset, OFFSET); in ccdc_config_gain_offset()
159 regw(0, i); in ccdc_restore_defaults()
162 regw(MODESET_DEFAULT, MODESET); in ccdc_restore_defaults()
[all …]
Disif.c141 static inline void regw(u32 val, u32 offset) in regw() function
151 regw(new_val, offset); in reg_modify()
166 regw(0, CLAMPCFG); in isif_disable_all_modules()
168 regw(0, DFCCTL); in isif_disable_all_modules()
170 regw(0, CSCCTL); in isif_disable_all_modules()
172 regw(0, LINCFG0); in isif_disable_all_modules()
201 regw(val, CULH); in isif_config_culling()
204 regw(cul->vcpat, CULV); in isif_config_culling()
228 regw(val, CRGAIN); in isif_config_gain_offset()
232 regw(val, CGRGAIN); in isif_config_gain_offset()
[all …]
Dvpif.c297 regw(value, vpifregs[channel_id].h_cfg); in vpif_set_mode_info()
302 regw(value, vpifregs[channel_id].v_cfg_00); in vpif_set_mode_info()
307 regw(value, vpifregs[channel_id].v_cfg_01); in vpif_set_mode_info()
312 regw(value, vpifregs[channel_id].v_cfg_02); in vpif_set_mode_info()
315 regw(value, vpifregs[channel_id].v_cfg); in vpif_set_mode_info()
367 regw(value, reg); in config_vpif_params()
371 regw((vpifparams->video_params.hpitch), in config_vpif_params()
393 regw(0x80, VPIF_REQ_SIZE); in vpif_set_video_params()
394 regw(0x01, VPIF_EMULATION_CTRL); in vpif_set_video_params()
407 regw(value, vpifregs[channel_id].vanc0_strt); in vpif_set_vbi_display_params()
[all …]
/drivers/ata/
Dpata_sis.c656 u16 regw; in sis_fixup() local
660 pci_read_config_word(pdev, 0x50, &regw); in sis_fixup()
661 if (regw & 0x08) in sis_fixup()
662 pci_write_config_word(pdev, 0x50, regw & ~0x08); in sis_fixup()
663 pci_read_config_word(pdev, 0x52, &regw); in sis_fixup()
664 if (regw & 0x08) in sis_fixup()
665 pci_write_config_word(pdev, 0x52, regw & ~0x08); in sis_fixup()