| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_stream.c | 255 struct resource_context *res_ctx; in program_cursor_attributes() local
261 res_ctx = &dc->current_state->res_ctx; in program_cursor_attributes()
264 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; in program_cursor_attributes()
355 struct resource_context *res_ctx; in program_cursor_position() local
361 res_ctx = &dc->current_state->res_ctx; in program_cursor_position()
364 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; in program_cursor_position()
559 struct resource_context *res_ctx = in dc_stream_get_vblank_counter() local
560 &dc->current_state->res_ctx; in dc_stream_get_vblank_counter()
563 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; in dc_stream_get_vblank_counter()
565 if (res_ctx->pipe_ctx[i].stream != stream || !tg) in dc_stream_get_vblank_counter()
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| D | dc_resource.c | 393 struct resource_context *res_ctx, in resource_unreference_clock_source() argument
400 res_ctx->clock_source_ref_count[i]--; in resource_unreference_clock_source()
403 res_ctx->dp_clock_source_ref_count--; in resource_unreference_clock_source()
407 struct resource_context *res_ctx, in resource_reference_clock_source() argument
414 res_ctx->clock_source_ref_count[i]++; in resource_reference_clock_source()
417 res_ctx->dp_clock_source_ref_count++; in resource_reference_clock_source()
421 struct resource_context *res_ctx, in resource_get_clock_source_reference() argument
428 return res_ctx->clock_source_ref_count[i]; in resource_get_clock_source_reference()
431 return res_ctx->dp_clock_source_ref_count; in resource_get_clock_source_reference()
568 struct resource_context *res_ctx, in resource_find_used_clk_src_for_sharing() argument
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| D | dc_link_enc_cfg.c | 94 state->res_ctx.link_enc_assignments[stream_idx] = (struct link_enc_assignment){ in update_link_enc_assignment()
100 state->res_ctx.link_enc_avail[eng_idx] = ENGINE_ID_UNKNOWN; in update_link_enc_assignment()
103 state->res_ctx.link_enc_assignments[stream_idx].valid = false; in update_link_enc_assignment()
104 state->res_ctx.link_enc_avail[eng_idx] = eng_id; in update_link_enc_assignment()
122 eng_id = state->res_ctx.link_enc_avail[i]; in find_first_avail_link_enc()
140 struct link_enc_assignment assignment = state->res_ctx.link_enc_assignments[i]; in get_stream_using_link_enc()
164 state->res_ctx.link_enc_avail[i] = (enum engine_id) i; in link_enc_cfg_init()
166 state->res_ctx.link_enc_avail[i] = ENGINE_ID_UNKNOWN; in link_enc_cfg_init()
255 struct link_enc_assignment assignment = state->res_ctx.link_enc_assignments[i]; in link_enc_cfg_get_link_using_link_enc()
285 struct link_enc_assignment assignment = state->res_ctx.link_enc_assignments[i]; in link_enc_cfg_get_link_enc_used_by_link()
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| D | dc.c | 315 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_adjust_vmin_vmax()
351 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_get_last_used_drr_vtotal()
382 &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_get_crtc_position()
419 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_forward_dmcu_crc_window()
453 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_stop_dmcu_crc_win_update()
498 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_configure_crc()
563 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_get_crc()
587 if (dc->current_state->res_ctx.pipe_ctx[i].stream in dc_stream_set_dyn_expansion()
589 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_set_dyn_expansion()
609 if (link->dc->current_state->res_ctx.pipe_ctx[i].stream == in dc_stream_set_dither_option()
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| D | dc_debug.c | 309 struct resource_context *res_ctx) in context_timing_trace() argument
319 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; in context_timing_trace()
331 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; in context_timing_trace()
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| D | dc_surface.c | 152 &dc->current_state->res_ctx.pipe_ctx[i]; in dc_plane_get_status()
164 &dc->current_state->res_ctx.pipe_ctx[i]; in dc_plane_get_status()
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | resource.h | 101 struct resource_context *res_ctx,
106 struct resource_context *res_ctx,
111 struct resource_context *res_ctx,
124 struct resource_context *res_ctx,
128 struct resource_context *res_ctx,
132 struct resource_context *res_ctx,
143 struct resource_context *res_ctx,
176 struct resource_context *res_ctx,
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| D | core_types.h | 166 struct resource_context *res_ctx,
171 struct resource_context *res_ctx,
184 struct resource_context *res_ctx,
191 struct resource_context *res_ctx,
450 struct resource_context res_ctx; member
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_resource.c | 1657 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); in dcn20_build_mapped_resource()
1670 struct resource_context *res_ctx, in dcn20_acquire_dsc() argument
1676 …struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_r… in dcn20_acquire_dsc()
1684 res_ctx->is_dsc_acquired[pipe_idx] = true; in dcn20_acquire_dsc()
1689 if (dsc_old && !res_ctx->is_dsc_acquired[dsc_old->inst]) { in dcn20_acquire_dsc()
1691 res_ctx->is_dsc_acquired[dsc_old->inst] = true; in dcn20_acquire_dsc()
1697 if (!res_ctx->is_dsc_acquired[i]) { in dcn20_acquire_dsc()
1699 res_ctx->is_dsc_acquired[i] = true; in dcn20_acquire_dsc()
1704 void dcn20_release_dsc(struct resource_context *res_ctx, in dcn20_release_dsc() argument
1712 res_ctx->is_dsc_acquired[i] = false; in dcn20_release_dsc()
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| D | dcn20_resource.h | 131 void dcn20_release_dsc(struct resource_context *res_ctx,
136 struct resource_context *res_ctx,
142 struct resource_context *res_ctx,
146 struct resource_context *res_ctx,
150 struct resource_context *res_ctx,
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| D | dcn20_hwseq.c | 1688 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn20_program_front_end_for_ctx()
1690 &dc->current_state->res_ctx.pipe_ctx[i]; in dcn20_program_front_end_for_ctx()
1699 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn20_program_front_end_for_ctx()
1712 dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i], in dcn20_program_front_end_for_ctx()
1713 &context->res_ctx.pipe_ctx[i]); in dcn20_program_front_end_for_ctx()
1717 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable in dcn20_program_front_end_for_ctx()
1718 && !context->res_ctx.pipe_ctx[i].top_pipe in dcn20_program_front_end_for_ctx()
1719 && !context->res_ctx.pipe_ctx[i].prev_odm_pipe in dcn20_program_front_end_for_ctx()
1720 && context->res_ctx.pipe_ctx[i].stream) in dcn20_program_front_end_for_ctx()
1721 hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true); in dcn20_program_front_end_for_ctx()
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_resource.h | 72 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
80 struct resource_context *res_ctx,
87 struct resource_context *res_ctx,
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| D | dcn30_resource.c | 1465 struct resource_context *res_ctx = &context->res_ctx; in dcn30_populate_dml_pipes_from_context() local
1470 if (!res_ctx->pipe_ctx[i].stream) in dcn30_populate_dml_pipes_from_context()
1481 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) in dcn30_populate_dml_writeback_from_context() argument
1489 struct dc_stream_state *stream = res_ctx->pipe_ctx[i].stream; in dcn30_populate_dml_writeback_from_context()
1502 (wb_info->writeback_source_plane == res_ctx->pipe_ctx[i].plane_state)) { in dcn30_populate_dml_writeback_from_context()
1607 if (!context->res_ctx.pipe_ctx[i].stream) in dcn30_set_mcif_arb_params()
1611 …struct dc_writeback_info *writeback_info = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j]; in dcn30_set_mcif_arb_params()
1629 …wb_arb_params->time_per_pixel = (1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk;… in dcn30_set_mcif_arb_params()
1653 struct resource_context *res_ctx, in dcn30_acquire_post_bldn_3dlut() argument
1668 if (!res_ctx->is_mpc_3dlut_acquired[i]) { in dcn30_acquire_post_bldn_3dlut()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn2x/ |
| D | dcn2x.c | 65 struct resource_context *res_ctx, in dcn20_populate_dml_writeback_from_context() argument
73 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0]; in dcn20_populate_dml_writeback_from_context()
75 if (!res_ctx->pipe_ctx[i].stream) in dcn20_populate_dml_writeback_from_context()
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| D | dcn2x.h | 31 struct resource_context *res_ctx,
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dmub_psr.c | 241 struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx; in dmub_psr_copy_settings() local
245 if (res_ctx->pipe_ctx[i].stream && in dmub_psr_copy_settings()
246 res_ctx->pipe_ctx[i].stream->link == link && in dmub_psr_copy_settings()
247 res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) { in dmub_psr_copy_settings()
248 pipe_ctx = &res_ctx->pipe_ctx[i]; in dmub_psr_copy_settings()
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| /drivers/gpu/drm/amd/display/dc/dce60/ |
| D | dce60_hw_sequencer.c | 56 struct resource_context *res_ctx = &context->res_ctx; in dce60_should_enable_fbc() local
71 if (res_ctx->pipe_ctx[i].stream) { in dce60_should_enable_fbc()
73 pipe_ctx = &res_ctx->pipe_ctx[i]; in dce60_should_enable_fbc()
124 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; in dce60_enable_fbc()
396 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dce60_apply_ctx_for_surface()
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| /drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_hw_sequencer.c | 1102 if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL) in dce110_enable_audio_stream()
1386 struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. in dce110_enable_stream_timing()
1628 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i; in disable_vga_and_power_gate_all_controllers()
1630 &dc->current_state->res_ctx.pipe_ctx[i]); in disable_vga_and_power_gate_all_controllers()
1785 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dce110_set_displaymarks()
1814 struct resource_context *res_ctx, in dce110_set_safe_displaymarks() argument
1826 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL) in dce110_set_safe_displaymarks()
1829 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks( in dce110_set_safe_displaymarks()
1830 res_ctx->pipe_ctx[i].plane_res.mi, in dce110_set_safe_displaymarks()
1838 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks( in dce110_set_safe_displaymarks()
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| D | dce110_resource.c | 945 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); in build_mapped_resource()
978 context->res_ctx.pipe_ctx, in dce110_validate_bandwidth()
1128 struct resource_context *res_ctx = &context->res_ctx; in dce110_acquire_underlay() local
1130 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx]; in dce110_acquire_underlay()
1132 if (res_ctx->pipe_ctx[underlay_idx].stream) in dce110_acquire_underlay()
1144 if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) { in dce110_acquire_underlay()
1198 struct resource_context *res_ctx, in dce110_find_first_free_match_stream_enc_for_link() argument
1207 if (!res_ctx->is_stream_enc_acquired[i] && in dce110_find_first_free_match_stream_enc_for_link()
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| D | dce110_resource.h | 49 struct resource_context *res_ctx,
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| /drivers/gpu/drm/amd/display/dc/dce100/ |
| D | dce100_hw_sequencer.c | 112 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); in dce100_prepare_bandwidth()
124 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); in dce100_optimize_bandwidth()
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| D | dce100_resource.h | 50 struct resource_context *res_ctx,
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_resource.h | 46 struct resource_context *res_ctx,
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| /drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_hwseq.c | 553 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, in dcn31_reset_back_end_for_pipe()
577 &dc->current_state->res_ctx.pipe_ctx[i]; in dcn31_reset_hw_ctx_wrap()
578 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn31_reset_hw_ctx_wrap()
605 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn31_is_abm_supported()
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| /drivers/gpu/drm/amd/display/dc/ |
| D | dc_trace.h | 28 struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[index]; \
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