Home
last modified time | relevance | path

Searched refs:res_pool (Results 1 – 25 of 54) sorted by relevance

123

/drivers/bus/fsl-mc/
Dfsl-mc-allocator.c37 struct fsl_mc_resource_pool *res_pool; in fsl_mc_resource_pool_add_device() local
49 res_pool = &mc_bus->resource_pools[pool_type]; in fsl_mc_resource_pool_add_device()
50 if (res_pool->type != pool_type) in fsl_mc_resource_pool_add_device()
52 if (res_pool->mc_bus != mc_bus) in fsl_mc_resource_pool_add_device()
55 mutex_lock(&res_pool->mutex); in fsl_mc_resource_pool_add_device()
57 if (res_pool->max_count < 0) in fsl_mc_resource_pool_add_device()
59 if (res_pool->free_count < 0 || in fsl_mc_resource_pool_add_device()
60 res_pool->free_count > res_pool->max_count) in fsl_mc_resource_pool_add_device()
75 resource->parent_pool = res_pool; in fsl_mc_resource_pool_add_device()
77 list_add_tail(&resource->node, &res_pool->free_list); in fsl_mc_resource_pool_add_device()
[all …]
/drivers/gpu/drm/amd/display/dc/dcn31/
Ddcn31_hwseq.c68 struct abm **abms = dc->res_pool->multiple_abms; in dcn31_init_hw()
71 struct resource_pool *res_pool = dc->res_pool; in dcn31_init_hw() local
106 if (res_pool->dccg->funcs->dccg_init) in dcn31_init_hw()
107 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn31_init_hw()
128 res_pool->ref_clocks.xtalin_clock_inKhz = in dcn31_init_hw()
132 if (res_pool->dccg && res_pool->hubbub) { in dcn31_init_hw()
134 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn31_init_hw()
136 &res_pool->ref_clocks.dccg_ref_clock_inKhz); in dcn31_init_hw()
138 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, in dcn31_init_hw()
139 res_pool->ref_clocks.dccg_ref_clock_inKhz, in dcn31_init_hw()
[all …]
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_hwseq.c97 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn30_set_mpc_shaper_3dlut()
192 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn30_set_output_transfer_func()
230 ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count); in dcn30_set_writeback()
231 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; in dcn30_set_writeback()
235 dc->res_pool->mpc->funcs->set_dwb_mux(dc->res_pool->mpc, in dcn30_set_writeback()
248 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn30_update_writeback()
270 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst]; in dcn30_mmhubbub_warmup()
284 mcif_wb = dc->res_pool->mcif_wb[0]; in dcn30_mmhubbub_warmup()
299 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst]; in dcn30_mmhubbub_warmup()
300 mcif_wb = dc->res_pool->mcif_wb[wb_info[i].dwb_pipe_inst]; in dcn30_mmhubbub_warmup()
[all …]
Ddcn30_resource.c1469 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_populate_dml_pipes_from_context()
1488 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_populate_dml_writeback_from_context()
1605 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_set_mcif_arb_params()
1767 const struct resource_pool *pool = dc->res_pool; in dcn30_split_stream_for_mpc_or_odm()
1835 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn30_find_split_pipe()
1852 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn30_find_split_pipe()
1883 dc->res_pool->funcs->update_soc_for_wm_a(dc, context); in dcn30_internal_validate_bw()
1884 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); in dcn30_internal_validate_bw()
1931 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_internal_validate_bw()
1951 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_internal_validate_bw()
[all …]
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hwseq.c69 if (dc->res_pool->gsl_groups.gsl_0 == 0) in find_free_gsl_group()
71 if (dc->res_pool->gsl_groups.gsl_1 == 0) in find_free_gsl_group()
73 if (dc->res_pool->gsl_groups.gsl_2 == 0) in find_free_gsl_group()
119 dc->res_pool->gsl_groups.gsl_0 = 1; in dcn20_setup_gsl_group_as_lock()
123 dc->res_pool->gsl_groups.gsl_1 = 1; in dcn20_setup_gsl_group_as_lock()
127 dc->res_pool->gsl_groups.gsl_2 = 1; in dcn20_setup_gsl_group_as_lock()
145 dc->res_pool->gsl_groups.gsl_0 = 0; in dcn20_setup_gsl_group_as_lock()
149 dc->res_pool->gsl_groups.gsl_1 = 0; in dcn20_setup_gsl_group_as_lock()
153 dc->res_pool->gsl_groups.gsl_2 = 0; in dcn20_setup_gsl_group_as_lock()
298 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) { in dcn20_init_blank()
[all …]
Ddcn20_resource.c1675 const struct resource_pool *pool = dc->res_pool; in dcn20_acquire_dsc()
1728 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_add_dsc_to_stream_resource()
1763 dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc); in remove_dsc_from_stream_resource()
1873 const struct resource_pool *pool = dc->res_pool; in dcn20_split_stream_for_odm()
1991 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_pipes_from_context()
2015 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_pipes_from_context()
2033 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; in dcn20_populate_dml_pipes_from_context()
2363 dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes); in dcn20_populate_dml_pipes_from_context()
2410 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_set_mcif_arb_params()
2456 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_validate_dsc()
[all …]
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hw_sequencer.c84 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in print_microsec()
101 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_lock_all_pipes()
142 dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm); in dcn10_log_hubbub_state()
166 struct resource_pool *pool = dc->res_pool; in dcn10_log_hubp_states()
281 struct resource_pool *pool = dc->res_pool; in dcn10_log_hw_state()
691 struct hubp *hubp = dc->res_pool->hubps[0]; in undo_DEGVIDCN10_253_wa()
711 struct hubp *hubp = dc->res_pool->hubps[0]; in apply_DEGVIDCN10_253_wa()
720 for (i = 0; i < dc->res_pool->pipe_count; i++) { in apply_DEGVIDCN10_253_wa()
721 if (!dc->res_pool->hubps[i]->power_gated) in apply_DEGVIDCN10_253_wa()
748 if (dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled) in dcn10_bios_golden_init()
[all …]
Ddcn10_hw_sequencer_debug.c80 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in dcn10_get_hubbub_state()
84 dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm); in dcn10_get_hubbub_state()
112 struct resource_pool *pool = dc->res_pool; in dcn10_get_hubp_states()
118 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in dcn10_get_hubp_states()
190 struct resource_pool *pool = dc->res_pool; in dcn10_get_rq_states()
232 struct resource_pool *pool = dc->res_pool; in dcn10_get_dlg_states()
289 struct resource_pool *pool = dc->res_pool; in dcn10_get_ttu_states()
329 struct resource_pool *pool = dc->res_pool; in dcn10_get_cm_states()
384 struct resource_pool *pool = dc->res_pool; in dcn10_get_mpcc_states()
415 struct resource_pool *pool = dc->res_pool; in dcn10_get_otg_states()
[all …]
/drivers/gpu/drm/amd/display/dc/core/
Ddc_resource.c160 struct resource_pool *res_pool = NULL; in dc_create_resource_pool() local
165 res_pool = dce60_create_resource_pool( in dc_create_resource_pool()
169 res_pool = dce61_create_resource_pool( in dc_create_resource_pool()
173 res_pool = dce64_create_resource_pool( in dc_create_resource_pool()
178 res_pool = dce80_create_resource_pool( in dc_create_resource_pool()
182 res_pool = dce81_create_resource_pool( in dc_create_resource_pool()
186 res_pool = dce83_create_resource_pool( in dc_create_resource_pool()
190 res_pool = dce100_create_resource_pool( in dc_create_resource_pool()
194 res_pool = dce110_create_resource_pool( in dc_create_resource_pool()
200 res_pool = dce112_create_resource_pool( in dc_create_resource_pool()
[all …]
Ddc_link_enc_cfg.c38 for (i = 0; i < stream->ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in is_dig_link_enc_stream()
39 link_enc = stream->ctx->dc->res_pool->link_encoders[i]; in is_dig_link_enc_stream()
101 stream->link_enc = stream->ctx->dc->res_pool->link_encoders[eng_idx]; in update_link_enc_assignment()
121 for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in find_first_avail_link_enc()
162 for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) { in link_enc_cfg_init()
163 if (dc->res_pool->link_encoders[i]) in link_enc_cfg_init()
181 dc->res_pool->funcs->link_enc_unassign(state, streams[i]); in link_enc_cfg_link_encs_assign()
312 link_enc = dc->res_pool->link_encoders[eng_id - ENGINE_ID_DIGA]; in link_enc_cfg_get_next_avail_link_enc()
Ddc.c400 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_stream_forward_dmcu_crc_window()
445 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_stream_stop_dmcu_crc_win_update()
882 dc->res_pool = dc_create_resource_pool(dc, init_params, dc_ctx->dce_version); in dc_construct()
883 if (!dc->res_pool) in dc_construct()
891 dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg); in dc_construct()
897 if (dc->res_pool->funcs->update_bw_bounding_box) { in dc_construct()
899 dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params); in dc_construct()
950 for (i = 0; i < dc->res_pool->pipe_count; i++) { in apply_ctx_interdependent_lock()
975 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_dangling_plane()
1017 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_vbios_mode_if_required()
[all …]
Ddc_link_hwss.c72 struct dmcu *dmcu = dc->res_pool->dmcu; in dp_enable_link_phy()
77 link->dc->res_pool->dp_clock_source; in dp_enable_link_phy()
81 if (link->is_dig_mapping_flexible && dc->res_pool->funcs->link_encs_assign) in dp_enable_link_phy()
208 struct dmcu *dmcu = dc->res_pool->dmcu; in dp_disable_link_phy()
212 if (link->is_dig_mapping_flexible && dc->res_pool->funcs->link_encs_assign) in dp_disable_link_phy()
312 link->dc->res_pool->funcs->link_encs_assign) in dp_set_hw_test_pattern()
Ddc_link.c88 link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = NULL; in dc_link_destruct()
89 link->dc->res_pool->dig_link_enc_count--; in dc_link_destruct()
469 &link->dc->res_pool->audio_support; in link_detect_sink()
711 struct audio_support *audio_support = &link->dc->res_pool->audio_support; in detect_dp()
828 struct audio_support *aud_support = &link->dc->res_pool->audio_support; in dc_link_detect_helper()
1434 if (link->dc->res_pool->funcs->link_init) in dc_link_construct()
1435 link->dc->res_pool->funcs->link_init(link); in dc_link_construct()
1515 if (link->dc->res_pool->funcs->panel_cntl_create && in dc_link_construct()
1522 link->dc->res_pool->funcs->panel_cntl_create( in dc_link_construct()
1544 link->dc->res_pool->funcs->link_enc_create(&enc_init_data); in dc_link_construct()
[all …]
Ddc_stream.c452 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
472 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
483 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
705 if (dc->res_pool->funcs->add_dsc_to_stream_resource) { in dc_stream_add_dsc_to_resource()
706 return dc->res_pool->funcs->add_dsc_to_stream_resource(dc, state, stream); in dc_stream_add_dsc_to_resource()
Ddc_debug.c314 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; in context_timing_trace()
318 for (i = 0; i < dc->res_pool->pipe_count; i++) { in context_timing_trace()
330 for (i = 0; i < dc->res_pool->pipe_count; i++) { in context_timing_trace()
Ddc_surface.c150 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
162 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_hw_sequencer.c211 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; in dce110_enable_display_power_gating()
1547 for (i = 0; i < dc->res_pool->stream_enc_count; i++) { in power_down_encoders()
1548 dc->res_pool->stream_enc[i]->funcs->dp_blank( in power_down_encoders()
1549 dc->res_pool->stream_enc[i]); in power_down_encoders()
1576 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { in power_down_controllers()
1577 dc->res_pool->timing_generators[i]->funcs->disable_crtc( in power_down_controllers()
1578 dc->res_pool->timing_generators[i]); in power_down_controllers()
1586 if (dc->res_pool->dp_clock_source->funcs->cs_power_down( in power_down_clock_sources()
1587 dc->res_pool->dp_clock_source) == false) in power_down_clock_sources()
1590 for (i = 0; i < dc->res_pool->clk_src_count; i++) { in power_down_clock_sources()
[all …]
/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_hwseq.c83 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); in dcn21_init_sys_ctx()
168 struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu; in dcn21_set_abm_immediate_disable()
187 struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu; in dcn21_set_pipe()
208 if (dc->dc->res_pool->dmcu) { in dcn21_set_backlight_level()
237 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn21_is_abm_supported()
Ddcn21_resource.c1113 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn21_calculate_wm()
1117 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; in dcn21_calculate_wm()
1142 if (dc->res_pool->funcs->populate_dml_pipes) in dcn21_calculate_wm()
1143 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, in dcn21_calculate_wm()
1201 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); in dcn21_fast_validate_bw()
1235 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn21_fast_validate_bw()
1259 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { in dcn21_fast_validate_bw()
1269 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); in dcn21_fast_validate_bw()
1288 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); in dcn21_fast_validate_bw()
1302 &context->res_ctx, dc->res_pool, in dcn21_fast_validate_bw()
[all …]
/drivers/gpu/drm/amd/display/dc/
Ddc_edid_parser.c35 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_send_cea()
52 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_recv_cea_ack()
68 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_recv_amd_vsdb()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
Ddcn20_clk_mgr.c109 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dpp_dto()
143 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dentist()
146 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn20_update_clocks_update_dentist()
174 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dentist()
176 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn20_update_clocks_update_dentist()
220 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; in dcn2_update_clocks()
238 if (dc->res_pool->pp_smu) in dcn2_update_clocks()
239 pp_smu = &dc->res_pool->pp_smu->nv_funcs; in dcn2_update_clocks()
/drivers/gpu/drm/amd/display/dc/dce100/
Ddce100_hw_sequencer.c112 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); in dce100_prepare_bandwidth()
124 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); in dce100_optimize_bandwidth()
/drivers/gpu/drm/amd/display/modules/power/
Dpower_helpers.c662 bool dmub_init_abm_config(struct resource_pool *res_pool, in dmub_init_abm_config() argument
673 if (res_pool->abm == NULL && res_pool->multiple_abms[inst] == NULL) in dmub_init_abm_config()
676 if (res_pool->abm == NULL) in dmub_init_abm_config()
732 if (res_pool->multiple_abms[inst]) { in dmub_init_abm_config()
733 result = res_pool->multiple_abms[inst]->funcs->init_abm_config( in dmub_init_abm_config()
734 res_pool->multiple_abms[inst], (char *)(&config), sizeof(struct abm_config_table), inst); in dmub_init_abm_config()
737 result = res_pool->abm->funcs->init_abm_config( in dmub_init_abm_config()
738 res_pool->abm, (char *)(&config), sizeof(struct abm_config_table), 0); in dmub_init_abm_config()
/drivers/gpu/drm/amd/display/dc/dce60/
Ddce60_hw_sequencer.c57 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; in dce60_should_enable_fbc()
70 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_should_enable_fbc()
86 if (i == dc->res_pool->pipe_count) in dce60_should_enable_fbc()
395 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_apply_ctx_for_surface()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/
Ddce112_clk_mgr.c76 struct dmcu *dmcu = dc->res_pool->dmcu; in dce112_set_clock()
131 struct dmcu *dmcu = dc->res_pool->dmcu; in dce112_set_dispclk()

123