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Searched refs:rmmio (Results 1 – 17 of 17) sorted by relevance

/drivers/gpu/drm/mgag200/
Dmgag200_drv.h36 #define RREG8(reg) ioread8(((void __iomem *)mdev->rmmio) + (reg))
37 #define WREG8(reg, v) iowrite8(v, ((void __iomem *)mdev->rmmio) + (reg))
38 #define RREG32(reg) ioread32(((void __iomem *)mdev->rmmio) + (reg))
39 #define WREG32(reg, v) iowrite32(v, ((void __iomem *)mdev->rmmio) + (reg))
218 void __iomem *rmmio; member
Dmgag200_drv.c119 mdev->rmmio = pcim_iomap(pdev, 1, 0); in mgag200_regs_init()
120 if (mdev->rmmio == NULL) in mgag200_regs_init()
/drivers/gpu/drm/amd/amdgpu/
Damdgpu_device.c466 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); in amdgpu_device_rreg()
497 return (readb(adev->rmmio + offset)); in amdgpu_mm_rreg8()
522 writeb(value, adev->rmmio + offset); in amdgpu_mm_wreg8()
551 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); in amdgpu_device_wreg()
577 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); in amdgpu_mm_wreg_mmio_rlc()
689 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; in amdgpu_device_indirect_rreg()
690 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; in amdgpu_device_indirect_rreg()
720 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; in amdgpu_device_indirect_rreg64()
721 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; in amdgpu_device_indirect_rreg64()
755 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; in amdgpu_device_indirect_wreg()
[all …]
Damdgpu_kms.c98 if (adev->rmmio == NULL) in amdgpu_driver_unload_kms()
278 if (adev->rmmio && adev->runpm) in amdgpu_driver_load_kms()
Dgfx_v9_0.c752 …scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_RE… in gfx_v9_0_rlcg_w()
753 …scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_RE… in gfx_v9_0_rlcg_w()
754 …scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_RE… in gfx_v9_0_rlcg_w()
755 …scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_RE… in gfx_v9_0_rlcg_w()
756 …spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_IN… in gfx_v9_0_rlcg_w()
772 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4)); in gfx_v9_0_rlcg_w()
Damdgpu.h850 void __iomem *rmmio; member
Dgfx_v10_0.c1531 scratch_reg0 = adev->rmmio + in gfx_v10_rlcg_rw()
1533 scratch_reg1 = adev->rmmio + in gfx_v10_rlcg_rw()
1535 scratch_reg2 = adev->rmmio + in gfx_v10_rlcg_rw()
1537 scratch_reg3 = adev->rmmio + in gfx_v10_rlcg_rw()
1541 spare_int = adev->rmmio + in gfx_v10_rlcg_rw()
1545 spare_int = adev->rmmio + in gfx_v10_rlcg_rw()
1558 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4)); in gfx_v10_rlcg_rw()
/drivers/gpu/drm/radeon/
Dradeon_device.c1414 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); in radeon_device_init()
1415 if (rdev->rmmio == NULL) in radeon_device_init()
1539 iounmap(rdev->rmmio); in radeon_device_fini()
1540 rdev->rmmio = NULL; in radeon_device_fini()
Dradeon.h2390 void __iomem *rmmio; member
2504 return readl(((void __iomem *)rdev->rmmio) + reg); in r100_mm_rreg()
2512 writel(v, ((void __iomem *)rdev->rmmio) + reg); in r100_mm_wreg()
2541 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2542 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2543 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2544 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
Dradeon_kms.c69 if (rdev->rmmio == NULL) in radeon_driver_unload_kms()
Dr100.c4105 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); in r100_mm_rreg_slow()
4106 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); in r100_mm_rreg_slow()
4116 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); in r100_mm_wreg_slow()
4117 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); in r100_mm_wreg_slow()
/drivers/gpu/drm/vmwgfx/
Dvmwgfx_drv.h494 u32 __iomem *rmmio; member
680 iowrite32(value, dev_priv->rmmio + offset); in vmw_write()
695 val = ioread32(dev_priv->rmmio + offset); in vmw_read()
Dvmwgfx_drv.c747 dev->rmmio = devm_ioremap(dev->drm.dev, in vmw_setup_pci_resources()
750 if (!dev->rmmio) { in vmw_setup_pci_resources()
/drivers/misc/habanalabs/common/
Ddevice.c1669 return readl(hdev->rmmio + reg); in hl_rreg()
1684 writel(val, hdev->rmmio + reg); in hl_wreg()
Dhabanalabs.h2469 void __iomem *rmmio; member
/drivers/misc/habanalabs/goya/
Dgoya.c496 hdev->rmmio = hdev->pcie_bar[SRAM_CFG_BAR_ID] + in goya_pci_bars_map()
/drivers/misc/habanalabs/gaudi/
Dgaudi.c677 hdev->rmmio = hdev->pcie_bar[CFG_BAR_ID] + in gaudi_pci_bars_map()