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Searched refs:sec2 (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/nouveau/nvkm/engine/sec2/
Dbase.c30 struct nvkm_sec2 *sec2 = container_of(work, typeof(*sec2), work); in nvkm_sec2_recv() local
32 if (!sec2->initmsg_received) { in nvkm_sec2_recv()
33 int ret = sec2->func->initmsg(sec2); in nvkm_sec2_recv()
35 nvkm_error(&sec2->engine.subdev, in nvkm_sec2_recv()
40 sec2->initmsg_received = true; in nvkm_sec2_recv()
43 nvkm_falcon_msgq_recv(sec2->msgq); in nvkm_sec2_recv()
49 struct nvkm_sec2 *sec2 = nvkm_sec2(engine); in nvkm_sec2_intr() local
50 sec2->func->intr(sec2); in nvkm_sec2_intr()
56 struct nvkm_sec2 *sec2 = nvkm_sec2(engine); in nvkm_sec2_fini() local
58 flush_work(&sec2->work); in nvkm_sec2_fini()
[all …]
Dgp102.c32 gp102_sec2_nofw(struct nvkm_sec2 *sec2, int ver, in gp102_sec2_nofw() argument
35 nvkm_warn(&sec2->engine.subdev, "firmware unavailable\n"); in gp102_sec2_nofw()
62 struct nvkm_sec2 *sec2 = container_of(falcon, typeof(*sec2), falcon); in gp102_sec2_acr_bootstrap_falcon() local
64 .cmd.hdr.unit_id = sec2->func->unit_acr, in gp102_sec2_acr_bootstrap_falcon()
71 return nvkm_falcon_cmdq_send(sec2->cmdq, &cmd.cmd.hdr, in gp102_sec2_acr_bootstrap_falcon()
73 &sec2->engine.subdev, in gp102_sec2_acr_bootstrap_falcon()
133 gp102_sec2_initmsg(struct nvkm_sec2 *sec2) in gp102_sec2_initmsg() argument
138 ret = nvkm_falcon_msgq_recv_initmsg(sec2->msgq, &msg, sizeof(msg)); in gp102_sec2_initmsg()
148 nvkm_falcon_msgq_init(sec2->msgq, in gp102_sec2_initmsg()
153 nvkm_falcon_cmdq_init(sec2->cmdq, in gp102_sec2_initmsg()
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DKbuild2 nvkm-y += nvkm/engine/sec2/base.o
3 nvkm-y += nvkm/engine/sec2/gp102.o
4 nvkm-y += nvkm/engine/sec2/gp108.o
5 nvkm-y += nvkm/engine/sec2/tu102.o
/drivers/crypto/hisilicon/
DMakefile4 obj-$(CONFIG_CRYPTO_DEV_HISI_SEC2) += sec2/
/drivers/gpu/drm/nouveau/nvkm/engine/
DKbuild22 include $(src)/nvkm/engine/sec2/Kbuild
/drivers/rtc/
Drtc-sh.c277 unsigned int sec128, sec2, yr, yr100, cf_bit; in sh_rtc_read_time() local
312 sec2 = readb(rtc->regbase + R64CNT); in sh_rtc_read_time()
316 } while (cf_bit != 0 || ((sec128 ^ sec2) & RTC_BIT_INVERTED) != 0); in sh_rtc_read_time()
/drivers/gpu/drm/nouveau/nvkm/engine/device/
Dbase.c2202 .sec2 = { 0x00000001, gp102_sec2_new },
2236 .sec2 = { 0x00000001, gp102_sec2_new },
2270 .sec2 = { 0x00000001, gp102_sec2_new },
2304 .sec2 = { 0x00000001, gp102_sec2_new },
2337 .sec2 = { 0x00000001, gp108_sec2_new },
2396 .sec2 = { 0x00000001, gp108_sec2_new },
2430 .sec2 = { 0x00000001, tu102_sec2_new },
2464 .sec2 = { 0x00000001, tu102_sec2_new },
2498 .sec2 = { 0x00000001, tu102_sec2_new },
2532 .sec2 = { 0x00000001, tu102_sec2_new },
[all …]
/drivers/gpu/drm/nouveau/include/nvkm/core/
Dlayout.h50 NVKM_LAYOUT_ONCE(NVKM_ENGINE_SEC2 , struct nvkm_sec2 , sec2)
/drivers/gpu/drm/nouveau/nvkm/subdev/acr/
Dgp102.c212 &acr->subdev.device->sec2->falcon); in gp102_acr_load_load()
/drivers/md/
Ddm-integrity.c2475 sector_t sec2, area2, offset2; in do_journal_write() local
2479 sec2 = journal_entry_get_sector(je2); in do_journal_write()
2480 if (unlikely(sec2 >= ic->provided_data_sectors)) in do_journal_write()
2482 get_area_and_offset(ic, sec2, &area2, &offset2); in do_journal_write()