Home
last modified time | relevance | path

Searched refs:smac_15_0 (Results 1 – 12 of 12) sorted by relevance

/drivers/net/ethernet/mellanox/mlx5/core/esw/acl/
Dingress_lgcy.c38 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_15_0); in esw_acl_ingress_lgcy_groups_create()
71 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_15_0); in esw_acl_ingress_lgcy_groups_create()
236 outer_headers.smac_15_0); in esw_acl_ingress_lgcy_setup()
/drivers/net/ethernet/mellanox/mlx5/core/steering/
Ddr_ste_v0.c709 if (mask->smac_47_16 || mask->smac_15_0) { in dr_ste_v0_build_eth_l2_src_dst_bit_mask()
713 mask->smac_47_16 << 16 | mask->smac_15_0); in dr_ste_v0_build_eth_l2_src_dst_bit_mask()
715 mask->smac_15_0 = 0; in dr_ste_v0_build_eth_l2_src_dst_bit_mask()
742 if (spec->smac_47_16 || spec->smac_15_0) { in dr_ste_v0_build_eth_l2_src_dst_tag()
746 spec->smac_47_16 << 16 | spec->smac_15_0); in dr_ste_v0_build_eth_l2_src_dst_tag()
748 spec->smac_15_0 = 0; in dr_ste_v0_build_eth_l2_src_dst_tag()
996 DR_STE_SET_TAG(eth_l2_src, bit_mask, smac_15_0, mask, smac_15_0); in dr_ste_v0_build_eth_l2_src_bit_mask()
1009 DR_STE_SET_TAG(eth_l2_src, tag, smac_15_0, spec, smac_15_0); in dr_ste_v0_build_eth_l2_src_tag()
Dmlx5_ifc_dr_ste_v1.h185 u8 smac_15_0[0x10]; member
252 u8 smac_15_0[0x10]; member
Ddr_ste_v1.c925 DR_STE_SET_TAG(eth_l2_src_dst_v1, bit_mask, smac_15_0, mask, smac_15_0); in dr_ste_v1_build_eth_l2_src_dst_bit_mask()
951 DR_STE_SET_TAG(eth_l2_src_dst_v1, tag, smac_15_0, spec, smac_15_0); in dr_ste_v1_build_eth_l2_src_dst_tag()
1184 DR_STE_SET_TAG(eth_l2_src_v1, bit_mask, smac_15_0, mask, smac_15_0); in dr_ste_v1_build_eth_l2_src_bit_mask()
1196 DR_STE_SET_TAG(eth_l2_src_v1, tag, smac_15_0, spec, smac_15_0); in dr_ste_v1_build_eth_l2_src_tag()
Dmlx5_ifc_dr.h154 u8 smac_15_0[0x10]; member
Ddr_ste.c759 spec->smac_15_0 = MLX5_GET(fte_match_set_lyr_2_4, mask, smac_15_0); in dr_ste_copy_mask_spec()
Ddr_matcher.c8 return (spec->smac_47_16 || spec->smac_15_0); in dr_mask_is_smac_set()
Ddr_types.h498 u32 smac_15_0:16; /* Source MAC address of incoming packet */ member
/drivers/net/ethernet/mellanox/mlx5/core/diag/
Dfs_tracepoint.c70 MLX5_GET(fte_match_set_lyr_2_4, mask, smac_15_0), in print_lyr_2_4_hdrs()
72 MLX5_GET(fte_match_set_lyr_2_4, value, smac_15_0)}; in print_lyr_2_4_hdrs()
/drivers/net/ethernet/mellanox/mlx5/core/esw/
Dbridge.c130 MLX5_SET_TO_ONES(fte_match_param, match, outer_headers.smac_15_0); in mlx5_esw_bridge_ingress_vlan_fg_create()
169 MLX5_SET_TO_ONES(fte_match_param, match, outer_headers.smac_15_0); in mlx5_esw_bridge_ingress_filter_fg_create()
206 MLX5_SET_TO_ONES(fte_match_param, match, outer_headers.smac_15_0); in mlx5_esw_bridge_ingress_mac_fg_create()
/drivers/net/ethernet/mellanox/mlx5/core/fpga/
Dipsec.c650 MLX5_GET(fte_match_set_lyr_2_4, outer_c, smac_15_0); in mlx5_is_fpga_egress_ipsec_rule()
/drivers/net/ethernet/mellanox/mlx5/core/
Den_tc.c2741 OFFLOAD(SMAC_15_0, 16, U16_MAX, eth.h_source[4], 0, smac_15_0),