| /drivers/net/ethernet/mellanox/mlx5/core/esw/acl/ |
| D | ingress_lgcy.c | 37 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_47_16); in esw_acl_ingress_lgcy_groups_create()
70 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_47_16); in esw_acl_ingress_lgcy_groups_create()
234 outer_headers.smac_47_16); in esw_acl_ingress_lgcy_setup()
239 outer_headers.smac_47_16); in esw_acl_ingress_lgcy_setup()
|
| /drivers/net/ethernet/mellanox/mlx5/core/steering/ |
| D | dr_ste_v0.c | 709 if (mask->smac_47_16 || mask->smac_15_0) { in dr_ste_v0_build_eth_l2_src_dst_bit_mask()
711 mask->smac_47_16 >> 16); in dr_ste_v0_build_eth_l2_src_dst_bit_mask()
713 mask->smac_47_16 << 16 | mask->smac_15_0); in dr_ste_v0_build_eth_l2_src_dst_bit_mask()
714 mask->smac_47_16 = 0; in dr_ste_v0_build_eth_l2_src_dst_bit_mask()
742 if (spec->smac_47_16 || spec->smac_15_0) { in dr_ste_v0_build_eth_l2_src_dst_tag()
744 spec->smac_47_16 >> 16); in dr_ste_v0_build_eth_l2_src_dst_tag()
746 spec->smac_47_16 << 16 | spec->smac_15_0); in dr_ste_v0_build_eth_l2_src_dst_tag()
747 spec->smac_47_16 = 0; in dr_ste_v0_build_eth_l2_src_dst_tag()
995 DR_STE_SET_TAG(eth_l2_src, bit_mask, smac_47_16, mask, smac_47_16); in dr_ste_v0_build_eth_l2_src_bit_mask()
1008 DR_STE_SET_TAG(eth_l2_src, tag, smac_47_16, spec, smac_47_16); in dr_ste_v0_build_eth_l2_src_tag()
|
| D | mlx5_ifc_dr_ste_v1.h | 183 u8 smac_47_16[0x20]; member
238 u8 smac_47_16[0x20]; member
|
| D | dr_ste_v1.c | 924 DR_STE_SET_TAG(eth_l2_src_dst_v1, bit_mask, smac_47_16, mask, smac_47_16); in dr_ste_v1_build_eth_l2_src_dst_bit_mask()
950 DR_STE_SET_TAG(eth_l2_src_dst_v1, tag, smac_47_16, spec, smac_47_16); in dr_ste_v1_build_eth_l2_src_dst_tag()
1183 DR_STE_SET_TAG(eth_l2_src_v1, bit_mask, smac_47_16, mask, smac_47_16); in dr_ste_v1_build_eth_l2_src_bit_mask()
1195 DR_STE_SET_TAG(eth_l2_src_v1, tag, smac_47_16, spec, smac_47_16); in dr_ste_v1_build_eth_l2_src_tag()
|
| D | mlx5_ifc_dr.h | 152 u8 smac_47_16[0x20]; member
|
| D | dr_ste.c | 757 spec->smac_47_16 = MLX5_GET(fte_match_set_lyr_2_4, mask, smac_47_16); in dr_ste_copy_mask_spec()
|
| D | dr_matcher.c | 8 return (spec->smac_47_16 || spec->smac_15_0); in dr_mask_is_smac_set()
|
| D | dr_types.h | 493 u32 smac_47_16; /* Source MAC address of incoming packet */ member
|
| /drivers/net/ethernet/mellanox/mlx5/core/esw/ |
| D | bridge.c | 129 MLX5_SET_TO_ONES(fte_match_param, match, outer_headers.smac_47_16); in mlx5_esw_bridge_ingress_vlan_fg_create()
168 MLX5_SET_TO_ONES(fte_match_param, match, outer_headers.smac_47_16); in mlx5_esw_bridge_ingress_filter_fg_create()
205 MLX5_SET_TO_ONES(fte_match_param, match, outer_headers.smac_47_16); in mlx5_esw_bridge_ingress_mac_fg_create()
434 outer_headers.smac_47_16); in mlx5_esw_bridge_ingress_flow_with_esw_create()
437 outer_headers.smac_47_16); in mlx5_esw_bridge_ingress_flow_with_esw_create()
524 outer_headers.smac_47_16); in mlx5_esw_bridge_ingress_filter_flow_create()
527 outer_headers.smac_47_16); in mlx5_esw_bridge_ingress_filter_flow_create()
|
| /drivers/net/ethernet/mellanox/mlx5/core/diag/ |
| D | fs_tracepoint.c | 69 .m = MLX5_GET(fte_match_set_lyr_2_4, mask, smac_47_16) << 16 | in print_lyr_2_4_hdrs()
71 .v = MLX5_GET(fte_match_set_lyr_2_4, value, smac_47_16) << 16 | in print_lyr_2_4_hdrs()
|
| /drivers/net/ethernet/mellanox/mlx5/core/ |
| D | en_fs_ethtool.c | 308 ether_addr_copy(MLX5E_FTE_ADDR_OF(headers_c, smac_47_16), eth_mask->h_source); in parse_ether()
309 ether_addr_copy(MLX5E_FTE_ADDR_OF(headers_v, smac_47_16), eth_val->h_source); in parse_ether()
|
| D | en_tc.c | 2364 smac_47_16), in __parse_cls_flower()
2367 smac_47_16), in __parse_cls_flower()
2740 OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16),
|
| /drivers/infiniband/hw/mlx5/ |
| D | fs.c | 244 smac_47_16), in parse_flow_attr()
247 smac_47_16), in parse_flow_attr()
|
| /drivers/net/ethernet/mellanox/mlx5/core/fpga/ |
| D | ipsec.c | 649 bool is_smac = MLX5_GET(fte_match_set_lyr_2_4, outer_c, smac_47_16) || in mlx5_is_fpga_egress_ipsec_rule()
|