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Searched refs:sr_enter_plus_exit_time_us (Results 1 – 22 of 22) sorted by relevance

/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
Drn_clk_mgr.c625 .sr_enter_plus_exit_time_us = 8.14,
633 .sr_enter_plus_exit_time_us = 11.48,
641 .sr_enter_plus_exit_time_us = 11.48,
649 .sr_enter_plus_exit_time_us = 11.48,
662 .sr_enter_plus_exit_time_us = 6.38,
670 .sr_enter_plus_exit_time_us = 11.196,
678 .sr_enter_plus_exit_time_us = 11.24,
686 .sr_enter_plus_exit_time_us = 11.102,
699 .sr_enter_plus_exit_time_us = 9.38,
707 .sr_enter_plus_exit_time_us = 11.196,
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
Ddcn31_clk_mgr.c339 .sr_enter_plus_exit_time_us = 11,
347 .sr_enter_plus_exit_time_us = 11,
355 .sr_enter_plus_exit_time_us = 11,
363 .sr_enter_plus_exit_time_us = 11,
376 .sr_enter_plus_exit_time_us = 14.5,
384 .sr_enter_plus_exit_time_us = 14.5,
392 .sr_enter_plus_exit_time_us = 14.5,
400 .sr_enter_plus_exit_time_us = 14.5,
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
Ddcn30_clk_mgr.c112 double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us; in dcn3_build_wm_range_table() local
119 …e.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_t… in dcn3_build_wm_range_table()
141 …e.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_t… in dcn3_build_wm_range_table()
152 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = 4; in dcn3_build_wm_range_table()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
Dvg_clk_mgr.c549 .sr_enter_plus_exit_time_us = 7.14,
557 .sr_enter_plus_exit_time_us = 11.48,
565 .sr_enter_plus_exit_time_us = 11.48,
573 .sr_enter_plus_exit_time_us = 11.48,
586 .sr_enter_plus_exit_time_us = 16.5,
594 .sr_enter_plus_exit_time_us = 16.5,
602 .sr_enter_plus_exit_time_us = 16.5,
610 .sr_enter_plus_exit_time_us = 16.5,
/drivers/gpu/drm/amd/display/dc/inc/hw/
Dclk_mgr.h108 double sr_enter_plus_exit_time_us; member
126 double sr_enter_plus_exit_time_us; member
/drivers/gpu/drm/amd/amdgpu/
Damdgpu_socbb.h40 uint32_t sr_enter_plus_exit_time_us; member
/drivers/gpu/drm/amd/display/dc/dcn31/
Ddcn31_resource.c219 .sr_enter_plus_exit_time_us = 11.0,
1654 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A… in dcn31_update_soc_for_wm_a()
1694 …xt->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].… in dcn31_calculate_wm_and_dlg_fp()
1716 …xt->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].… in dcn31_calculate_wm_and_dlg_fp()
1735 …xt->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].… in dcn31_calculate_wm_and_dlg_fp()
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_resource.c185 .sr_enter_plus_exit_time_us = 20,
1749 dcn3_0_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10; in init_soc_bounding_box()
2152 …xt->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].… in dcn30_calculate_wm_and_dlg_fp()
2206 …xt->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].… in dcn30_calculate_wm_and_dlg_fp()
2278 …xt->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].… in dcn30_update_soc_for_wm_a()
/drivers/gpu/drm/amd/display/dc/dml/
Ddisplay_mode_structs.h76 double sr_enter_plus_exit_time_us; member
Ddml1_display_rq_dlg_calc.c1305 line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait); in dml1_rq_dlg_get_dlg_params()
1320 (double) mode_lib->soc.sr_enter_plus_exit_time_us); in dml1_rq_dlg_get_dlg_params()
Ddisplay_mode_vba.c233 mode_lib->vba.SREnterPlusExitTime = soc->sr_enter_plus_exit_time_us; in fetch_socbb_params()
/drivers/gpu/drm/amd/display/dc/dcn301/
Ddcn301_resource.c230 .sr_enter_plus_exit_time_us = 11.0,
1521 dcn3_01_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10; in init_soc_bounding_box()
1647 dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us; in calculate_wm_set_for_vlevel()
/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_resource.c272 .sr_enter_plus_exit_time_us = 17.0,
1052 dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us; in calculate_wm_set_for_vlevel()
1079 dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us = in patch_bounding_box()
/drivers/gpu/drm/amd/display/dc/calcs/
Ddcn_calcs.c1094 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time; in dcn_validate_bandwidth()
1310 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = in dcn_validate_bandwidth()
1752 dc->dml.soc.sr_enter_plus_exit_time_us = dc->dcn_soc->sr_enter_plus_exit_time; in dcn_bw_sync_calcs_and_dml()
/drivers/gpu/drm/amd/display/dc/dcn302/
Ddcn302_resource.c168 .sr_enter_plus_exit_time_us = 31,
1120 dcn3_02_soc.sr_enter_plus_exit_time_us = in init_soc_bounding_box()
/drivers/gpu/drm/amd/display/dc/dcn303/
Ddcn303_resource.c150 .sr_enter_plus_exit_time_us = 40,
1046 dcn3_03_soc.sr_enter_plus_exit_time_us = in init_soc_bounding_box()
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_resource.c303 .sr_enter_plus_exit_time_us = 10.9,
414 .sr_enter_plus_exit_time_us = 13.9,
3580 if ((int)(bb->sr_enter_plus_exit_time_us * 1000) in dcn20_patch_bounding_box()
3583 bb->sr_enter_plus_exit_time_us = in dcn20_patch_bounding_box()
/drivers/gpu/drm/amd/display/dc/dml/dcn20/
Ddisplay_rq_dlg_calc_20v2.c1092 line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait); in dml20v2_rq_dlg_get_dlg_params()
Ddisplay_rq_dlg_calc_20.c1091 line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait); in dml20_rq_dlg_get_dlg_params()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_resource.c115 .sr_enter_plus_exit_time_us = 11.0,
/drivers/gpu/drm/amd/display/dc/dml/dcn21/
Ddisplay_rq_dlg_calc_21.c1138 line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait); in dml_rq_dlg_get_dlg_params()
/drivers/gpu/drm/amd/display/dc/dml/dcn30/
Ddisplay_rq_dlg_calc_30.c1331 line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait); in dml_rq_dlg_get_dlg_params()