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Searched refs:src_w (Results 1 – 25 of 86) sorted by relevance

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/drivers/media/platform/ti-vpe/
Dsc.c61 void sc_set_hs_coeffs(struct sc_data *sc, void *addr, unsigned int src_w, in sc_set_hs_coeffs() argument
70 if (dst_w > src_w) { in sc_set_hs_coeffs()
73 if ((dst_w << 1) < src_w) in sc_set_hs_coeffs()
75 if ((dst_w << 1) < src_w) in sc_set_hs_coeffs()
78 if (dst_w == src_w) { in sc_set_hs_coeffs()
81 sixteenths = (dst_w << 4) / src_w; in sc_set_hs_coeffs()
148 u32 *sc_reg17, unsigned int src_w, unsigned int src_h, in sc_config_scaler() argument
178 if (src_w == dst_w && src_h == dst_h) { in sc_config_scaler()
190 dcm_x = src_w / dst_w; in sc_config_scaler()
202 lin_acc_inc = div64_u64(((u64)(src_w >> dcm_shift) - 1) << 24, lltmp); in sc_config_scaler()
[all …]
/drivers/media/pci/ivtv/
Divtv-yuv.c224 f->tru_w, f->src_w, f->dst_w, f->src_x, f->dst_x); in ivtv_yuv_handle_horizontal()
227 x_cutoff = f->src_w + f->src_x; in ivtv_yuv_handle_horizontal()
251 if (f->dst_w >= f->src_w) in ivtv_yuv_handle_horizontal()
257 if (f->dst_w < f->src_w) in ivtv_yuv_handle_horizontal()
263 reg_2870_offset = (f->src_x * ((f->dst_w << 21) / f->src_w)) >> 19; in ivtv_yuv_handle_horizontal()
265 if (f->dst_w >= f->src_w) { in ivtv_yuv_handle_horizontal()
267 master_width = (f->src_w * 0x00200000) / (f->dst_w); in ivtv_yuv_handle_horizontal()
268 if (master_width * f->dst_w != f->src_w * 0x00200000) in ivtv_yuv_handle_horizontal()
280 if (f->dst_w > f->src_w) in ivtv_yuv_handle_horizontal()
281 reg_2870_base = ((f->dst_w - f->src_w)<<16) / (f->src_w <<14); in ivtv_yuv_handle_horizontal()
[all …]
/drivers/gpu/drm/zte/
Dzx_plane.c150 u32 src_w, u32 src_h, u32 dst_w, u32 dst_h) in zx_vl_rsz_setup() argument
153 u32 src_chroma_w = src_w; in zx_vl_rsz_setup()
158 zx_writel(rsz + RSZ_SRC_CFG, RSZ_VER(src_h - 1) | RSZ_HOR(src_w - 1)); in zx_vl_rsz_setup()
168 src_chroma_w = src_w >> 1; in zx_vl_rsz_setup()
171 src_chroma_w = src_w >> 1; in zx_vl_rsz_setup()
175 zx_writel(rsz + RSZ_VL_LUMA_HOR, rsz_step_value(src_w, dst_w)); in zx_vl_rsz_setup()
197 u32 src_x, src_y, src_w, src_h; in zx_vl_plane_atomic_update() local
210 src_w = drm_rect_width(src) >> 16; in zx_vl_plane_atomic_update()
230 zx_writel(layer + VL_SRC_SIZE, GL_SRC_W(src_w) | GL_SRC_H(src_h)); in zx_vl_plane_atomic_update()
252 zx_vl_rsz_setup(zplane, format, src_w, src_h, dst_w, dst_h); in zx_vl_plane_atomic_update()
[all …]
/drivers/gpu/drm/msm/disp/mdp4/
Dmdp4_plane.c53 uint32_t src_w, uint32_t src_h);
142 new_state->src_w, new_state->src_h); in mdp4_plane_atomic_update()
214 uint32_t src_w, uint32_t src_h) in mdp4_plane_mode_set() argument
236 src_w = src_w >> 16; in mdp4_plane_mode_set()
240 fb->base.id, src_x, src_y, src_w, src_h, in mdp4_plane_mode_set()
245 if (src_w > (crtc_w * DOWN_SCALE_MAX)) { in mdp4_plane_mode_set()
255 if (crtc_w > (src_w * UP_SCALE_MAX)) { in mdp4_plane_mode_set()
265 if (src_w != crtc_w) { in mdp4_plane_mode_set()
270 if (crtc_w > src_w) in mdp4_plane_mode_set()
272 else if (crtc_w <= (src_w / 4)) in mdp4_plane_mode_set()
[all …]
/drivers/gpu/drm/armada/
Darmada_trace.h34 uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h),
35 TP_ARGS(plane, crtc, fb, crtc_x, crtc_y, crtc_w, crtc_h, src_x, src_y, src_w, src_h),
46 __field(u32, src_w)
59 __entry->src_w = src_w;
67 __entry->src_w >> 16, __entry->src_h >> 16)
/drivers/gpu/drm/imx/dcss/
Ddcss-plane.c126 static bool dcss_plane_is_source_size_allowed(u16 src_w, u16 src_h, u32 pix_fmt) in dcss_plane_is_source_size_allowed() argument
128 if (src_w < 64 && in dcss_plane_is_source_size_allowed()
131 else if (src_w < 32 && in dcss_plane_is_source_size_allowed()
136 return src_w >= 16 && src_h >= 8; in dcss_plane_is_source_size_allowed()
166 if (!dcss_plane_is_source_size_allowed(new_plane_state->src_w >> 16, in dcss_plane_atomic_check()
258 state->src_w != old_state->src_w || in dcss_plane_needs_setup()
278 u32 src_w, src_h, dst_w, dst_h; in dcss_plane_atomic_update() local
301 src_w = drm_rect_width(&src) >> 16; in dcss_plane_atomic_update()
314 dcss_dpr_set_res(dcss->dpr, dcss_plane->ch_num, src_w, src_h); in dcss_plane_atomic_update()
328 is_rotation_90_or_270 ? src_h : src_w, in dcss_plane_atomic_update()
[all …]
/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_plane.c201 if (state->src_w > max_width) { in mdp5_plane_atomic_check_with_state()
208 (state->src_w <= 2 * max_width)) in mdp5_plane_atomic_check_with_state()
240 if (((state->src_w >> 16) != state->crtc_w) || in mdp5_plane_atomic_check_with_state()
276 state->src_w >> 16, false); in mdp5_plane_atomic_check_with_state()
407 plane->state->src_w != new_plane_state->src_w || in mdp5_plane_atomic_async_check()
691 uint32_t src_w, int pe_left[COMP_MAX], int pe_right[COMP_MAX], in mdp5_write_pixel_ext() argument
699 uint32_t roi_w = src_w; in mdp5_write_pixel_ext()
772 u32 src_w, u32 src_h) in mdp5_hwpipe_mode_set() argument
784 MDP5_PIPE_SRC_SIZE_WIDTH(src_w) | in mdp5_hwpipe_mode_set()
828 src_w, pe->left, pe->right, in mdp5_hwpipe_mode_set()
[all …]
/drivers/gpu/drm/sti/
Dsti_hqvdp.c480 int src_w, src_h, dst_w, dst_h; in hqvdp_dbg_dump_cmd() local
512 src_w = c->top.input_viewport_size & 0x0000FFFF; in hqvdp_dbg_dump_cmd()
514 seq_printf(s, "\t%dx%d", src_w, src_h); in hqvdp_dbg_dump_cmd()
534 if (dst_w > src_w) in hqvdp_dbg_dump_cmd()
535 seq_printf(s, " %d/1", dst_w / src_w); in hqvdp_dbg_dump_cmd()
537 seq_printf(s, " 1/%d", src_w / dst_w); in hqvdp_dbg_dump_cmd()
734 int src_w, int src_h, in sti_hqvdp_check_hw_scaling() argument
741 lfw /= max(src_w, dst_w) * mode->clock / 1000; in sti_hqvdp_check_hw_scaling()
1031 int src_x, src_y, src_w, src_h; in sti_hqvdp_atomic_check() local
1046 src_w = new_plane_state->src_w >> 16; in sti_hqvdp_atomic_check()
[all …]
Dsti_cursor.c195 int src_w, src_h; in sti_cursor_atomic_check() local
210 src_w = new_plane_state->src_w >> 16; in sti_cursor_atomic_check()
213 if (src_w < STI_CURS_MIN_SIZE || in sti_cursor_atomic_check()
215 src_w > STI_CURS_MAX_SIZE || in sti_cursor_atomic_check()
218 src_w, src_h); in sti_cursor_atomic_check()
224 (cursor->width != src_w) || in sti_cursor_atomic_check()
226 cursor->width = src_w; in sti_cursor_atomic_check()
Dsti_gdp.c630 int src_x, src_y, src_w, src_h; in sti_gdp_atomic_check() local
647 src_w = clamp_val(new_plane_state->src_w >> 16, 0, in sti_gdp_atomic_check()
696 src_w, src_h, src_x, src_y); in sti_gdp_atomic_check()
714 int src_x, src_y, src_w, src_h; in sti_gdp_atomic_update() local
735 (oldstate->src_w == newstate->src_w) && in sti_gdp_atomic_update()
761 src_w = clamp_val(newstate->src_w >> 16, 0, GAM_GDP_SIZE_MAX_WIDTH); in sti_gdp_atomic_update()
792 dst_w = sti_gdp_get_dst(gdp->dev, dst_w, src_w); in sti_gdp_atomic_update()
802 src_w = dst_w; in sti_gdp_atomic_update()
804 top_field->gam_gdp_size = src_h << 16 | src_w; in sti_gdp_atomic_update()
/drivers/gpu/drm/nouveau/dispnv04/
Doverlay.c94 uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h, in verify_scaling() argument
97 if (crtc_w < (src_w >> shift) || crtc_h < (src_h >> shift)) { in verify_scaling()
99 src_w, src_h, crtc_w, crtc_h); in verify_scaling()
117 uint32_t src_w, uint32_t src_h, in nv10_update_plane() argument
137 src_w >>= 16; in nv10_update_plane()
140 ret = verify_scaling(fb, shift, 0, 0, src_w, src_h, crtc_w, crtc_h); in nv10_update_plane()
156 nvif_wr32(dev, NV_PVIDEO_SIZE_IN(flip), src_h << 16 | src_w); in nv10_update_plane()
158 nvif_wr32(dev, NV_PVIDEO_DS_DX(flip), (src_w << 20) / crtc_w); in nv10_update_plane()
367 uint32_t src_w, uint32_t src_h, in nv04_update_plane() argument
382 src_w >>= 16; in nv04_update_plane()
[all …]
/drivers/media/platform/rockchip/rga/
Drga-hw.c166 unsigned int src_h, src_w, src_x, src_y, dst_h, dst_w, dst_x, dst_y; in rga_cmd_set_trans_info() local
181 src_w = ctx->in.crop.width; in rga_cmd_set_trans_info()
264 if (abs(src_w - dst_h) < 16) in rga_cmd_set_trans_info()
265 src_w -= 16; in rga_cmd_set_trans_info()
275 if (src_w == scale_dst_w) { in rga_cmd_set_trans_info()
278 } else if (src_w > scale_dst_w) { in rga_cmd_set_trans_info()
281 rga_get_scaling(src_w, scale_dst_w) + 1; in rga_cmd_set_trans_info()
285 rga_get_scaling(src_w - 1, scale_dst_w - 1); in rga_cmd_set_trans_info()
309 src_act_info.data.act_width = src_w - 1; in rga_cmd_set_trans_info()
319 src_w, src_h); in rga_cmd_set_trans_info()
/drivers/gpu/drm/sun4i/
Dsun8i_vi_layer.c105 u32 src_w, src_h, dst_w, dst_h; in sun8i_vi_layer_update_coord() local
119 src_w = drm_rect_width(&state->src) >> 16; in sun8i_vi_layer_update_coord()
133 src_w = (src_w + remainder) & ~mask; in sun8i_vi_layer_update_coord()
146 insize = SUN8I_MIXER_SIZE(src_w, src_h); in sun8i_vi_layer_update_coord()
153 DRM_DEBUG_DRIVER("Layer source size W: %d H: %d\n", src_w, src_h); in sun8i_vi_layer_update_coord()
180 do_div(ability, mode->vdisplay * fps * max(src_w, dst_w)); in sun8i_vi_layer_update_coord()
194 if (src_w > scanline) { in sun8i_vi_layer_update_coord()
196 hm = src_w; in sun8i_vi_layer_update_coord()
198 src_w = hn; in sun8i_vi_layer_update_coord()
201 hscale = (src_w << 16) / dst_w; in sun8i_vi_layer_update_coord()
[all …]
Dsun8i_ui_layer.c101 u32 src_w, src_h, dst_w, dst_h; in sun8i_ui_layer_update_coord() local
112 src_w = drm_rect_width(&state->src) >> 16; in sun8i_ui_layer_update_coord()
120 insize = SUN8I_MIXER_SIZE(src_w, src_h); in sun8i_ui_layer_update_coord()
156 DRM_DEBUG_DRIVER("Layer source size W: %d H: %d\n", src_w, src_h); in sun8i_ui_layer_update_coord()
169 hscale = state->src_w / state->crtc_w; in sun8i_ui_layer_update_coord()
172 sun8i_ui_scaler_setup(mixer, channel, src_w, src_h, dst_w, in sun8i_ui_layer_update_coord()
/drivers/gpu/drm/arm/
Dmalidp_planes.c276 u32 src_w, src_h; in malidp_se_check_scaling() local
290 src_w = state->src_h >> 16; in malidp_se_check_scaling()
291 src_h = state->src_w >> 16; in malidp_se_check_scaling()
293 src_w = state->src_w >> 16; in malidp_se_check_scaling()
297 if ((state->crtc_w == src_w) && (state->crtc_h == src_h)) { in malidp_se_check_scaling()
754 u32 src_w, src_h, val = 0, src_x, src_y; in malidp_de_set_plane_afbc() local
769 src_w = plane->state->src_w >> 16; in malidp_de_set_plane_afbc()
774 val = ((fb->width - (src_x + src_w)) << MALIDP_AD_CROP_RIGHT_OFFSET) | in malidp_de_set_plane_afbc()
804 u32 src_w, src_h, dest_w, dest_h, val; in malidp_de_plane_update() local
815 src_w = fb->width; in malidp_de_plane_update()
[all …]
/drivers/gpu/drm/atmel-hlcdc/
Datmel_hlcdc_plane.c53 uint32_t src_w; member
293 if (state->crtc_w == state->src_w && state->crtc_h == state->src_h) { in atmel_hlcdc_plane_setup_scaler()
300 xfactor = atmel_hlcdc_plane_phiscaler_get_factor(state->src_w, in atmel_hlcdc_plane_setup_scaler()
309 state->crtc_w < state->src_w ? in atmel_hlcdc_plane_setup_scaler()
322 xfactor = (1024 * state->src_w) / state->crtc_w; in atmel_hlcdc_plane_setup_scaler()
346 ATMEL_HLCDC_LAYER_SIZE(state->src_w, in atmel_hlcdc_plane_update_pos_and_size()
500 pixels = (plane_state->src_w * plane_state->src_h) - in atmel_hlcdc_plane_prepare_ahb_routing()
623 hstate->src_w = drm_rect_width(&s->src); in atmel_hlcdc_plane_atomic_check()
630 if ((hstate->src_x | hstate->src_y | hstate->src_w | hstate->src_h) & in atmel_hlcdc_plane_atomic_check()
636 hstate->src_w >>= 16; in atmel_hlcdc_plane_atomic_check()
[all …]
/drivers/gpu/drm/i915/display/
Dintel_sprite.c57 u32 src_x, src_y, src_w, src_h, hsub, vsub; in intel_plane_check_src_coordinates() local
77 src_w = drm_rect_width(src) >> 16; in intel_plane_check_src_coordinates()
82 src_w << 16, src_h << 16); in intel_plane_check_src_coordinates()
95 if (src_x % hsub || src_w % hsub) { in intel_plane_check_src_coordinates()
97 src_x, src_w, hsub, yesno(rotated)); in intel_plane_check_src_coordinates()
615 unsigned int src_w, dst_w, pixel_rate; in ivb_sprite_min_cdclk() local
627 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; in ivb_sprite_min_cdclk()
630 if (src_w != dst_w) in ivb_sprite_min_cdclk()
636 dst_w = min(src_w, dst_w); in ivb_sprite_min_cdclk()
638 return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_rate, num * src_w), in ivb_sprite_min_cdclk()
[all …]
Dskl_scaler.c93 int src_w, int src_h, int dst_w, int dst_h, in skl_update_scaler() argument
109 if (src_w != dst_w || src_h != dst_h) in skl_update_scaler()
151 (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) { in skl_update_scaler()
158 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || in skl_update_scaler()
161 (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H || in skl_update_scaler()
164 (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || in skl_update_scaler()
169 crtc->pipe, scaler_user, src_w, src_h, in skl_update_scaler()
178 crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, in skl_update_scaler()
/drivers/gpu/drm/selftests/
Dtest-drm_plane_helper.c16 unsigned src_w, unsigned src_h) in set_src() argument
20 plane_state->src_w = src_w; in set_src()
26 unsigned src_w, unsigned src_h) in check_src_eq() argument
41 drm_rect_width(&plane_state->src) != src_w || in check_src_eq()
/drivers/gpu/drm/arm/display/komeda/
Dkomeda_framebuffer.c209 u32 src_x, u32 src_y, u32 src_w, u32 src_h) in komeda_fb_check_src_coords() argument
216 if ((src_x + src_w > fb->width) || (src_y + src_h > fb->height)) { in komeda_fb_check_src_coords()
221 if ((src_x % info->hsub) || (src_w % info->hsub) || in komeda_fb_check_src_coords()
224 src_x, src_y, src_w, src_h, info->format); in komeda_fb_check_src_coords()
228 if ((src_x % block_w) || (src_w % block_w) || in komeda_fb_check_src_coords()
231 src_x, src_y, src_w, src_h, info->format); in komeda_fb_check_src_coords()
/drivers/gpu/drm/
Ddrm_plane.c774 uint32_t src_w, uint32_t src_h) in __setplane_check() argument
803 ret = drm_framebuffer_check_src_coords(src_x, src_y, src_w, src_h, fb); in __setplane_check()
848 uint32_t src_w, uint32_t src_h, in __setplane_internal() argument
870 src_x, src_y, src_w, src_h); in __setplane_internal()
877 src_x, src_y, src_w, src_h, ctx); in __setplane_internal()
900 uint32_t src_w, uint32_t src_h, in __setplane_atomic() argument
920 src_x, src_y, src_w, src_h); in __setplane_atomic()
926 src_x, src_y, src_w, src_h, ctx); in __setplane_atomic()
936 uint32_t src_w, uint32_t src_h) in setplane_internal() argument
947 src_x, src_y, src_w, src_h, &ctx); in setplane_internal()
[all …]
Ddrm_plane_helper.c119 .src_w = drm_rect_width(src), in drm_plane_helper_check_update()
153 uint32_t src_w, uint32_t src_h, in drm_primary_helper_update() argument
166 .x2 = src_x + src_w, in drm_primary_helper_update()
/drivers/gpu/drm/vc4/
Dvc4_plane.c365 vc4_state->src_w[0] = DIV_ROUND_CLOSEST(state->src.x2, 1 << 16) - vc4_state->src_x; in vc4_plane_setup_clipping_and_scaling()
377 vc4_state->x_scaling[0] = vc4_get_scaling_mode(vc4_state->src_w[0], in vc4_plane_setup_clipping_and_scaling()
388 vc4_state->src_w[1] = vc4_state->src_w[0] / h_subsample; in vc4_plane_setup_clipping_and_scaling()
392 vc4_get_scaling_mode(vc4_state->src_w[1], in vc4_plane_setup_clipping_and_scaling()
465 pix_per_line = vc4_state->src_w[0]; in vc4_lbm_size()
499 vc4_state->src_w[channel], vc4_state->crtc_w); in vc4_write_scaling_parameters()
512 vc4_state->src_w[channel], vc4_state->crtc_w); in vc4_write_scaling_parameters()
572 vc4_state->membus_load += vc4_state->src_w[i] * in vc4_plane_calc_load()
868 VC4_SET_FIELD(vc4_state->src_w[0], in vc4_plane_mode_set()
934 VC4_SET_FIELD(vc4_state->src_w[0], in vc4_plane_mode_set()
[all …]
/drivers/gpu/drm/meson/
Dmeson_plane.c147 int src_w, src_h, dst_w, dst_h; in meson_plane_atomic_update() local
263 src_w = fixed16_to_int(new_state->src_w); in meson_plane_atomic_update()
281 hf_phase_step = ((src_w << 18) / dst_w) << 6; in meson_plane_atomic_update()
292 if (src_h != dst_h || src_w != dst_w) { in meson_plane_atomic_update()
293 priv->viu.osd_sc_i_wh_m1 = SCI_WH_M1_W(src_w - 1) | in meson_plane_atomic_update()
331 if (src_w != dst_w) { in meson_plane_atomic_update()
/drivers/gpu/drm/ingenic/
Dingenic-ipu.c279 state->src_w != oldstate->src_w || in osd_changed()
350 stride = ((newstate->src_w >> 16) * finfo->cpp[2] / finfo->hsub) in ingenic_ipu_plane_atomic_update()
354 stride |= ((newstate->src_w >> 16) * finfo->cpp[1] / finfo->hsub) in ingenic_ipu_plane_atomic_update()
359 stride = ((newstate->src_w >> 16) * finfo->cpp[0]) << JZ_IPU_Y_STRIDE_Y_LSB; in ingenic_ipu_plane_atomic_update()
520 newstate->src_w >> 16, newstate->src_h >> 16, in ingenic_ipu_plane_atomic_update()
559 if ((new_plane_state->src_w >> 16) < 4 || (new_plane_state->src_h >> 16) < 4) in ingenic_ipu_plane_atomic_check()
563 if (((new_plane_state->src_w >> 16) & 1) || (new_plane_state->crtc_w & 1)) in ingenic_ipu_plane_atomic_check()
571 xres = new_plane_state->src_w >> 16; in ingenic_ipu_plane_atomic_check()

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