| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_resource.c | 1351 struct dc_stream_status *stream_status = NULL; in dc_add_plane_to_context() local
1355 stream_status = &context->stream_status[i]; in dc_add_plane_to_context()
1358 if (stream_status == NULL) { in dc_add_plane_to_context()
1364 if (stream_status->plane_count == MAX_SURFACE_NUM) { in dc_add_plane_to_context()
1420 stream_status->plane_states[stream_status->plane_count] = plane_state; in dc_add_plane_to_context()
1422 stream_status->plane_count++; in dc_add_plane_to_context()
1434 struct dc_stream_status *stream_status = NULL; in dc_remove_plane_from_context() local
1442 stream_status = &context->stream_status[i]; in dc_remove_plane_from_context()
1446 if (stream_status == NULL) { in dc_remove_plane_from_context()
1478 for (i = 0; i < stream_status->plane_count; i++) { in dc_remove_plane_from_context()
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| D | dc.c | 1609 context->stream_status[i].plane_count, in dc_commit_state_no_check()
1646 context->stream_status[i].plane_count, in dc_commit_state_no_check()
1875 for (j = 0; j < new_ctx->stream_status[i].plane_count; j++) in dc_copy_state()
1877 new_ctx->stream_status[i].plane_states[j]); in dc_copy_state()
2196 const struct dc_stream_status *stream_status) in check_update_surfaces_for_stream() argument
2206 if (stream_status == NULL || stream_status->plane_count != surface_count) in check_update_surfaces_for_stream()
2267 const struct dc_stream_status *stream_status) in dc_check_update_surfaces_for_stream() argument
2277 type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status); in dc_check_update_surfaces_for_stream()
2312 return &ctx->stream_status[i]; in stream_get_status()
2569 const struct dc_stream_status *stream_status; in update_planes_and_stream_state() local
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| D | dc_stream.c | 229 return &state->stream_status[i]; in dc_stream_get_status_from_state()
471 struct dc_stream_status *stream_status = dc_stream_get_status(stream); in dc_stream_add_writeback() local
473 dwb->otg_inst = stream_status->primary_otg_inst; in dc_stream_add_writeback()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/ |
| D | clk_mgr.c | 78 const struct dc_stream_status stream_status = context->stream_status[i]; in clk_mgr_helper_get_active_plane_cnt() local
83 total_plane_count += stream_status.plane_count; in clk_mgr_helper_get_active_plane_cnt()
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_hwseq.c | 375 struct dc_stream_status *stream_status = NULL; in dcn30_program_all_writeback_pipes_in_tree() local
382 stream_status = &context->stream_status[i_stream]; in dcn30_program_all_writeback_pipes_in_tree()
386 ASSERT(stream_status); in dcn30_program_all_writeback_pipes_in_tree()
752 if (dc->current_state->stream_status[i].plane_count) in dcn30_apply_idle_power_optimizations()
771 plane = (stream ? dc->current_state->stream_status[0].plane_states[0] : NULL); in dcn30_apply_idle_power_optimizations()
790 dc->current_state->stream_status[0].plane_count == 1 && in dcn30_apply_idle_power_optimizations()
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_resource.c | 1219 if (context->stream_status[i].plane_count == 0) in dcn10_validate_global()
1222 if (context->stream_status[i].plane_count > 2) in dcn10_validate_global()
1225 if (context->stream_status[i].plane_count > 1) in dcn10_validate_global()
1228 for (j = 0; j < context->stream_status[i].plane_count; j++) { in dcn10_validate_global()
1230 context->stream_status[i].plane_states[j]; in dcn10_validate_global()
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| D | dcn10_hw_sequencer.c | 2889 if (context->stream_status[i].plane_count == 0) in dcn10_post_unlock_program_front_end()
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| /drivers/gpu/drm/amd/display/dc/dce100/ |
| D | dce100_resource.c | 867 if (context->stream_status[i].plane_count == 0) in dce100_validate_surface_sets()
870 if (context->stream_status[i].plane_count > 1) in dce100_validate_surface_sets()
873 if (context->stream_status[i].plane_states[0]->format in dce100_validate_surface_sets()
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| /drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_resource.c | 1053 if (context->stream_status[i].plane_count == 0) in dce110_validate_surface_sets()
1056 if (context->stream_status[i].plane_count > 2) in dce110_validate_surface_sets()
1059 for (j = 0; j < context->stream_status[i].plane_count; j++) { in dce110_validate_surface_sets()
1061 context->stream_status[i].plane_states[j]; in dce110_validate_surface_sets()
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| /drivers/gpu/drm/amd/display/dc/dce112/ |
| D | dce112_resource.c | 996 if (context->stream_status[i].plane_count == 0) in dce112_validate_surface_sets()
999 if (context->stream_status[i].plane_count > 1) in dce112_validate_surface_sets()
1002 if (context->stream_status[i].plane_states[0]->format in dce112_validate_surface_sets()
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| /drivers/gpu/drm/amd/display/dc/dce80/ |
| D | dce80_resource.c | 901 if (context->stream_status[i].plane_count == 0) in dce80_validate_surface_sets()
904 if (context->stream_status[i].plane_count > 1) in dce80_validate_surface_sets()
907 if (context->stream_status[i].plane_states[0]->format in dce80_validate_surface_sets()
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| /drivers/gpu/drm/amd/display/dc/dce60/ |
| D | dce60_resource.c | 896 if (context->stream_status[i].plane_count == 0) in dce60_validate_surface_sets()
899 if (context->stream_status[i].plane_count > 1) in dce60_validate_surface_sets()
902 if (context->stream_status[i].plane_states[0]->format in dce60_validate_surface_sets()
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | core_types.h | 446 struct dc_stream_status stream_status[MAX_PIPES]; member
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| /drivers/gpu/drm/amd/display/dc/ |
| D | dc_stream.h | 441 const struct dc_stream_status *stream_status);
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| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm.c | 2333 adev, state->stream_status[i].primary_otg_inst); in dm_gpureset_toggle_interrupts()
2335 if (acrtc && state->stream_status[i].plane_count != 0) { in dm_gpureset_toggle_interrupts()
2582 for (m = 0; m < dc_state->stream_status->plane_count; m++) { in dm_gpureset_commit_state()
2584 dc_state->stream_status->plane_states[m]; in dm_gpureset_commit_state()
2591 dc_state->stream_status->plane_count, in dm_gpureset_commit_state()
2666 for (j = 0; j < dc_state->stream_status[i].plane_count; j++) { in dm_resume()
2667 dc_state->stream_status[i].plane_states[j]->update_flags.raw in dm_resume()
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_hwseq.c | 1822 if (dc->current_state->stream_status[0].plane_count == 1 && in dcn20_post_unlock_program_front_end()
1823 context->stream_status[0].plane_count > 1) { in dcn20_post_unlock_program_front_end()
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