| /drivers/gpu/drm/radeon/ |
| D | evergreen_cs.c | 190 struct eg_surface *surf, in evergreen_surface_check_linear() argument
193 surf->layer_size = surf->nbx * surf->nby * surf->bpe * surf->nsamples; in evergreen_surface_check_linear()
194 surf->base_align = surf->bpe; in evergreen_surface_check_linear()
195 surf->palign = 1; in evergreen_surface_check_linear()
196 surf->halign = 1; in evergreen_surface_check_linear()
201 struct eg_surface *surf, in evergreen_surface_check_linear_aligned() argument
207 palign = MAX(64, track->group_size / surf->bpe); in evergreen_surface_check_linear_aligned()
208 surf->layer_size = surf->nbx * surf->nby * surf->bpe * surf->nsamples; in evergreen_surface_check_linear_aligned()
209 surf->base_align = track->group_size; in evergreen_surface_check_linear_aligned()
210 surf->palign = palign; in evergreen_surface_check_linear_aligned()
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| /drivers/gpu/drm/qxl/ |
| D | qxl_cmd.c | 333 int qxl_io_update_area(struct qxl_device *qdev, struct qxl_bo *surf, in qxl_io_update_area() argument
340 if (!surf->hw_surf_alloc) in qxl_io_update_area()
343 if (surf->is_primary) in qxl_io_update_area()
346 surface_id = surf->surface_id; in qxl_io_update_area()
347 surface_width = surf->surf.width; in qxl_io_update_area()
348 surface_height = surf->surf.height; in qxl_io_update_area()
394 create->format = bo->surf.format; in qxl_io_create_primary()
395 create->width = bo->surf.width; in qxl_io_create_primary()
396 create->height = bo->surf.height; in qxl_io_create_primary()
397 create->stride = bo->surf.stride; in qxl_io_create_primary()
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| D | qxl_dumb.c | 40 struct qxl_surface surf; in qxl_mode_dumb_create() local
58 surf.width = args->width; in qxl_mode_dumb_create()
59 surf.height = args->height; in qxl_mode_dumb_create()
60 surf.stride = pitch; in qxl_mode_dumb_create()
61 surf.format = format; in qxl_mode_dumb_create()
62 surf.data = 0; in qxl_mode_dumb_create()
66 args->size, &surf, &gobj, in qxl_mode_dumb_create()
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| D | qxl_display.c | 218 return qxl_check_mode(qdev, bo->surf.width, bo->surf.height); in qxl_check_framebuffer()
746 width = bo->surf.width; in qxl_update_dumb_head()
747 height = bo->surf.height; in qxl_update_dumb_head()
766 struct qxl_surface *surf) in qxl_calc_dumb_shadow() argument
771 memset(surf, 0, sizeof(*surf)); in qxl_calc_dumb_shadow()
774 head->x = surf->width; in qxl_calc_dumb_shadow()
775 surf->width += head->width; in qxl_calc_dumb_shadow()
776 if (surf->height < head->height) in qxl_calc_dumb_shadow()
777 surf->height = head->height; in qxl_calc_dumb_shadow()
779 if (surf->width < 64) in qxl_calc_dumb_shadow()
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| D | qxl_gem.c | 48 struct qxl_surface *surf, in qxl_gem_object_create() argument
58 r = qxl_bo_create(qdev, size, kernel, false, initial_domain, 0, surf, &qbo); in qxl_gem_object_create()
85 struct qxl_surface *surf, in qxl_gem_object_create_with_handle() argument
96 false, false, surf, in qxl_gem_object_create_with_handle()
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| D | qxl_drv.h | 94 struct qxl_surface surf; member
314 struct qxl_surface *surf,
320 struct qxl_surface *surf,
365 int qxl_io_update_area(struct qxl_device *qdev, struct qxl_bo *surf,
446 struct qxl_bo *surf);
450 struct qxl_bo *surf);
452 struct qxl_bo *surf);
458 void qxl_surface_evict(struct qxl_device *qdev, struct qxl_bo *surf, bool freeing);
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| D | qxl_ioctl.c | 398 struct qxl_surface surf; in qxl_alloc_surf_ioctl() local
404 surf.format = param->format; in qxl_alloc_surf_ioctl()
405 surf.width = param->width; in qxl_alloc_surf_ioctl()
406 surf.height = param->height; in qxl_alloc_surf_ioctl()
407 surf.stride = param->stride; in qxl_alloc_surf_ioctl()
408 surf.data = 0; in qxl_alloc_surf_ioctl()
413 &surf, in qxl_alloc_surf_ioctl()
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| D | qxl_object.c | 111 struct qxl_surface *surf, in qxl_bo_create() argument
138 if (surf) in qxl_bo_create()
139 bo->surf = *surf; in qxl_bo_create()
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| D | qxl_object.h | 60 struct qxl_surface *surf,
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| /drivers/gpu/drm/vc4/ |
| D | vc4_render_cl.c | 101 struct drm_vc4_submit_rcl_surface *surf, in vc4_full_res_offset() argument
104 return bo->paddr + surf->offset + VC4_TILE_BUFFER_SIZE * in vc4_full_res_offset()
385 struct drm_vc4_submit_rcl_surface *surf) in vc4_full_res_bounds_check() argument
390 if (surf->offset > obj->base.size) { in vc4_full_res_bounds_check()
392 surf->offset, obj->base.size); in vc4_full_res_bounds_check()
396 if ((obj->base.size - surf->offset) / VC4_TILE_BUFFER_SIZE < in vc4_full_res_bounds_check()
402 surf->offset); in vc4_full_res_bounds_check()
411 struct drm_vc4_submit_rcl_surface *surf) in vc4_rcl_msaa_surface_setup() argument
413 if (surf->flags != 0 || surf->bits != 0) { in vc4_rcl_msaa_surface_setup()
418 if (surf->hindex == ~0) in vc4_rcl_msaa_surface_setup()
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| /drivers/gpu/drm/vmwgfx/ |
| D | vmwgfx_stdu.c | 1016 if (vps->surf) in vmw_stdu_primary_plane_cleanup_fb()
1054 if (vps->surf) { in vmw_stdu_primary_plane_prepare_fb()
1056 vmw_surface_unreference(&vps->surf); in vmw_stdu_primary_plane_prepare_fb()
1112 if (vps->surf) { in vmw_stdu_primary_plane_prepare_fb()
1114 vps->surf->metadata.base_size; in vmw_stdu_primary_plane_prepare_fb()
1118 vps->surf->metadata.format != metadata.format) { in vmw_stdu_primary_plane_prepare_fb()
1120 vmw_surface_unreference(&vps->surf); in vmw_stdu_primary_plane_prepare_fb()
1125 if (!vps->surf) { in vmw_stdu_primary_plane_prepare_fb()
1127 &vps->surf); in vmw_stdu_primary_plane_prepare_fb()
1140 if (vps->surf) { in vmw_stdu_primary_plane_prepare_fb()
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| D | vmwgfx_kms.c | 309 if (vps->surf) { in vmw_du_plane_unpin_surf()
311 vmw_resource_unpin(&vps->surf->res); in vmw_du_plane_unpin_surf()
318 vmw_surface_unreference(&vps->surf); in vmw_du_plane_unpin_surf()
360 if (vps->surf) in vmw_du_cursor_plane_prepare_fb()
361 vmw_surface_unreference(&vps->surf); in vmw_du_cursor_plane_prepare_fb()
371 vps->surf = vmw_framebuffer_to_vfbs(fb)->surface; in vmw_du_cursor_plane_prepare_fb()
372 vmw_surface_reference(vps->surf); in vmw_du_cursor_plane_prepare_fb()
404 du->cursor_surface = vps->surf; in vmw_du_cursor_plane_atomic_update()
407 if (vps->surf) { in vmw_du_cursor_plane_atomic_update()
411 vps->surf->snooper.image, in vmw_du_cursor_plane_atomic_update()
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| D | vmwgfx_kms.h | 286 struct vmw_surface *surf; member
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| /drivers/gpu/drm/gma500/ |
| D | oaktrail_device.c | 210 p->surf = PSB_RVDC32(DSPASURF); in oaktrail_save_display_registers()
343 PSB_WVDC32(p->surf, DSPASURF); in oaktrail_restore_display_registers()
467 .surf = DSPASURF,
491 .surf = DSPBSURF,
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| D | psb_device.c | 268 .surf = DSPASURF,
292 .surf = DSPBSURF,
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| D | psb_drv.h | 252 u32 surf; member
287 u32 surf; member
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| D | cdv_device.c | 541 .surf = DSPASURF,
566 .surf = DSPBSURF,
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| D | oaktrail_crtc.c | 642 REG_WRITE(map->surf, start); in oaktrail_pipe_set_base()
643 REG_READ(map->surf); in oaktrail_pipe_set_base()
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| D | oaktrail_hdmi.c | 774 pipeb->surf = PSB_RVDC32(DSPBSURF); in oaktrail_hdmi_save()
830 PSB_WVDC32(pipeb->surf, DSPBSURF); in oaktrail_hdmi_restore()
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| D | gma_display.c | 121 REG_WRITE(map->surf, start); in gma_pipe_set_base()
122 REG_READ(map->surf); in gma_pipe_set_base()
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