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Searched refs:tg_mask (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn31/
Ddcn31_optc.c41 optc1->tg_shift->field_name, optc1->tg_mask->field_name
278 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn31_timing_generator_init()
279 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn31_timing_generator_init()
Ddcn31_resource.c1144 tgn10->tg_mask = &optc_mask; in dcn31_timing_generator_create()
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_optc.c39 optc1->tg_shift->field_name, optc1->tg_mask->field_name
347 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn30_timing_generator_init()
348 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn30_timing_generator_init()
Ddcn30_resource.c1039 tgn10->tg_mask = &optc_mask; in dcn30_timing_generator_create()
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_optc.c38 optc1->tg_shift->field_name, optc1->tg_mask->field_name
594 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn20_timing_generator_init()
595 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn20_timing_generator_init()
Ddcn20_resource.c871 static const struct dcn_optc_mask tg_mask = { variable
1268 tgn10->tg_mask = &tg_mask; in dcn20_timing_generator_create()
/drivers/net/ethernet/mscc/
Docelot_vcap.c46 u32 tg_mask; /* Current type-group mask */ member
199 data->tg_mask = 0; in vcap_data_offset_get()
203 data->tg_mask |= GENMASK(offset + width - 1, offset); in vcap_data_offset_get()
364 data.tg = (data.tg & ~data.tg_mask); in is2_entry_set()
689 data.tg = (data.tg & ~data.tg_mask); in is1_entry_set()
829 data.tg = (data.tg & ~data.tg_mask); in es0_entry_set()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_optc.c39 optc1->tg_shift->field_name, optc1->tg_mask->field_name
318 if (optc1->tg_mask->OTG_H_TIMING_DIV_MODE != 0) { in optc1_program_timing()
1590 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn10_timing_generator_init()
1591 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn10_timing_generator_init()
Ddcn10_resource.c466 static const struct dcn_optc_mask tg_mask = { variable
790 tgn10->tg_mask = &tg_mask; in dcn10_timing_generator_create()
Ddcn10_optc.h538 const struct dcn_optc_mask *tg_mask; member
/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_resource.c497 static const struct dcn_optc_mask tg_mask = { variable
1515 tgn10->tg_mask = &tg_mask; in dcn21_timing_generator_create()
/drivers/gpu/drm/amd/display/dc/dcn302/
Ddcn302_resource.c750 tgn10->tg_mask = &optc_mask; in dcn302_timing_generator_create()
/drivers/gpu/drm/amd/display/dc/dcn303/
Ddcn303_resource.c703 tgn10->tg_mask = &optc_mask; in dcn303_timing_generator_create()
/drivers/gpu/drm/amd/display/dc/dcn301/
Ddcn301_resource.c1055 tgn10->tg_mask = &optc_mask; in dcn301_timing_generator_create()