Home
last modified time | relevance | path

Searched refs:tiling_info (Results 1 – 25 of 25) sorted by relevance

/drivers/gpu/drm/amd/display/dc/core/
Ddc_debug.c141 plane_state->tiling_info.gfx8.num_banks, in pre_surface_trace()
142 plane_state->tiling_info.gfx8.bank_width, in pre_surface_trace()
143 plane_state->tiling_info.gfx8.bank_width_c, in pre_surface_trace()
144 plane_state->tiling_info.gfx8.bank_height, in pre_surface_trace()
145 plane_state->tiling_info.gfx8.bank_height_c, in pre_surface_trace()
146 plane_state->tiling_info.gfx8.tile_aspect, in pre_surface_trace()
147 plane_state->tiling_info.gfx8.tile_aspect_c, in pre_surface_trace()
148 plane_state->tiling_info.gfx8.tile_split, in pre_surface_trace()
149 plane_state->tiling_info.gfx8.tile_split_c, in pre_surface_trace()
150 plane_state->tiling_info.gfx8.tile_mode, in pre_surface_trace()
[all …]
Ddc_hw_sequencer.c418 switch (bottom_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) { in get_surface_tile_visual_confirm_color()
Ddc.c2039 if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info, in get_plane_info_update_type()
2047 if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) { in get_plane_info_update_type()
2365 surface->tiling_info = in copy_surface_update_to_plane()
2366 srf_update->plane_info->tiling_info; in copy_surface_update_to_plane()
Ddc_resource.c2180 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) { in dc_validate_global_state()
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_mem_input.c101 union dc_tiling_info *tiling_info) in get_mi_tiling() argument
103 switch (tiling_info->gfx8.array_mode) { in get_mi_tiling()
136 union dc_tiling_info *tiling_info, in dce_mi_program_pte_vm() argument
141 enum mi_tiling_format mi_tiling = get_mi_tiling(tiling_info); in dce_mi_program_pte_vm()
633 union dc_tiling_info *tiling_info, in dce_mi_program_surface_config() argument
642 program_tiling(dce_mi, tiling_info); in dce_mi_program_surface_config()
654 union dc_tiling_info *tiling_info, in dce60_mi_program_surface_config() argument
663 program_tiling(dce_mi, tiling_info); in dce60_mi_program_surface_config()
/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_mem_input_v.c528 union dc_tiling_info *tiling_info, in get_dvmm_hw_setting() argument
546 switch (tiling_info->gfx8.array_mode) { in get_dvmm_hw_setting()
568 union dc_tiling_info *tiling_info, in dce_mem_input_v_program_pte_vm() argument
572 const unsigned int *pte = get_dvmm_hw_setting(tiling_info, format, false); in dce_mem_input_v_program_pte_vm()
573 const unsigned int *pte_chroma = get_dvmm_hw_setting(tiling_info, format, true); in dce_mem_input_v_program_pte_vm()
641 union dc_tiling_info *tiling_info, in dce_mem_input_v_program_surface_config() argument
650 program_tiling(mem_input110, tiling_info, format); in dce_mem_input_v_program_surface_config()
Ddce110_hw_sequencer.c1978 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) in should_enable_fbc()
2673 &plane_state->tiling_info, in dce110_program_front_end_for_pipe()
2685 &plane_state->tiling_info, in dce110_program_front_end_for_pipe()
/drivers/gpu/drm/amd/display/dc/inc/hw/
Dmem_input.h142 union dc_tiling_info *tiling_info,
156 union dc_tiling_info *tiling_info,
Dhubp.h118 union dc_tiling_info *tiling_info,
132 union dc_tiling_info *tiling_info,
/drivers/gpu/drm/amd/display/dc/dce60/
Ddce60_hw_sequencer.c105 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) in dce60_should_enable_fbc()
319 &plane_state->tiling_info, in dce60_program_front_end_for_pipe()
331 &plane_state->tiling_info, in dce60_program_front_end_for_pipe()
/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm.c4756 fill_gfx8_tiling_info_from_flags(union dc_tiling_info *tiling_info, in fill_gfx8_tiling_info_from_flags() argument
4770 tiling_info->gfx8.num_banks = num_banks; in fill_gfx8_tiling_info_from_flags()
4771 tiling_info->gfx8.array_mode = in fill_gfx8_tiling_info_from_flags()
4773 tiling_info->gfx8.tile_split = tile_split; in fill_gfx8_tiling_info_from_flags()
4774 tiling_info->gfx8.bank_width = bankw; in fill_gfx8_tiling_info_from_flags()
4775 tiling_info->gfx8.bank_height = bankh; in fill_gfx8_tiling_info_from_flags()
4776 tiling_info->gfx8.tile_aspect = mtaspect; in fill_gfx8_tiling_info_from_flags()
4777 tiling_info->gfx8.tile_mode = in fill_gfx8_tiling_info_from_flags()
4781 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; in fill_gfx8_tiling_info_from_flags()
4784 tiling_info->gfx8.pipe_config = in fill_gfx8_tiling_info_from_flags()
[all …]
Damdgpu_dm_trace.h448 __entry->swizzle = plane_state->tiling_info.gfx9.swizzle;
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_hubp.c408 union dc_tiling_info *tiling_info, in hubp3_program_surface_config() argument
418 hubp3_program_tiling(hubp2, tiling_info, format); in hubp3_program_surface_config()
Ddcn30_hubp.h267 union dc_tiling_info *tiling_info,
/drivers/gpu/drm/amd/display/dc/
Ddc.h903 union dc_tiling_info tiling_info; member
958 union dc_tiling_info tiling_info; member
/drivers/gpu/drm/amd/amdgpu/
Damdgpu_gem.c568 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); in amdgpu_gem_metadata_ioctl()
578 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); in amdgpu_gem_metadata_ioctl()
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hubp.h323 union dc_tiling_info *tiling_info,
Ddcn20_hubp.c538 union dc_tiling_info *tiling_info, in hubp2_program_surface_config() argument
548 hubp2_program_tiling(hubp2, tiling_info, format); in hubp2_program_surface_config()
Ddcn20_resource.c2323 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle); in dcn20_populate_dml_pipes_from_context()
2324 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle, in dcn20_populate_dml_pipes_from_context()
3350 plane_state->tiling_info.gfx9.swizzle = swizzle; in dcn20_patch_unknown_plane_state()
Ddcn20_hwseq.c1547 &plane_state->tiling_info, in dcn20_update_dchubp_dpp()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hubp.c538 union dc_tiling_info *tiling_info, in hubp1_program_surface_config() argument
546 hubp1_program_tiling(hubp, tiling_info, format); in hubp1_program_surface_config()
Ddcn10_hubp.h702 union dc_tiling_info *tiling_info,
Ddcn10_resource.c1279 plane_state->tiling_info.gfx9.swizzle = swizzle; in dcn10_patch_unknown_plane_state()
Ddcn10_hw_sequencer.c2715 &plane_state->tiling_info, in dcn10_update_dchubp_dpp()
/drivers/gpu/drm/amd/display/dc/calcs/
Ddcn_calcs.c339 input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle; in pipe_ctx_to_e2e_pipe_params()
348 …input->src.macro_tile_size = swizzle_mode_to_macro_tile_size(pipe->plane_state->tiling_info.gfx9.s… in pipe_ctx_to_e2e_pipe_params()
1026 pipe->plane_state->tiling_info.gfx9.swizzle); in dcn_validate_bandwidth()