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Searched refs:timing_generator_count (Results 1 – 22 of 22) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hw_sequencer_debug.c426 for (i = 0; i < pool->timing_generator_count; i++) { in dcn10_get_otg_states()
493 for (i = 0; i < pool->timing_generator_count; i++) { in dcn10_clear_otpc_underflow()
Ddcn10_resource.c1639 pool->base.timing_generator_count = j; in dcn10_resource_construct()
Ddcn10_hw_sequencer.c349 for (i = 0; i < pool->timing_generator_count; i++) { in dcn10_log_hw_state()
/drivers/gpu/drm/amd/display/dc/dce80/
Ddce80_resource.c965 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce80_construct()
1166 pool->base.timing_generator_count = res_cap_81.num_timing_generator; in dce81_construct()
1366 pool->base.timing_generator_count = res_cap_83.num_timing_generator; in dce83_construct()
/drivers/gpu/drm/amd/display/dc/dce60/
Ddce60_resource.c960 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce60_construct()
1155 pool->base.timing_generator_count = res_cap_61.num_timing_generator; in dce61_construct()
1353 pool->base.timing_generator_count = res_cap_64.num_timing_generator; in dce64_construct()
/drivers/gpu/drm/amd/display/dc/inc/
Dcore_types.h258 unsigned int timing_generator_count; member
/drivers/gpu/drm/amd/display/dc/dce120/
Ddce120_resource.c1072 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce120_resource_construct()
1237 pool->base.timing_generator_count = j; in dce120_resource_construct()
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hwseq.c2501 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { in dcn20_fpga_init_hw()
2508 for (i = 0; i < res_pool->timing_generator_count; i++) { in dcn20_fpga_init_hw()
2563 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { in dcn20_fpga_init_hw()
2579 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { in dcn20_fpga_init_hw()
Ddcn20_resource.c3982 pool->base.timing_generator_count = i; in dcn20_resource_construct()
/drivers/gpu/drm/amd/display/dc/dce100/
Ddce100_resource.c1066 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce100_resource_construct()
/drivers/gpu/drm/amd/display/dc/dce112/
Ddce112_resource.c1235 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce112_resource_construct()
/drivers/gpu/drm/amd/display/dc/core/
Ddc_resource.c1766 if (new_ctx->stream_count >= dc->res_pool->timing_generator_count) { in dc_add_stream_to_ctx()
1954 if (tg_inst >= pool->timing_generator_count) in acquire_resource_from_hw_enabled_state()
Ddc_link.c2842 link->dc->res_pool->timing_generator_count; in dc_link_setup_psr()
Ddc.c1405 if (tg_inst >= dc->res_pool->timing_generator_count) in dc_validate_seamless_boot_timing()
/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_resource.c1367 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct()
Ddce110_hw_sequencer.c1576 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { in power_down_controllers()
1616 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { in disable_vga_and_power_gate_all_controllers()
/drivers/gpu/drm/amd/display/dc/dcn302/
Ddcn302_resource.c1673 pool->timing_generator_count = i; in dcn302_resource_construct()
/drivers/gpu/drm/amd/display/dc/dcn303/
Ddcn303_resource.c1604 pool->timing_generator_count = i; in dcn303_resource_construct()
/drivers/gpu/drm/amd/display/dc/dcn301/
Ddcn301_resource.c1949 pool->base.timing_generator_count = j; in dcn301_resource_construct()
/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_resource.c2213 pool->base.timing_generator_count = j; in dcn21_resource_construct()
/drivers/gpu/drm/amd/display/dc/dcn31/
Ddcn31_resource.c2195 pool->base.timing_generator_count = i; in dcn31_resource_construct()
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_resource.c2790 pool->base.timing_generator_count = i; in dcn30_resource_construct()