Searched refs:ui32 (Results 1 – 3 of 3) sorted by relevance
568 uint32_t ui32 = 0; in amdgpu_info_ioctl() local571 int ui32_size = sizeof(ui32); in amdgpu_info_ioctl()578 ui32 = adev->accel_working; in amdgpu_info_ioctl()579 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; in amdgpu_info_ioctl()586 ui32 = amdgpu_crtc->crtc_id; in amdgpu_info_ioctl()595 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; in amdgpu_info_ioctl()980 (void *)&ui32, &ui32_size)) { in amdgpu_info_ioctl()983 ui32 /= 100; in amdgpu_info_ioctl()989 (void *)&ui32, &ui32_size)) { in amdgpu_info_ioctl()992 ui32 /= 100; in amdgpu_info_ioctl()[all …]
507 reg_sq_cmd.bits.simd_id = pMsg->ui32.SIMD; in dbgdev_wave_control_set_registers()508 reg_sq_cmd.bits.wave_id = pMsg->ui32.WaveId; in dbgdev_wave_control_set_registers()511 reg_gfx_index.bits.sh_index = pMsg->ui32.ShaderArray; in dbgdev_wave_control_set_registers()512 reg_gfx_index.bits.se_index = pMsg->ui32.ShaderEngine; in dbgdev_wave_control_set_registers()513 reg_gfx_index.bits.instance_index = pMsg->ui32.HSACU; in dbgdev_wave_control_set_registers()534 reg_gfx_index.bits.sh_index = pMsg->ui32.ShaderArray; in dbgdev_wave_control_set_registers()535 reg_gfx_index.bits.se_index = pMsg->ui32.ShaderEngine; in dbgdev_wave_control_set_registers()536 reg_gfx_index.bits.instance_index = pMsg->ui32.HSACU; in dbgdev_wave_control_set_registers()
78 struct ui32 { struct89 } ui32; member