Home
last modified time | relevance | path

Searched refs:v5 (Results 1 – 23 of 23) sorted by relevance

/drivers/input/rmi4/
Drmi_f34.c58 init_completion(&f34->v5.cmd_done); in rmi_f34_command()
60 ret = rmi_read(rmi_dev, f34->v5.ctrl_address, &f34->v5.status); in rmi_f34_command()
68 f34->v5.status |= command & 0x0f; in rmi_f34_command()
70 ret = rmi_write(rmi_dev, f34->v5.ctrl_address, f34->v5.status); in rmi_f34_command()
78 if (!wait_for_completion_timeout(&f34->v5.cmd_done, in rmi_f34_command()
81 ret = rmi_read(rmi_dev, f34->v5.ctrl_address, &f34->v5.status); in rmi_f34_command()
89 if (f34->v5.status & 0x7f) { in rmi_f34_command()
92 __func__, command, f34->v5.status); in rmi_f34_command()
108 ret = rmi_read(f34->fn->rmi_dev, f34->v5.ctrl_address, in rmi_f34_attention()
114 complete(&f34->v5.cmd_done); in rmi_f34_attention()
[all …]
Drmi_f34.h303 struct f34v5_data v5; member
/drivers/char/mwave/
Dmwavedd.h99 #define PRINTK_6(f,s,v1,v2,v3,v4,v5) \ argument
101 printk(s,v1,v2,v3,v4,v5); \
104 #define PRINTK_7(f,s,v1,v2,v3,v4,v5,v6) \ argument
106 printk(s,v1,v2,v3,v4,v5,v6); \
109 #define PRINTK_8(f,s,v1,v2,v3,v4,v5,v6,v7) \ argument
111 printk(s,v1,v2,v3,v4,v5,v6,v7); \
120 #define PRINTK_6(f,s,v1,v2,v3,v4,v5) argument
121 #define PRINTK_7(f,s,v1,v2,v3,v4,v5,v6) argument
122 #define PRINTK_8(f,s,v1,v2,v3,v4,v5,v6,v7) argument
/drivers/gpu/drm/amd/display/dc/inc/
Dreg_helper.h86 f5, v5) \ argument
92 FN(reg, f5), v5)
95 f5, v5, f6, v6) \ argument
101 FN(reg, f5), v5,\
105 f5, v5, f6, v6, f7, v7) \ argument
111 FN(reg, f5), v5,\
116 f5, v5, f6, v6, f7, v7, f8, v8) \ argument
122 FN(reg, f5), v5,\
128 v5, f6, v6, f7, v7, f8, v8, f9, v9) \ argument
134 FN(reg, f5), v5, \
[all …]
Ddcn_calc_math.h38 float dcn_bw_max5(float v1, float v2, float v3, float v4, float v5);
/drivers/gpu/drm/amd/amdgpu/
Datombios_encoders.c559 DIG_ENCODER_CONTROL_PARAMETERS_V5 v5; member
690 args.v5.asDPPanelModeParam.ucAction = action; in amdgpu_atombios_encoder_setup_dig_encoder()
691 args.v5.asDPPanelModeParam.ucPanelMode = panel_mode; in amdgpu_atombios_encoder_setup_dig_encoder()
692 args.v5.asDPPanelModeParam.ucDigId = dig->dig_encoder; in amdgpu_atombios_encoder_setup_dig_encoder()
695 args.v5.asStreamParam.ucAction = action; in amdgpu_atombios_encoder_setup_dig_encoder()
696 args.v5.asStreamParam.ucDigId = dig->dig_encoder; in amdgpu_atombios_encoder_setup_dig_encoder()
697 args.v5.asStreamParam.ucDigMode = in amdgpu_atombios_encoder_setup_dig_encoder()
699 if (ENCODER_MODE_IS_DP(args.v5.asStreamParam.ucDigMode)) in amdgpu_atombios_encoder_setup_dig_encoder()
700 args.v5.asStreamParam.ucLaneNum = dp_lane_count; in amdgpu_atombios_encoder_setup_dig_encoder()
703 args.v5.asStreamParam.ucLaneNum = 8; in amdgpu_atombios_encoder_setup_dig_encoder()
[all …]
Datombios_crtc.c463 PIXEL_CLOCK_PARAMETERS_V5 v5; member
492 args.v5.ucCRTC = ATOM_CRTC_INVALID; in amdgpu_atombios_crtc_set_disp_eng_pll()
493 args.v5.usPixelClock = cpu_to_le16(dispclk); in amdgpu_atombios_crtc_set_disp_eng_pll()
494 args.v5.ucPpll = ATOM_DCPLL; in amdgpu_atombios_crtc_set_disp_eng_pll()
644 args.v5.ucCRTC = crtc_id; in amdgpu_atombios_crtc_program_pll()
645 args.v5.usPixelClock = cpu_to_le16(clock / 10); in amdgpu_atombios_crtc_program_pll()
646 args.v5.ucRefDiv = ref_div; in amdgpu_atombios_crtc_program_pll()
647 args.v5.usFbDiv = cpu_to_le16(fb_div); in amdgpu_atombios_crtc_program_pll()
648 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); in amdgpu_atombios_crtc_program_pll()
649 args.v5.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll()
[all …]
Damdgpu_atombios.c991 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5; member
1037 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock); in amdgpu_atombios_get_clock_dividers()
1039 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN; in amdgpu_atombios_get_clock_dividers()
1043 dividers->post_div = args.v5.ucPostDiv; in amdgpu_atombios_get_clock_dividers()
1044 dividers->enable_post_div = (args.v5.ucCntlFlag & in amdgpu_atombios_get_clock_dividers()
1046 dividers->enable_dithen = (args.v5.ucCntlFlag & in amdgpu_atombios_get_clock_dividers()
1048 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv); in amdgpu_atombios_get_clock_dividers()
1049 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac); in amdgpu_atombios_get_clock_dividers()
1050 dividers->ref_div = args.v5.ucRefDiv; in amdgpu_atombios_get_clock_dividers()
1051 dividers->vco_mode = (args.v5.ucCntlFlag & in amdgpu_atombios_get_clock_dividers()
/drivers/gpu/drm/amd/display/dc/calcs/
Ddcn_calc_math.c101 float dcn_bw_max5(float v1, float v2, float v3, float v4, float v5) in dcn_bw_max5() argument
103 …return dcn_bw_max3(v1, v2, v3) > dcn_bw_max2(v4, v5) ? dcn_bw_max3(v1, v2, v3) : dcn_bw_max2(v4, v… in dcn_bw_max5()
/drivers/gpu/drm/radeon/
Datombios_encoders.c1010 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5; member
1311 args.v5.ucAction = action; in atombios_dig_transmitter_setup2()
1313 args.v5.usSymClock = cpu_to_le16(dp_clock / 10); in atombios_dig_transmitter_setup2()
1315 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); in atombios_dig_transmitter_setup2()
1320 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB; in atombios_dig_transmitter_setup2()
1322 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA; in atombios_dig_transmitter_setup2()
1326 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD; in atombios_dig_transmitter_setup2()
1328 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC; in atombios_dig_transmitter_setup2()
1332 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF; in atombios_dig_transmitter_setup2()
1334 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE; in atombios_dig_transmitter_setup2()
[all …]
Datombios_crtc.c766 PIXEL_CLOCK_PARAMETERS_V5 v5; member
794 args.v5.ucCRTC = ATOM_CRTC_INVALID; in atombios_crtc_set_disp_eng_pll()
795 args.v5.usPixelClock = cpu_to_le16(dispclk); in atombios_crtc_set_disp_eng_pll()
796 args.v5.ucPpll = ATOM_DCPLL; in atombios_crtc_set_disp_eng_pll()
890 args.v5.ucCRTC = crtc_id; in atombios_crtc_program_pll()
891 args.v5.usPixelClock = cpu_to_le16(clock / 10); in atombios_crtc_program_pll()
892 args.v5.ucRefDiv = ref_div; in atombios_crtc_program_pll()
893 args.v5.usFbDiv = cpu_to_le16(fb_div); in atombios_crtc_program_pll()
894 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); in atombios_crtc_program_pll()
895 args.v5.ucPostDiv = post_div; in atombios_crtc_program_pll()
[all …]
Dradeon_atombios.c2826 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5; member
2898 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock); in radeon_atom_get_clock_dividers()
2900 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN; in radeon_atom_get_clock_dividers()
2904 dividers->post_div = args.v5.ucPostDiv; in radeon_atom_get_clock_dividers()
2905 dividers->enable_post_div = (args.v5.ucCntlFlag & in radeon_atom_get_clock_dividers()
2907 dividers->enable_dithen = (args.v5.ucCntlFlag & in radeon_atom_get_clock_dividers()
2909 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv); in radeon_atom_get_clock_dividers()
2910 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac); in radeon_atom_get_clock_dividers()
2911 dividers->ref_div = args.v5.ucRefDiv; in radeon_atom_get_clock_dividers()
2912 dividers->vco_mode = (args.v5.ucCntlFlag & in radeon_atom_get_clock_dividers()
/drivers/ufs/host/
Dufs-mediatek.h188 unsigned long v5; member
196 s.cmd, s.v1, s.v2, s.v3, s.v4, s.v5, s.v6, s.res); in _ufs_mtk_smc()
/drivers/crypto/ccp/
DMakefile7 ccp-dev-v5.o \
/drivers/net/wireless/intel/iwlwifi/fw/api/
Dpower.h376 struct iwl_dev_tx_power_cmd_v5 v5; member
/drivers/video/fbdev/sis/
Dsis_main.c4353 u8 reg, v1, v2, v3, v4, v5, v6, v7, v8; in sisfb_post_sis300() local
4374 v4 = 0x44; v5 = 0x42; in sisfb_post_sis300()
4377 v4 = 0x68; v5 = 0x43; /* Assume 125Mhz ECLK */ in sisfb_post_sis300()
4386 v5 = bios[rindex++]; in sisfb_post_sis300()
4394 SiS_SetReg(SISSR, 0x2f, v5); in sisfb_post_sis300()
4405 v5 = 0x06; v6 = 0x00; v7 = 0x00; v8 = 0x00; in sisfb_post_sis300()
4412 v5 = bios[memtype + 32]; in sisfb_post_sis300()
4423 SiS_SetReg(SISSR, 0x19, v5); in sisfb_post_sis300()
4467 v4 = 0x00; v5 = 0x00; v6 = 0x10; in sisfb_post_sis300()
4470 v5 = bios[0xf6]; in sisfb_post_sis300()
[all …]
/drivers/remoteproc/
DKconfig192 tristate "Qualcomm Hexagon v5 Peripheral Authentication Service support"
207 for the Qualcomm Hexagon v5 based remote processors. This is commonly
/drivers/net/wireless/broadcom/brcm80211/brcmfmac/
Dfwil_types.h621 } v5; member
/drivers/net/wireless/intel/iwlwifi/mvm/
Dfw.c729 len = sizeof(cmd.v5); in iwl_mvm_sar_select_profile()
731 per_chain = cmd.v5.per_chain[0][0]; in iwl_mvm_sar_select_profile()
Dmac80211.c1311 len = sizeof(cmd.v5); in iwl_mvm_set_tx_power()
/drivers/net/wireless/realtek/rtlwifi/rtl8723be/
Dphy.c712 u32 v1 = 0, v2 = 0, v3 = 0, v4 = 0, v5 = 0, v6 = 0; in _rtl8723be_phy_config_bb_with_pgheaderfile() local
723 v5 = phy_regarray_table_pg[i+4]; in _rtl8723be_phy_config_bb_with_pgheaderfile()
732 v1, v2, v3, v4, v5, v6); in _rtl8723be_phy_config_bb_with_pgheaderfile()
/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/
Dphy.c858 u32 v1 = 0, v2 = 0, v3 = 0, v4 = 0, v5 = 0, v6 = 0; in phy_config_bb_with_pghdrfile() local
869 v5 = phy_regarray_table_pg[i+4]; in phy_config_bb_with_pghdrfile()
874 v4, v5, v6); in phy_config_bb_with_pghdrfile()
/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
Dphy.c1991 u32 v1, v2, v3, v4, v5, v6; in _rtl8821ae_phy_config_bb_with_pgheaderfile() local
2011 v5 = array[i+4]; in _rtl8821ae_phy_config_bb_with_pgheaderfile()
2036 v4, v5, v6); in _rtl8821ae_phy_config_bb_with_pgheaderfile()