| /drivers/iio/common/hid-sensors/ |
| D | hid-sensor-attributes.c | 355 static void adjust_exponent_nano(int *val0, int *val1, int scale0, in adjust_exponent_nano() argument
365 *val0 = scale0 * int_pow(10, exp); in adjust_exponent_nano()
377 *val0 += res; in adjust_exponent_nano()
382 *val0 = *val1 = 0; in adjust_exponent_nano()
386 *val0 = scale0 / divisor; in adjust_exponent_nano()
397 *val0 = scale0; in adjust_exponent_nano()
404 int *val0, int *val1) in hid_sensor_format_scale() argument
409 *val0 = 1; in hid_sensor_format_scale()
417 adjust_exponent_nano(val0, val1, in hid_sensor_format_scale()
559 int val0, val1; in hid_sensor_parse_common_attributes() local
[all …]
|
| /drivers/soc/rockchip/ |
| D | io-domain.c | 86 u32 val0, val1; in rk3568_iodomain_write() local
94 val0 = BIT(16 + b) | (is_3v3 ? 0 : BIT(b)); in rk3568_iodomain_write()
98 regmap_write(iod->grf, RK3568_PMU_GRF_IO_VSEL2, val0); in rk3568_iodomain_write()
110 val0 = BIT(16 + b) | (is_3v3 ? 0 : BIT(b)); in rk3568_iodomain_write()
113 regmap_write(iod->grf, RK3568_PMU_GRF_IO_VSEL0, val0); in rk3568_iodomain_write()
|
| /drivers/gpu/drm/msm/adreno/ |
| D | a6xx_gpu_state.h | 168 u32 val0; member
173 { .val0 = _base, .val1 = _type, .registers = _array, \
281 .val0 = _sel_reg, .val1 = _sel_val }
|
| D | a6xx_gpu_state.c | 650 regs->registers[i] - (regs->val0 >> 2); in a6xx_get_crashdumper_hlsq_registers()
684 if (regs->val0) in a6xx_get_crashdumper_registers()
685 in += CRASHDUMP_WRITE(in, regs->val0, regs->val1); in a6xx_get_crashdumper_registers()
|
| /drivers/net/ethernet/chelsio/cxgb/ |
| D | pm3393.c | 429 t1_tpi_read((mac)->adapter, OFFSET(name), &val0); \
432 (mac)->stats.stat_name = (u64)(val0 & 0xffff) | \
446 u32 val0, val1, val2, val3; in pm3393_update_statistics() local
453 pmread(mac, SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_0, &val0); in pm3393_update_statistics()
457 ro = ((u64)val0 & 0xffff) | (((u64)val1 & 0xffff) << 16) | in pm3393_update_statistics()
|
| /drivers/misc/sgi-gru/ |
| D | grulib.h | 97 int val0; member
|
| D | grufault.c | 875 if (req.val0 < -1 || req.val0 >= GRU_CHIPLETS_PER_HUB || in gru_set_context_option()
881 gts->ts_user_chiplet_id = req.val0; in gru_set_context_option()
|
| /drivers/media/usb/gspca/ |
| D | ov519.c | 2914 unsigned char val0, val1; in ov51x_upload_quan_tables() local
2930 val0 = *pYTable++; in ov51x_upload_quan_tables()
2932 val0 &= 0x0f; in ov51x_upload_quan_tables()
2934 val0 |= val1 << 4; in ov51x_upload_quan_tables()
2935 reg_w(sd, reg, val0); in ov51x_upload_quan_tables()
2937 val0 = *pUVTable++; in ov51x_upload_quan_tables()
2939 val0 &= 0x0f; in ov51x_upload_quan_tables()
2941 val0 |= val1 << 4; in ov51x_upload_quan_tables()
2942 reg_w(sd, reg + size, val0); in ov51x_upload_quan_tables()
|
| /drivers/gpu/drm/mga/ |
| D | mga_drv.h | 338 #define DMA_BLOCK(reg0, val0, reg1, val1, reg2, val2, reg3, val3) \ argument
344 DMA_WRITE(1, val0); \
|
| /drivers/thunderbolt/ |
| D | icm.c | 1843 u32 val0, val1; in icm_reset_phy_port() local
1861 ret = pcie2cio_read(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, &val0); in icm_reset_phy_port()
1868 state0 = val0 & PHY_PORT_CS1_LINK_STATE_MASK; in icm_reset_phy_port()
1877 val0 |= PHY_PORT_CS1_LINK_DISABLE; in icm_reset_phy_port()
1878 ret = pcie2cio_write(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, val0); in icm_reset_phy_port()
1890 ret = pcie2cio_read(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, &val0); in icm_reset_phy_port()
1897 val0 &= ~PHY_PORT_CS1_LINK_DISABLE; in icm_reset_phy_port()
1898 ret = pcie2cio_write(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, val0); in icm_reset_phy_port()
|
| /drivers/clk/nxp/ |
| D | clk-lpc32xx.c | 373 static inline bool pll_is_valid(u64 val0, u64 val1, u64 min, u64 max) in pll_is_valid() argument
375 return (val0 >= (val1 * min) && val0 <= (val1 * max)); in pll_is_valid()
|
| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_ring.h | 293 uint32_t reg0, uint32_t val0,
|
| /drivers/infiniband/hw/qib/ |
| D | qib_sd7220.c | 1003 #define RXEQ_VAL(elt, adr, val0, val1, val2, val3) \ argument
1004 {RXEQ_INIT_RDESC((elt), (adr)), {(val0), (val1), (val2), (val3)} }
|
| /drivers/staging/media/atomisp/i2c/ |
| D | mt9m114.h | 234 u32 val0; member
|
| /drivers/staging/media/ipu3/ |
| D | ipu3-css.c | 467 u32 val0 = imgu_css_gdc_lut[0][i] & IMGU_GDC_LUT_MASK; in imgu_css_hw_init() local
472 writel(val0 | (val1 << 16), in imgu_css_hw_init()
|