Home
last modified time | relevance | path

Searched refs:vba (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dml/dcn20/
Ddisplay_mode_vba_20.c237 mode_lib->vba.FabricAndDRAMBandwidth = dml_min( in dml20_recalculate()
238 mode_lib->vba.DRAMSpeed * mode_lib->vba.NumberOfChannels * mode_lib->vba.DRAMChannelWidth, in dml20_recalculate()
239 mode_lib->vba.FabricClock * mode_lib->vba.FabricDatapathToDCNDataReturn) / 1000.0; in dml20_recalculate()
255 > mode_lib->vba.DCFCLK * mode_lib->vba.ReturnBusWidth / 4.0) in adjust_ReturnBW()
261 - mode_lib->vba.UrgentLatencyPixelDataOnly in adjust_ReturnBW()
262 / ((mode_lib->vba.ROBBufferSizeInKByte in adjust_ReturnBW()
263 - mode_lib->vba.PixelChunkSizeInKByte) in adjust_ReturnBW()
266 - mode_lib->vba.DCFCLK in adjust_ReturnBW()
267 * mode_lib->vba.ReturnBusWidth in adjust_ReturnBW()
269 + mode_lib->vba.UrgentLatencyPixelDataOnly)); in adjust_ReturnBW()
[all …]
Ddisplay_mode_vba_20v2.c261 mode_lib->vba.FabricAndDRAMBandwidth = dml_min( in dml20v2_recalculate()
262 mode_lib->vba.DRAMSpeed * mode_lib->vba.NumberOfChannels * mode_lib->vba.DRAMChannelWidth, in dml20v2_recalculate()
263 mode_lib->vba.FabricClock * mode_lib->vba.FabricDatapathToDCNDataReturn) / 1000.0; in dml20v2_recalculate()
279 > mode_lib->vba.DCFCLK * mode_lib->vba.ReturnBusWidth / 4.0) in adjust_ReturnBW()
285 - mode_lib->vba.UrgentLatencyPixelDataOnly in adjust_ReturnBW()
286 / ((mode_lib->vba.ROBBufferSizeInKByte in adjust_ReturnBW()
287 - mode_lib->vba.PixelChunkSizeInKByte) in adjust_ReturnBW()
290 - mode_lib->vba.DCFCLK in adjust_ReturnBW()
291 * mode_lib->vba.ReturnBusWidth in adjust_ReturnBW()
293 + mode_lib->vba.UrgentLatencyPixelDataOnly)); in adjust_ReturnBW()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/
Ddisplay_mode_vba.c56 bool need_recalculate = memcmp(&mode_lib->soc, &mode_lib->vba.soc, sizeof(mode_lib->vba.soc)) != 0 in dml_get_voltage_level()
57 || memcmp(&mode_lib->ip, &mode_lib->vba.ip, sizeof(mode_lib->vba.ip)) != 0 in dml_get_voltage_level()
58 || num_pipes != mode_lib->vba.cache_num_pipes in dml_get_voltage_level()
59 || memcmp(pipes, mode_lib->vba.cache_pipes, in dml_get_voltage_level()
62 mode_lib->vba.soc = mode_lib->soc; in dml_get_voltage_level()
63 mode_lib->vba.ip = mode_lib->ip; in dml_get_voltage_level()
64 memcpy(mode_lib->vba.cache_pipes, pipes, sizeof(*pipes) * num_pipes); in dml_get_voltage_level()
65 mode_lib->vba.cache_num_pipes = num_pipes; in dml_get_voltage_level()
77 return mode_lib->vba.VoltageLevel; in dml_get_voltage_level()
86 dml_get_attr_func(clk_dcf_deepsleep, mode_lib->vba.DCFCLKDeepSleep);
[all …]
Ddisplay_mode_lib.c266 for (i = mode_lib->vba.soc.num_states; i >= 0; i--) { in dml_log_mode_support_params()
269 …dml_print("DML SUPPORT: Mode Supported : %s\n", mode_lib->vba.ModeSupport[i][0] ?… in dml_log_mode_support_params()
270 …dml_print("DML SUPPORT: Mode Supported (pipe split) : %s\n", mode_lib->vba.ModeSupport[i][1] ?… in dml_log_mode_support_params()
271 …dml_print("DML SUPPORT: Scale Ratio And Taps : %s\n", mode_lib->vba.ScaleRatioA… in dml_log_mode_support_params()
272 …dml_print("DML SUPPORT: Source Format Pixel And Scan : %s\n", mode_lib->vba.SourceForma… in dml_log_mode_support_params()
273 … : [%s, %s]\n", mode_lib->vba.ViewportSizeSupport[i][0] ? "Supported" : "NOT Supported… in dml_log_mode_support_params()
274 …dml_print("DML SUPPORT: DIO Support : %s\n", mode_lib->vba.DIOSupport[… in dml_log_mode_support_params()
275 …dml_print("DML SUPPORT: ODM Combine 4To1 Support Check : %s\n", mode_lib->vba.ODMCombine4… in dml_log_mode_support_params()
276 …dml_print("DML SUPPORT: DSC Units : %s\n", mode_lib->vba.NotEnoughDS… in dml_log_mode_support_params()
277 …dml_print("DML SUPPORT: DSCCLK Required : %s\n", mode_lib->vba.DSCCLKRequi… in dml_log_mode_support_params()
[all …]
Ddisplay_mode_lib.h72 struct vba_vars_st vba; member
/drivers/gpu/drm/amd/display/dc/dml/dcn21/
Ddisplay_mode_vba_21.c1227 if (!mode_lib->vba.IgnoreViewportPositioning) { in CalculatePrefetchSourceLines()
1334 …MPDEBytesFrame = 128 * ((mode_lib->vba.GPUVMMaxPageTableLevels + 1) * (mode_lib->vba.HostVMMaxPage… in CalculateVMAndRowBytes()
1364 …if (GPUVMEnable == true && (mode_lib->vba.GPUVMMaxPageTableLevels + 1) * (mode_lib->vba.HostVMMaxP… in CalculateVMAndRowBytes()
1370 …ExtraDPDEBytesFrame = 128 * ((mode_lib->vba.GPUVMMaxPageTableLevels + 1) * (mode_lib->vba.HostVMMa… in CalculateVMAndRowBytes()
1469 struct vba_vars_st *locals = &mode_lib->vba; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1472 mode_lib->vba.WritebackDISPCLK = 0.0; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1473 mode_lib->vba.DISPCLKWithRamping = 0; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1474 mode_lib->vba.DISPCLKWithoutRamping = 0; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1475 mode_lib->vba.GlobalDPPCLK = 0.0; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1479 for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
[all …]
/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_resource.c1118 …_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.d… in dcn21_calculate_wm()
1122 … context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; in dcn21_calculate_wm()
1123 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx) in dcn21_calculate_wm()
1125 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx]; in dcn21_calculate_wm()
1131 …context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_… in dcn21_calculate_wm()
1132 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i]) in dcn21_calculate_wm()
1134 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]]; in dcn21_calculate_wm()
1238 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn21_fast_validate_bw() local
1244 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled in dcn21_fast_validate_bw()
1268 …if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn21_fast_validate_bw()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn30/
Ddisplay_mode_vba_30.c1697 if (!mode_lib->vba.IgnoreViewportPositioning) { in CalculatePrefetchSourceLines()
1801 MPDEBytesFrame = 128 * (mode_lib->vba.GPUVMMaxPageTableLevels - 1); in CalculateVMAndRowBytes()
1822 if (GPUVMEnable == true && mode_lib->vba.GPUVMMaxPageTableLevels > 1) { in CalculateVMAndRowBytes()
1828 ExtraDPDEBytesFrame = 128 * (mode_lib->vba.GPUVMMaxPageTableLevels - 2); in CalculateVMAndRowBytes()
1924 struct vba_vars_st *v = &mode_lib->vba; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3169 for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { in DisplayPipeConfiguration()
3172 mode_lib->vba.SourcePixelFormat[k], in DisplayPipeConfiguration()
3173 mode_lib->vba.SurfaceTiling[k], in DisplayPipeConfiguration()
3185 mode_lib->vba.NumberOfActivePlanes, in DisplayPipeConfiguration()
3186 mode_lib->vba.DETBufferSizeInKByte[0], in DisplayPipeConfiguration()
[all …]
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_resource.c1635 …wb_arb_params->dram_speed_change_duration = dml->vba.WritebackAllowDRAMClockChangeEndPosition[j] *… in dcn30_set_mcif_arb_params()
1877 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn30_internal_validate_bw() local
1907 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) { in dcn30_internal_validate_bw()
1939 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled in dcn30_internal_validate_bw()
2007 odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled; in dcn30_internal_validate_bw()
2093 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; in dcn30_internal_validate_bw()
2131 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn30_calculate_wm_and_dlg_fp()
2132 …bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.ma… in dcn30_calculate_wm_and_dlg_fp()
2194 unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed; in dcn30_calculate_wm_and_dlg_fp()
2197 …if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == … in dcn30_calculate_wm_and_dlg_fp()
[all …]
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_resource.c2634 struct vba_vars_st *v = &context->bw_ctx.dml.vba; in dcn20_validate_apply_pipe_split_flags()
2857 …if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn20_fast_validate_bw()
2876 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) in dcn20_fast_validate_bw()
2885 … context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2; in dcn20_fast_validate_bw()
2888 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn20_fast_validate_bw()
2910 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = in dcn20_fast_validate_bw()
2942 …pe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml… in dcn20_calculate_wm()
2946 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; in dcn20_calculate_wm()
2947 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx) in dcn20_calculate_wm()
2949 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]; in dcn20_calculate_wm()
[all …]
/drivers/parisc/
Dccio-dma.c556 ccio_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba, in ccio_io_pdir_entry() argument
570 pa = lpa(vba); in ccio_io_pdir_entry()
595 asm volatile ("lci %%r0(%1), %0" : "=r" (ci) : "r" (vba)); in ccio_io_pdir_entry()
Dsba_iommu.c566 sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba, in sba_io_pdir_entry() argument
572 pa = lpa(vba); in sba_io_pdir_entry()
575 asm("lci 0(%1), %0" : "=r" (ci) : "r" (vba)); in sba_io_pdir_entry()
/drivers/gpu/drm/amd/display/dc/dcn31/
Ddcn31_resource.c1666 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn31_calculate_wm_and_dlg_fp()
1846 …dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_st… in dcn31_validate_bandwidth()
/drivers/gpu/drm/amd/display/dc/dml/dcn31/
Ddisplay_mode_vba_31.c1798 struct vba_vars_st *v = &mode_lib->vba;
1880 struct vba_vars_st *v = &mode_lib->vba;
2052 struct vba_vars_st *v = &mode_lib->vba;
3328 struct vba_vars_st *v = &mode_lib->vba;
3640 struct vba_vars_st *v = &mode_lib->vba;
3828 struct vba_vars_st *v = &mode_lib->vba;
3846 mode_lib->vba.AllowDRAMSelfRefreshOrDRAMClockChangeInVblank,
5585 struct vba_vars_st *v = &mode_lib->vba;
5785 struct vba_vars_st *v = &mode_lib->vba;
6369 struct vba_vars_st *v = &mode_lib->vba;
[all …]