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Searched refs:vddc_dependency_on_sclk (Results 1 – 19 of 19) sorted by relevance

/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dsmu8_hwmgr.c104 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_get_sclk_level()
262 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_construct_max_power_limits_table()
444 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_upload_pptable_to_smu()
558 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_init_sclk_limit()
687 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_update_sclk_limit()
1162 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_phm_unforce_dpm_levels()
1373 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_dpm_get_pp_table_entry_callback()
1549 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_print_clock_levels()
1648 table = hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_get_clock_by_type()
1667 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_get_max_high_clocks()
[all …]
Dprocesspptables.c1324 hwmgr->dyn_state.vddc_dependency_on_sclk = NULL; in init_clock_voltage_dependency()
1420 &hwmgr->dyn_state.vddc_dependency_on_sclk, table); in init_clock_voltage_dependency()
1452 if(result == 0 && (NULL != hwmgr->dyn_state.vddc_dependency_on_sclk) && in init_clock_voltage_dependency()
1453 (0 != hwmgr->dyn_state.vddc_dependency_on_sclk->count)) in init_clock_voltage_dependency()
1456 hwmgr->dyn_state.vddc_dependency_on_sclk); in init_clock_voltage_dependency()
1754 kfree(hwmgr->dyn_state.vddc_dependency_on_sclk); in pp_tables_uninitialize()
1755 hwmgr->dyn_state.vddc_dependency_on_sclk = NULL; in pp_tables_uninitialize()
Dppatomctrl.c1162 for (entry_id = 0; entry_id < hwmgr->dyn_state.vddc_dependency_on_sclk->count; entry_id++) { in atomctrl_get_voltage_evv()
1163 if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].v == virtual_voltage_id) { in atomctrl_get_voltage_evv()
1169 if (entry_id >= hwmgr->dyn_state.vddc_dependency_on_sclk->count) { in atomctrl_get_voltage_evv()
1178 cpu_to_le32(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].clk); in atomctrl_get_voltage_evv()
Dsmu7_hwmgr.c786 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu7_setup_dpm_tables_v0()
2739 tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_sclk); in smu7_patch_dependency_tables_with_leakage()
2795 …clock_voltage_dependency_table *allowed_sclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_sclk; in smu7_set_private_data_based_on_pptable_v0()
3147 for (count = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1; in smu7_get_profiling_clk()
3149 if (tmp_sclk >= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk) { in smu7_get_profiling_clk()
3150 tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk; in smu7_get_profiling_clk()
3157 tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].clk; in smu7_get_profiling_clk()
3161 *sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1; in smu7_get_profiling_clk()
5132 sclk_table = hwmgr->dyn_state.vddc_dependency_on_sclk; in smu7_get_sclks()
/drivers/gpu/drm/amd/pm/powerplay/smumgr/
Diceland_smumgr.c400 …_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_on_sclk->count, in iceland_populate_bapm_vddc_vid_sidd()
540 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk, in iceland_get_std_voltage_value_sidd()
554 for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { in iceland_get_std_voltage_value_sidd()
555 if (tab->value == hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) { in iceland_get_std_voltage_value_sidd()
574 …for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { in iceland_get_std_voltage_value_sidd()
575 if (tab->value <= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) { in iceland_get_std_voltage_value_sidd()
734 if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) in iceland_populate_ulv_level()
738 …state->VddcOffset = (uint16_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltag… in iceland_populate_ulv_level()
741 if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) in iceland_populate_ulv_level()
745 (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage) in iceland_populate_ulv_level()
[all …]
Dci_smumgr.c418 hwmgr->dyn_state.vddc_dependency_on_sclk, clock, in ci_populate_single_graphic_level()
588 …_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_on_sclk->count, in ci_populate_bapm_vddc_vid_sidd()
772 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk, in ci_get_std_voltage_value_sidd()
781 for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { in ci_get_std_voltage_value_sidd()
782 if (tab->value == hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) { in ci_get_std_voltage_value_sidd()
797 …for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { in ci_get_std_voltage_value_sidd()
798 if (tab->value <= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) { in ci_get_std_voltage_value_sidd()
966 if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) in ci_populate_ulv_level()
970 …state->VddcOffset = (uint16_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltag… in ci_populate_ulv_level()
973 if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) in ci_populate_ulv_level()
[all …]
/drivers/gpu/drm/radeon/
Dkv_dpm.c399 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid2_to_vid7()
421 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid7_to_vid2()
562 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_program_bootup_state()
923 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_calculate_dfs_bypass_settings()
1533 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_set_valid_clock_range()
1905 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_get_high_voltage_limit()
1946 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_apply_state_adjust_rules()
2150 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_init_graphics_levels()
Dr600_dpm.c926 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in r600_parse_extended_power_table()
938 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries); in r600_parse_extended_power_table()
949 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries); in r600_parse_extended_power_table()
961 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries); in r600_parse_extended_power_table()
1302 kfree(dyn_state->vddc_dependency_on_sclk.entries); in r600_free_extended_power_table()
Dci_dpm.c264 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count) in ci_populate_bapm_vddc_vid_sidd()
2301 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) in ci_get_std_voltage_value_sidd()
2305 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in ci_get_std_voltage_value_sidd()
2307 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in ci_get_std_voltage_value_sidd()
2322 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in ci_get_std_voltage_value_sidd()
2324 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in ci_get_std_voltage_value_sidd()
2557 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) { in ci_populate_smc_initial_state()
2558 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >= in ci_populate_smc_initial_state()
3101 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) in ci_populate_ulv_level()
3105 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage; in ci_populate_ulv_level()
[all …]
Dbtc_dpm.c2207 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in btc_apply_state_adjust_rules()
2216 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in btc_apply_state_adjust_rules()
2225 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in btc_apply_state_adjust_rules()
Dsi_dpm.c3029 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
3135 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
4137 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) in si_get_std_voltage_value()
4140 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value()
4142 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in si_get_std_voltage_value()
4155 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value()
4157 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in si_get_std_voltage_value()
5886 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); in si_patch_dependency_tables_based_on_leakage()
Dradeon_atombios.c3310 u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; in radeon_atom_get_voltage_evv()
3314 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v == in radeon_atom_get_voltage_evv()
3326 cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk); in radeon_atom_get_voltage_evv()
Dni_dpm.c873 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in ni_apply_state_adjust_rules()
1012 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); in ni_patch_dependency_tables_based_on_leakage()
Dradeon.h1506 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; member
/drivers/gpu/drm/amd/pm/powerplay/
Dkv_dpm.c76 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid2_to_vid7()
98 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid7_to_vid2()
803 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_program_bootup_state()
1164 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_calculate_dfs_bypass_settings()
1764 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_set_valid_clock_range()
2160 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_get_high_voltage_limit()
2201 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_apply_state_adjust_rules()
2405 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_init_graphics_levels()
Dsi_dpm.c3487 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
3593 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
4599 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) in si_get_std_voltage_value()
4602 …for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value()
4604 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in si_get_std_voltage_value()
4617 …for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value()
4619 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in si_get_std_voltage_value()
6337 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk); in si_patch_dependency_tables_based_on_leakage()
/drivers/gpu/drm/amd/pm/inc/
Damdgpu_dpm.h208 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; member
Dhwmgr.h634 struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk; member
/drivers/gpu/drm/amd/pm/
Damdgpu_dpm.c339 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in amdgpu_parse_extended_power_table()
728 kfree(dyn_state->vddc_dependency_on_sclk.entries); in amdgpu_free_extended_power_table()