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/drivers/gpu/drm/vmwgfx/
Dvmwgfx_so.c129 struct vmw_view *view = vmw_view(res); in vmw_view_commit_notify() local
134 struct vmw_surface *srf = vmw_res_to_srf(view->srf); in vmw_view_commit_notify()
136 list_add_tail(&view->srf_head, &srf->view_list); in vmw_view_commit_notify()
137 vmw_cotable_add_resource(view->cotable, &view->cotable_head); in vmw_view_commit_notify()
138 view->committed = true; in vmw_view_commit_notify()
139 res->id = view->view_id; in vmw_view_commit_notify()
142 list_del_init(&view->cotable_head); in vmw_view_commit_notify()
143 list_del_init(&view->srf_head); in vmw_view_commit_notify()
144 view->committed = false; in vmw_view_commit_notify()
160 struct vmw_view *view = vmw_view(res); in vmw_view_create() local
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Dvmwgfx_execbuf.c393 struct vmw_resource *view) in vmw_view_res_val_add() argument
401 ret = vmw_execbuf_res_noctx_val_add(sw_context, vmw_view_srf(view), in vmw_view_res_val_add()
402 vmw_view_dirtying(view)); in vmw_view_res_val_add()
406 return vmw_execbuf_res_noctx_val_add(sw_context, view, in vmw_view_res_val_add()
430 struct vmw_resource *view; in vmw_view_id_val_add() local
436 view = vmw_view_lookup(sw_context->man, view_type, id); in vmw_view_id_val_add()
437 if (IS_ERR(view)) in vmw_view_id_val_add()
438 return view; in vmw_view_id_val_add()
440 ret = vmw_view_res_val_add(sw_context, view); in vmw_view_id_val_add()
444 return view; in vmw_view_id_val_add()
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/drivers/s390/char/
Draw3270.c46 struct raw3270_view *view; /* Active view. */ member
238 __raw3270_start(struct raw3270 *rp, struct raw3270_view *view, in __raw3270_start() argument
241 rq->view = view; in __raw3270_start()
242 raw3270_get_view(view); in __raw3270_start()
249 raw3270_put_view(view); in __raw3270_start()
258 raw3270_view_active(struct raw3270_view *view) in raw3270_view_active() argument
260 struct raw3270 *rp = view->dev; in raw3270_view_active()
262 return rp && rp->view == view; in raw3270_view_active()
266 raw3270_start(struct raw3270_view *view, struct raw3270_request *rq) in raw3270_start() argument
272 spin_lock_irqsave(get_ccwdev_lock(view->dev->cdev), flags); in raw3270_start()
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Dcon3270.c43 struct raw3270_view view; member
98 codepage_convert(cp->view.ascebc, cp->status->string + 24, 7); in con3270_update_status()
114 raw3270_buffer_address(cp->view.dev, cp->status->string + 1, in con3270_create_status()
115 cp->view.cols * (cp->view.rows - 1)); in con3270_create_status()
116 raw3270_buffer_address(cp->view.dev, cp->status->string + 21, in con3270_create_status()
117 cp->view.cols * cp->view.rows - 8); in con3270_create_status()
119 codepage_convert(cp->view.ascebc, cp->status->string + 8, 12); in con3270_create_status()
120 codepage_convert(cp->view.ascebc, cp->status->string + 24, 7); in con3270_create_status()
136 raw3270_buffer_address(cp->view.dev, s->string + s->len - 3, in con3270_update_string()
137 cp->view.cols * (nr + 1)); in con3270_update_string()
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Dtty3270.c64 struct raw3270_view view; member
147 if (count > tp->view.cols * 2 - 11) in tty3270_update_prompt()
148 count = tp->view.cols * 2 - 11; in tty3270_update_prompt()
152 if (count < tp->view.cols * 2 - 11) { in tty3270_update_prompt()
155 off = tp->view.cols * tp->view.rows - 9; in tty3270_update_prompt()
156 raw3270_buffer_address(tp->view.dev, line->string+count+8, off); in tty3270_update_prompt()
174 sizeof(blueprint) + tp->view.cols * 2 - 9); in tty3270_create_prompt()
181 offset = tp->view.cols * (tp->view.rows - 2); in tty3270_create_prompt()
182 raw3270_buffer_address(tp->view.dev, line->string + 1, offset); in tty3270_create_prompt()
183 offset = tp->view.cols * tp->view.rows - 9; in tty3270_create_prompt()
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Dfs3270.c33 struct raw3270_view view; member
64 fs3270_do_io(struct raw3270_view *view, struct raw3270_request *rq) in fs3270_do_io() argument
69 fp = (struct fs3270 *) view; in fs3270_do_io()
81 rc = raw3270_start(view, rq); in fs3270_do_io()
98 fp = (struct fs3270 *) rq->view; in fs3270_reset_callback()
108 fp = (struct fs3270 *) rq->view; in fs3270_restore_callback()
119 fs3270_activate(struct raw3270_view *view) in fs3270_activate() argument
125 fp = (struct fs3270 *) view; in fs3270_activate()
152 rc = fp->init->rc = raw3270_start_locked(view, fp->init); in fs3270_activate()
168 fp = (struct fs3270 *) rq->view; in fs3270_save_callback()
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Draw3270.h100 struct raw3270_view *view; /* view of this request */ member
176 raw3270_get_view(struct raw3270_view *view) in raw3270_get_view() argument
178 atomic_inc(&view->ref_count); in raw3270_get_view()
184 raw3270_put_view(struct raw3270_view *view) in raw3270_put_view() argument
186 if (atomic_dec_return(&view->ref_count) == 0) in raw3270_put_view()
/drivers/usb/phy/
Dphy-ulpi-viewport.c22 static int ulpi_viewport_wait(void __iomem *view, u32 mask) in ulpi_viewport_wait() argument
26 return readl_poll_timeout_atomic(view, val, !(val & mask), 1, 2000); in ulpi_viewport_wait()
32 void __iomem *view = otg->io_priv; in ulpi_viewport_read() local
34 writel(ULPI_VIEW_WAKEUP | ULPI_VIEW_WRITE, view); in ulpi_viewport_read()
35 ret = ulpi_viewport_wait(view, ULPI_VIEW_WAKEUP); in ulpi_viewport_read()
39 writel(ULPI_VIEW_RUN | ULPI_VIEW_READ | ULPI_VIEW_ADDR(reg), view); in ulpi_viewport_read()
40 ret = ulpi_viewport_wait(view, ULPI_VIEW_RUN); in ulpi_viewport_read()
44 return ULPI_VIEW_DATA_READ(readl(view)); in ulpi_viewport_read()
50 void __iomem *view = otg->io_priv; in ulpi_viewport_write() local
52 writel(ULPI_VIEW_WAKEUP | ULPI_VIEW_WRITE, view); in ulpi_viewport_write()
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/drivers/gpu/drm/nouveau/dispnv50/
Dhead.c68 if (asyh->set.view ) head->func->view (head, asyh); in nv50_head_flush_set()
152 asyh->view.iW = umode->hdisplay; in nv50_head_atomic_check_view()
153 asyh->view.iH = umode_vdisplay; in nv50_head_atomic_check_view()
156 asyh->view.oW = omode_hdisplay; in nv50_head_atomic_check_view()
157 asyh->view.oH = omode_vdisplay; in nv50_head_atomic_check_view()
168 u32 r = (asyh->view.oH << 19) / asyh->view.oW; in nv50_head_atomic_check_view()
171 asyh->view.oW -= (bX * 2); in nv50_head_atomic_check_view()
172 if (bY) asyh->view.oH -= (bY * 2); in nv50_head_atomic_check_view()
173 else asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19; in nv50_head_atomic_check_view()
175 asyh->view.oW -= (asyh->view.oW >> 4) + 32; in nv50_head_atomic_check_view()
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Dhead907d.c390 NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_IN, WIDTH, asyh->view.iW) | in head907d_view()
391 NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_IN, HEIGHT, asyh->view.iH)); in head907d_view()
394 NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT, WIDTH, asyh->view.oW) | in head907d_view()
395 NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT, HEIGHT, asyh->view.oH), in head907d_view()
398 NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT_MIN, WIDTH, asyh->view.oW) | in head907d_view()
399 NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT_MIN, HEIGHT, asyh->view.oH), in head907d_view()
402 NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT_MAX, WIDTH, asyh->view.oW) | in head907d_view()
403 NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT_MAX, HEIGHT, asyh->view.oH)); in head907d_view()
409 .view = head907d_view,
Dhead507d.c417 NVVAL(NV507D, HEAD_SET_VIEWPORT_SIZE_IN, WIDTH, asyh->view.iW) | in head507d_view()
418 NVVAL(NV507D, HEAD_SET_VIEWPORT_SIZE_IN, HEIGHT, asyh->view.iH)); in head507d_view()
421 NVVAL(NV507D, HEAD_SET_VIEWPORT_SIZE_OUT, WIDTH, asyh->view.oW) | in head507d_view()
422 NVVAL(NV507D, HEAD_SET_VIEWPORT_SIZE_OUT, HEIGHT, asyh->view.oH), in head507d_view()
425 NVVAL(NV507D, HEAD_SET_VIEWPORT_SIZE_OUT_MIN, WIDTH, asyh->view.oW) | in head507d_view()
426 NVVAL(NV507D, HEAD_SET_VIEWPORT_SIZE_OUT_MIN, HEIGHT, asyh->view.oH)); in head507d_view()
432 .view = head507d_view,
Dheadc37d.c265 NVVAL(NVC37D, HEAD_SET_VIEWPORT_SIZE_IN, WIDTH, asyh->view.iW) | in headc37d_view()
266 NVVAL(NVC37D, HEAD_SET_VIEWPORT_SIZE_IN, HEIGHT, asyh->view.iH)); in headc37d_view()
269 NVVAL(NVC37D, HEAD_SET_VIEWPORT_SIZE_OUT, WIDTH, asyh->view.oW) | in headc37d_view()
270 NVVAL(NVC37D, HEAD_SET_VIEWPORT_SIZE_OUT, HEIGHT, asyh->view.oH)); in headc37d_view()
285 .view = headc37d_view,
Datom.h33 } view; member
138 bool view:1; member
/drivers/gpu/drm/i915/selftests/
Di915_vma.c65 const struct i915_ggtt_view *view) in checked_vma_instance() argument
70 vma = i915_vma_instance(obj, vm, view); in checked_vma_instance()
87 if (i915_vma_compare(vma, vm, view)) { in checked_vma_instance()
590 struct i915_ggtt_view view = { in igt_vma_rotate_remap() local
595 struct intel_remapped_plane_info *plane_info = view.remapped.plane; in igt_vma_rotate_remap()
604 plane_info[0].dst_stride = view.type == I915_GGTT_VIEW_ROTATED ? in igt_vma_rotate_remap()
608 plane_info[1].dst_stride = view.type == I915_GGTT_VIEW_ROTATED ? in igt_vma_rotate_remap()
618 vma = checked_vma_instance(obj, vm, &view); in igt_vma_rotate_remap()
630 expected_pages = remapped_size(view.type, &plane_info[0], &plane_info[1]); in igt_vma_rotate_remap()
632 if (view.type == I915_GGTT_VIEW_ROTATED && in igt_vma_rotate_remap()
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/drivers/gpu/drm/i915/
Di915_vma.h45 const struct i915_ggtt_view *view);
157 const struct i915_ggtt_view *view) in i915_vma_compare() argument
161 GEM_BUG_ON(view && !i915_is_ggtt_or_dpt(vm)); in i915_vma_compare()
169 if (!view) in i915_vma_compare()
172 cmp -= view->type; in i915_vma_compare()
191 BUILD_BUG_ON(offsetof(typeof(*view), rotated) != in i915_vma_compare()
192 offsetof(typeof(*view), partial)); in i915_vma_compare()
193 BUILD_BUG_ON(offsetof(typeof(*view), rotated) != in i915_vma_compare()
194 offsetof(typeof(*view), remapped)); in i915_vma_compare()
195 return memcmp(&vma->ggtt_view.partial, &view->partial, view->type); in i915_vma_compare()
Di915_vma.c101 const struct i915_ggtt_view *view) in vma_create() argument
134 if (view && view->type != I915_GGTT_VIEW_NORMAL) { in vma_create()
135 vma->ggtt_view = *view; in vma_create()
136 if (view->type == I915_GGTT_VIEW_PARTIAL) { in vma_create()
138 view->partial.offset, in vma_create()
139 view->partial.size, in vma_create()
141 vma->size = view->partial.size; in vma_create()
144 } else if (view->type == I915_GGTT_VIEW_ROTATED) { in vma_create()
145 vma->size = intel_rotation_info_size(&view->rotated); in vma_create()
147 } else if (view->type == I915_GGTT_VIEW_REMAPPED) { in vma_create()
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/drivers/gpu/drm/i915/display/
Dintel_fb.c257 state->view.color_plane[color_plane].stride, in intel_plane_adjust_aligned_offset()
338 int pitch = state->view.color_plane[color_plane].stride; in intel_plane_compute_aligned_offset()
650 struct intel_fb_view *view) in calc_plane_remap_info() argument
653 struct intel_remapped_plane_info *remap_info = &view->gtt.remapped.plane[color_plane]; in calc_plane_remap_info()
654 struct i915_color_plane_view *color_plane_info = &view->color_plane[color_plane]; in calc_plane_remap_info()
666 if (view->gtt.type == I915_GGTT_VIEW_ROTATED) { in calc_plane_remap_info()
667 check_array_bounds(i915, view->gtt.rotated.plane, color_plane); in calc_plane_remap_info()
689 drm_WARN_ON(&i915->drm, view->gtt.type != I915_GGTT_VIEW_REMAPPED); in calc_plane_remap_info()
691 check_array_bounds(i915, view->gtt.remapped.plane, color_plane); in calc_plane_remap_info()
749 static void intel_fb_view_init(struct intel_fb_view *view, enum i915_ggtt_view_type view_type) in intel_fb_view_init() argument
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Dskl_universal_plane.c635 u32 stride = plane_state->view.color_plane[color_plane].stride; in skl_plane_stride()
993 u32 offset = plane_state->view.color_plane[color_plane].offset; in skl_surf_address()
1020 u32 x = plane_state->view.color_plane[color_plane].x; in skl_program_plane()
1021 u32 y = plane_state->view.color_plane[color_plane].y; in skl_program_plane()
1096 (plane_state->view.color_plane[1].y << 16) | in skl_program_plane()
1097 plane_state->view.color_plane[1].x); in skl_program_plane()
1132 u32 surf_addr = plane_state->view.color_plane[0].offset; in skl_plane_async_flip()
1367 int aux_x = plane_state->view.color_plane[ccs_plane].x; in skl_check_main_ccs_coordinates()
1368 int aux_y = plane_state->view.color_plane[ccs_plane].y; in skl_check_main_ccs_coordinates()
1369 u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset; in skl_check_main_ccs_coordinates()
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Di9xx_plane.c275 while ((src_x + src_w) * cpp > plane_state->view.color_plane[0].stride) { in i9xx_check_plane_surface()
315 plane_state->view.color_plane[0].offset = offset; in i9xx_check_plane_surface()
316 plane_state->view.color_plane[0].x = src_x; in i9xx_check_plane_surface()
317 plane_state->view.color_plane[0].y = src_y; in i9xx_check_plane_surface()
428 int x = plane_state->view.color_plane[0].x; in i9xx_update_plane()
429 int y = plane_state->view.color_plane[0].y; in i9xx_update_plane()
443 dspaddr_offset = plane_state->view.color_plane[0].offset; in i9xx_update_plane()
450 plane_state->view.color_plane[0].stride); in i9xx_update_plane()
535 u32 dspaddr_offset = plane_state->view.color_plane[0].offset; in g4x_primary_async_flip()
556 u32 dspaddr_offset = plane_state->view.color_plane[0].offset; in vlv_primary_async_flip()
Dintel_cursor.c49 return base + plane_state->view.color_plane[0].offset; in intel_cursor_base()
129 plane_state->view.color_plane[0].offset = offset; in intel_cursor_check_surface()
130 plane_state->view.color_plane[0].x = src_x; in intel_cursor_check_surface()
131 plane_state->view.color_plane[0].y = src_y; in intel_cursor_check_surface()
198 CURSOR_STRIDE(plane_state->view.color_plane[0].stride); in i845_cursor_ctl()
237 plane_state->view.color_plane[0].stride != fb->pitches[0]); in i845_check_cursor()
458 plane_state->view.color_plane[0].stride != fb->pitches[0]); in i9xx_check_cursor()
Dintel_sprite.c427 u32 sprsurf_offset = plane_state->view.color_plane[0].offset; in vlv_update_plane()
434 u32 x = plane_state->view.color_plane[0].x; in vlv_update_plane()
435 u32 y = plane_state->view.color_plane[0].y; in vlv_update_plane()
450 plane_state->view.color_plane[0].stride); in vlv_update_plane()
844 u32 sprsurf_offset = plane_state->view.color_plane[0].offset; in ivb_update_plane()
851 u32 x = plane_state->view.color_plane[0].x; in ivb_update_plane()
852 u32 y = plane_state->view.color_plane[0].y; in ivb_update_plane()
874 plane_state->view.color_plane[0].stride); in ivb_update_plane()
1172 u32 dvssurf_offset = plane_state->view.color_plane[0].offset; in g4x_update_plane()
1179 u32 x = plane_state->view.color_plane[0].x; in g4x_update_plane()
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Dintel_fb.h53 struct intel_fb_view *view);
/drivers/gpu/drm/i915/gem/
Di915_gem_mman.c198 struct i915_ggtt_view view; in compute_partial_view() local
203 view.type = I915_GGTT_VIEW_PARTIAL; in compute_partial_view()
204 view.partial.offset = rounddown(page_offset, chunk); in compute_partial_view()
205 view.partial.size = in compute_partial_view()
207 (obj->base.size >> PAGE_SHIFT) - view.partial.offset); in compute_partial_view()
211 view.type = I915_GGTT_VIEW_NORMAL; in compute_partial_view()
213 return view; in compute_partial_view()
341 struct i915_ggtt_view view = in vm_fault_gtt() local
346 if (view.type == I915_GGTT_VIEW_NORMAL) in vm_fault_gtt()
354 vma = i915_gem_object_ggtt_pin_ww(obj, &ww, &view, 0, 0, flags); in vm_fault_gtt()
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Di915_gem_domain.c377 const struct i915_ggtt_view *view, in i915_gem_object_pin_to_display_plane() argument
414 (!view || view->type == I915_GGTT_VIEW_NORMAL)) in i915_gem_object_pin_to_display_plane()
415 vma = i915_gem_object_ggtt_pin_ww(obj, ww, view, 0, alignment, in i915_gem_object_pin_to_display_plane()
419 vma = i915_gem_object_ggtt_pin_ww(obj, ww, view, 0, in i915_gem_object_pin_to_display_plane()
/drivers/gpu/drm/i915/gem/selftests/
Di915_gem_mman.c87 struct i915_ggtt_view view; in check_partial_mapping() local
116 view = compute_partial_view(obj, page, MIN_CHUNK_PAGES); in check_partial_mapping()
118 vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE); in check_partial_mapping()
125 n = page - view.partial.offset; in check_partial_mapping()
126 GEM_BUG_ON(n >= view.partial.size); in check_partial_mapping()
152 view.partial.offset, in check_partial_mapping()
153 view.partial.size, in check_partial_mapping()
201 struct i915_ggtt_view view = in check_partial_mappings() local
209 GEM_BUG_ON(view.partial.size > nreal); in check_partial_mappings()
212 vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE); in check_partial_mappings()
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