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Searched refs:vready_after_vcount0 (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dml/dcn31/
Ddisplay_rq_dlg_calc_31.c1144 disp_dlg_regs->vready_after_vcount0 = 1; in dml_rq_dlg_get_dlg_params()
1146 disp_dlg_regs->vready_after_vcount0 = 0; in dml_rq_dlg_get_dlg_params()
1149 disp_dlg_regs->vready_after_vcount0 = 1; in dml_rq_dlg_get_dlg_params()
1151 disp_dlg_regs->vready_after_vcount0 = 0; in dml_rq_dlg_get_dlg_params()
1154 …l_print("DML_DLG: %s: vready_after_vcount0 = %d\n", __func__, disp_dlg_regs->vready_after_vcount0); in dml_rq_dlg_get_dlg_params()
/drivers/gpu/drm/amd/display/dc/dml/dcn20/
Ddisplay_rq_dlg_calc_20v2.c1042 disp_dlg_regs->vready_after_vcount0 = 1; in dml20v2_rq_dlg_get_dlg_params()
1044 disp_dlg_regs->vready_after_vcount0 = 0; in dml20v2_rq_dlg_get_dlg_params()
1049 disp_dlg_regs->vready_after_vcount0 = 1; in dml20v2_rq_dlg_get_dlg_params()
1051 disp_dlg_regs->vready_after_vcount0 = 0; in dml20v2_rq_dlg_get_dlg_params()
Ddisplay_rq_dlg_calc_20.c1041 disp_dlg_regs->vready_after_vcount0 = 1; in dml20_rq_dlg_get_dlg_params()
1043 disp_dlg_regs->vready_after_vcount0 = 0; in dml20_rq_dlg_get_dlg_params()
1048 disp_dlg_regs->vready_after_vcount0 = 1; in dml20_rq_dlg_get_dlg_params()
1050 disp_dlg_regs->vready_after_vcount0 = 0; in dml20_rq_dlg_get_dlg_params()
/drivers/gpu/drm/amd/display/dc/dml/dcn21/
Ddisplay_rq_dlg_calc_21.c1081 disp_dlg_regs->vready_after_vcount0 = 1; in dml_rq_dlg_get_dlg_params()
1083 disp_dlg_regs->vready_after_vcount0 = 0; in dml_rq_dlg_get_dlg_params()
1088 disp_dlg_regs->vready_after_vcount0 = 1; in dml_rq_dlg_get_dlg_params()
1090 disp_dlg_regs->vready_after_vcount0 = 0; in dml_rq_dlg_get_dlg_params()
/drivers/gpu/drm/amd/display/dc/dml/
Ddisplay_rq_dlg_helpers.c311 dlg_regs.vready_after_vcount0); in print__dlg_regs_st()
Ddisplay_mode_structs.h481 unsigned int vready_after_vcount0; member
/drivers/gpu/drm/amd/display/dc/dml/dcn30/
Ddisplay_rq_dlg_calc_30.c1230 disp_dlg_regs->vready_after_vcount0 = 1; in dml_rq_dlg_get_dlg_params()
1232 disp_dlg_regs->vready_after_vcount0 = 0; in dml_rq_dlg_get_dlg_params()
1237 disp_dlg_regs->vready_after_vcount0 = 1; in dml_rq_dlg_get_dlg_params()
1239 disp_dlg_regs->vready_after_vcount0 = 0; in dml_rq_dlg_get_dlg_params()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hw_sequencer_debug.c275 … dlg_regs->chunk_hdl_adjust_cur1, dlg_regs->vready_after_vcount0, dlg_regs->dst_y_delta_drq_limit, in dcn10_get_dlg_states()
Ddcn10_hw_sequencer.c251 … dlg_regs->chunk_hdl_adjust_cur1, dlg_regs->vready_after_vcount0, dlg_regs->dst_y_delta_drq_limit, in dcn10_log_hubp_states()