| /drivers/gpu/drm/i915/gt/ |
| D | intel_workarounds.c | 84 static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) in _wa_add() argument
86 unsigned int addr = i915_mmio_reg_offset(wa->reg); in _wa_add()
96 list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa), in _wa_add()
104 memcpy(list, wal->list, sizeof(*wa) * wal->count); in _wa_add()
121 if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) { in _wa_add()
126 wa_->set &= ~wa->clr; in _wa_add()
130 wa_->set |= wa->set; in _wa_add()
131 wa_->clr |= wa->clr; in _wa_add()
132 wa_->read |= wa->read; in _wa_add()
139 *wa_ = *wa; in _wa_add()
[all …]
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| D | selftest_workarounds.c | 1056 const struct i915_wa *wa = &engine->whitelist.list[i]; in check_whitelisted_registers() local
1058 if (i915_mmio_reg_offset(wa->reg) & in check_whitelisted_registers()
1062 if (!fn(engine, a[i], b[i], wa->reg)) in check_whitelisted_registers()
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| /drivers/crypto/ccp/ |
| D | ccp-ops.c | 64 static void ccp_sg_free(struct ccp_sg_workarea *wa) in ccp_sg_free() argument
66 if (wa->dma_count) in ccp_sg_free()
67 dma_unmap_sg(wa->dma_dev, wa->dma_sg_head, wa->nents, wa->dma_dir); in ccp_sg_free()
69 wa->dma_count = 0; in ccp_sg_free()
72 static int ccp_init_sg_workarea(struct ccp_sg_workarea *wa, struct device *dev, in ccp_init_sg_workarea() argument
76 memset(wa, 0, sizeof(*wa)); in ccp_init_sg_workarea()
78 wa->sg = sg; in ccp_init_sg_workarea()
82 wa->nents = sg_nents_for_len(sg, len); in ccp_init_sg_workarea()
83 if (wa->nents < 0) in ccp_init_sg_workarea()
84 return wa->nents; in ccp_init_sg_workarea()
[all …]
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| /drivers/clocksource/ |
| D | arm_arch_timer.c | 509 bool arch_timer_check_dt_erratum(const struct arch_timer_erratum_workaround *wa, in arch_timer_check_dt_erratum() argument
514 return of_property_read_bool(np, wa->id); in arch_timer_check_dt_erratum()
518 bool arch_timer_check_local_cap_erratum(const struct arch_timer_erratum_workaround *wa, in arch_timer_check_local_cap_erratum() argument
521 return this_cpu_has_cap((uintptr_t)wa->id); in arch_timer_check_local_cap_erratum()
526 bool arch_timer_check_acpi_oem_erratum(const struct arch_timer_erratum_workaround *wa, in arch_timer_check_acpi_oem_erratum() argument
530 const struct ate_acpi_oem_info *info = wa->id; in arch_timer_check_acpi_oem_erratum()
565 void arch_timer_enable_workaround(const struct arch_timer_erratum_workaround *wa, in arch_timer_enable_workaround() argument
571 __this_cpu_write(timer_unstable_counter_workaround, wa); in arch_timer_enable_workaround()
574 per_cpu(timer_unstable_counter_workaround, i) = wa; in arch_timer_enable_workaround()
577 if (wa->read_cntvct_el0 || wa->read_cntpct_el0) in arch_timer_enable_workaround()
[all …]
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| /drivers/staging/media/zoran/ |
| D | zoran_device.c | 233 unsigned int wa, we, ha, he; in zr36057_set_vfe() local
239 wa = tvn->wa; in zr36057_set_vfe()
246 video_width > wa || video_height > ha) { in zr36057_set_vfe()
255 X = DIV_ROUND_UP(vid_win_wid * 64, tvn->wa); in zr36057_set_vfe()
258 hcrop1 = 2 * ((tvn->wa - we) / 4); in zr36057_set_vfe()
259 hcrop2 = tvn->wa - we - hcrop1; in zr36057_set_vfe()
269 h_end = h_start + tvn->wa - 1; in zr36057_set_vfe()
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| D | videocodec.h | 221 u16 wt, wa, h_start, h_sync_start, ht, ha, v_start; member
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| D | zoran.h | 48 #define BUZ_MAX_WIDTH (zr->timing->wa)
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| D | zr36060.c | 572 reg += norm->wa; /* BHend */ in zr36060_set_video()
606 reg += norm->wa + 8; /* SHend */ in zr36060_set_video()
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| /drivers/gpu/drm/i915/gt/uc/ |
| D | intel_guc_ads.c | 249 struct i915_wa *wa; in guc_mmio_regset_init() local
258 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) in guc_mmio_regset_init()
259 GUC_MMIO_REG_ADD(regset, wa->reg, wa->masked_reg); in guc_mmio_regset_init()
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| /drivers/gpu/drm/i915/ |
| D | i915_debugfs.c | 760 const struct i915_wa *wa; in i915_wa_registers() local
770 for (wa = wal->list; count--; wa++) in i915_wa_registers()
772 i915_mmio_reg_offset(wa->reg), in i915_wa_registers()
773 wa->set, wa->clr); in i915_wa_registers()
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| /drivers/net/wireless/broadcom/b43/ |
| D | Makefile | 4 b43-$(CONFIG_B43_PHY_G) += phy_g.o tables.o lo.o wa.o
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_mem_input.c | 756 if (dce_mi->wa.single_head_rdreq_dmif_limit) { in dce_mi_allocate_dmif()
758 dce_mi->wa.single_head_rdreq_dmif_limit; in dce_mi_allocate_dmif()
786 if (dce_mi->wa.single_head_rdreq_dmif_limit) { in dce_mi_free_dmif()
788 dce_mi->wa.single_head_rdreq_dmif_limit; in dce_mi_free_dmif()
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| D | dce_hwseq.c | 80 if (hws->wa.blnd_crtc_trigger) { in dce_pipe_control_lock()
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| D | dce_mem_input.h | 429 struct dce_mem_input_wa wa; member
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| /drivers/gpu/drm/amd/display/dc/ |
| D | dc_ddc_types.h | 156 union ddc_wa wa; member
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | hw_sequencer_private.h | 150 struct dce_hwseq_wa wa; member
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_resource.c | 927 hws->wa.DEGVIDCN10_253 = true; in dcn10_hwseq_create()
928 hws->wa.false_optc_underflow = true; in dcn10_hwseq_create()
929 hws->wa.DEGVIDCN10_254 = true; in dcn10_hwseq_create()
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| D | dcn10_hw_sequencer.c | 717 if (!hws->wa.DEGVIDCN10_253) in apply_DEGVIDCN10_253_wa()
786 if (!dc->hwseq->wa.false_optc_underflow) in false_optc_underflow_wa()
2904 if (dc->hwseq->wa.DEGVIDCN10_254) in dcn10_post_unlock_program_front_end()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_link_ddc.c | 227 ddc_service->wa.raw = 0; in ddc_service_construct()
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| /drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_resource.c | 571 hws->wa.blnd_crtc_trigger = true; in dce110_hwseq_create()
617 dce_mi->wa.single_head_rdreq_dmif_limit = 3; in dce110_mem_input_create()
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| /drivers/gpu/drm/amd/display/dc/dce100/ |
| D | dce100_resource.c | 569 dce_mi->wa.single_head_rdreq_dmif_limit = 2; in dce100_mem_input_create()
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| /drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_resource.c | 1726 hws->wa.DEGVIDCN21 = true; in dcn21_hwseq_create()
1727 hws->wa.disallow_self_refresh_during_multi_plane_transition = true; in dcn21_hwseq_create()
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| /drivers/gpu/drm/amd/display/dc/dce80/ |
| D | dce80_resource.c | 684 dce_mi->wa.single_head_rdreq_dmif_limit = 2; in dce80_mem_input_create()
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| /drivers/gpu/drm/amd/display/dc/dce60/ |
| D | dce60_resource.c | 679 dce_mi->wa.single_head_rdreq_dmif_limit = 2; in dce60_mem_input_create()
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_hwseq.c | 1815 if (hwseq->wa.DEGVIDCN21) in dcn20_post_unlock_program_front_end()
1820 if (hwseq->wa.disallow_self_refresh_during_multi_plane_transition) { in dcn20_post_unlock_program_front_end()
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