| /drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_hubbub.c | 153 struct dcn_watermark_set *watermarks, in hubbub31_program_urgent_watermarks() argument
163 if (safe_to_lower || watermarks->a.urgent_ns > hubbub2->watermarks.a.urgent_ns) { in hubbub31_program_urgent_watermarks()
164 hubbub2->watermarks.a.urgent_ns = watermarks->a.urgent_ns; in hubbub31_program_urgent_watermarks()
165 prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns, in hubbub31_program_urgent_watermarks()
172 watermarks->a.urgent_ns, prog_wm_value); in hubbub31_program_urgent_watermarks()
173 } else if (watermarks->a.urgent_ns < hubbub2->watermarks.a.urgent_ns) in hubbub31_program_urgent_watermarks()
177 if (safe_to_lower || watermarks->a.frac_urg_bw_flip in hubbub31_program_urgent_watermarks()
178 > hubbub2->watermarks.a.frac_urg_bw_flip) { in hubbub31_program_urgent_watermarks()
179 hubbub2->watermarks.a.frac_urg_bw_flip = watermarks->a.frac_urg_bw_flip; in hubbub31_program_urgent_watermarks()
182 DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, watermarks->a.frac_urg_bw_flip); in hubbub31_program_urgent_watermarks()
[all …]
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| D | dcn31_resource.c | 1697 …context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn31_calculate_wm_and_dlg_fp()
1698 …context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter… in dcn31_calculate_wm_and_dlg_fp()
1699 …context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->b… in dcn31_calculate_wm_and_dlg_fp()
1700 …context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter… in dcn31_calculate_wm_and_dlg_fp()
1701 …context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&cont… in dcn31_calculate_wm_and_dlg_fp()
1702 …context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&con… in dcn31_calculate_wm_and_dlg_fp()
1703 …context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, … in dcn31_calculate_wm_and_dlg_fp()
1704 …context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->b… in dcn31_calculate_wm_and_dlg_fp()
1705 …context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&… in dcn31_calculate_wm_and_dlg_fp()
1706 …context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, p… in dcn31_calculate_wm_and_dlg_fp()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_hubbub.c | 149 struct dcn_watermark_set *watermarks, in hubbub21_program_urgent_watermarks() argument
159 if (safe_to_lower || watermarks->a.urgent_ns > hubbub1->watermarks.a.urgent_ns) { in hubbub21_program_urgent_watermarks()
160 hubbub1->watermarks.a.urgent_ns = watermarks->a.urgent_ns; in hubbub21_program_urgent_watermarks()
161 prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns, in hubbub21_program_urgent_watermarks()
169 watermarks->a.urgent_ns, prog_wm_value); in hubbub21_program_urgent_watermarks()
170 } else if (watermarks->a.urgent_ns < hubbub1->watermarks.a.urgent_ns) in hubbub21_program_urgent_watermarks()
174 if (safe_to_lower || watermarks->a.frac_urg_bw_flip in hubbub21_program_urgent_watermarks()
175 > hubbub1->watermarks.a.frac_urg_bw_flip) { in hubbub21_program_urgent_watermarks()
176 hubbub1->watermarks.a.frac_urg_bw_flip = watermarks->a.frac_urg_bw_flip; in hubbub21_program_urgent_watermarks()
179 DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, watermarks->a.frac_urg_bw_flip); in hubbub21_program_urgent_watermarks()
[all …]
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| D | dcn21_hubbub.h | 130 struct dcn_watermark_set *watermarks,
135 struct dcn_watermark_set *watermarks,
140 struct dcn_watermark_set *watermarks,
145 struct dcn_watermark_set *watermarks,
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| D | dcn21_resource.c | 1161 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d, in dcn21_calculate_wm()
1166 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c, in dcn21_calculate_wm()
1171 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b, in dcn21_calculate_wm()
1177 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a, in dcn21_calculate_wm()
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hubbub.c | 247 struct dcn_watermark_set *watermarks, in hubbub1_program_urgent_watermarks() argument
257 if (safe_to_lower || watermarks->a.urgent_ns > hubbub1->watermarks.a.urgent_ns) { in hubbub1_program_urgent_watermarks()
258 hubbub1->watermarks.a.urgent_ns = watermarks->a.urgent_ns; in hubbub1_program_urgent_watermarks()
259 prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns, in hubbub1_program_urgent_watermarks()
266 watermarks->a.urgent_ns, prog_wm_value); in hubbub1_program_urgent_watermarks()
267 } else if (watermarks->a.urgent_ns < hubbub1->watermarks.a.urgent_ns) in hubbub1_program_urgent_watermarks()
270 if (safe_to_lower || watermarks->a.pte_meta_urgent_ns > hubbub1->watermarks.a.pte_meta_urgent_ns) { in hubbub1_program_urgent_watermarks()
271 hubbub1->watermarks.a.pte_meta_urgent_ns = watermarks->a.pte_meta_urgent_ns; in hubbub1_program_urgent_watermarks()
272 prog_wm_value = convert_and_clamp(watermarks->a.pte_meta_urgent_ns, in hubbub1_program_urgent_watermarks()
277 watermarks->a.pte_meta_urgent_ns, prog_wm_value); in hubbub1_program_urgent_watermarks()
[all …]
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| D | dcn10_hubbub.h | 357 struct dcn_watermark_set watermarks; member
371 struct dcn_watermark_set *watermarks,
394 struct dcn_watermark_set *watermarks,
399 struct dcn_watermark_set *watermarks,
404 struct dcn_watermark_set *watermarks,
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| D | dcn10_hw_sequencer.c | 2945 &context->bw_ctx.bw.dcn.watermarks, in dcn10_prepare_bandwidth()
2978 &context->bw_ctx.bw.dcn.watermarks, in dcn10_optimize_bandwidth()
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| /drivers/gpu/drm/amd/display/dc/calcs/ |
| D | dcn_calcs.c | 564 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns =
566 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
568 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns =
570 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
571 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = v->urgent_watermark * 1000;
578 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns =
580 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
582 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns =
584 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
585 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = v->urgent_watermark * 1000;
[all …]
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| D | vg_clk_mgr.h | 30 struct watermarks;
33 struct watermarks *wm_set;
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| D | vg_clk_mgr.c | 398 static void vg_build_watermark_ranges(struct clk_bw_params *bw_params, struct watermarks *table) in vg_build_watermark_ranges()
458 struct watermarks *table = clk_mgr_vgh->smu_wm_set.wm_set; in vg_notify_wm_ranges()
707 static struct watermarks dummy_wms = { 0 };
750 clk_mgr->smu_wm_set.wm_set = (struct watermarks *)dm_helpers_allocate_gpu_mem( in vg_clk_mgr_construct()
753 sizeof(struct watermarks), in vg_clk_mgr_construct()
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| D | dcn301_smu.h | 129 struct watermarks { struct
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_resource.c | 2155 …context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn30_calculate_wm_and_dlg_fp()
2156 …context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter… in dcn30_calculate_wm_and_dlg_fp()
2157 …context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->b… in dcn30_calculate_wm_and_dlg_fp()
2158 …context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&con… in dcn30_calculate_wm_and_dlg_fp()
2159 …context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, … in dcn30_calculate_wm_and_dlg_fp()
2160 …context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->b… in dcn30_calculate_wm_and_dlg_fp()
2161 …context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&… in dcn30_calculate_wm_and_dlg_fp()
2162 …context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, p… in dcn30_calculate_wm_and_dlg_fp()
2209 …context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn30_calculate_wm_and_dlg_fp()
2210 …context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter… in dcn30_calculate_wm_and_dlg_fp()
[all …]
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| D | dcn30_hubbub.c | 98 struct dcn_watermark_set *watermarks, in hubbub3_program_watermarks() argument
105 if (hubbub21_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) in hubbub3_program_watermarks()
108 if (hubbub21_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) in hubbub3_program_watermarks()
111 if (hubbub21_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) in hubbub3_program_watermarks()
379 uint32_t prog_wm_value = convert_and_clamp(hubbub1->watermarks.a.urgent_ns, in hubbub3_force_wm_propagate_to_pipes()
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| D | dcn30_hubbub.h | 127 struct dcn_watermark_set *watermarks,
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_hubbub.c | 573 struct dcn_watermark_set *watermarks, in hubbub2_program_watermarks() argument
583 if (hubbub1_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) in hubbub2_program_watermarks()
586 if (hubbub1_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) in hubbub2_program_watermarks()
598 hubbub1_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower); in hubbub2_program_watermarks()
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| D | dcn20_resource.c | 2996 …context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn20_calculate_wm()
2997 …context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter… in dcn20_calculate_wm()
2998 …context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->b… in dcn20_calculate_wm()
2999 …context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&con… in dcn20_calculate_wm()
3000 …context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, … in dcn20_calculate_wm()
3001 …context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->b… in dcn20_calculate_wm()
3002 …context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&… in dcn20_calculate_wm()
3003 …context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, p… in dcn20_calculate_wm()
3010 …context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn20_calculate_wm()
3011 …context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter… in dcn20_calculate_wm()
[all …]
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| D | dcn20_hubbub.h | 88 struct dcn_watermark_set watermarks; member
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| D | dcn20_hwseq.c | 1848 &context->bw_ctx.bw.dcn.watermarks, in dcn20_prepare_bandwidth()
1864 &context->bw_ctx.bw.dcn.watermarks, in dcn20_optimize_bandwidth()
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| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | dchubbub.h | 150 struct dcn_watermark_set *watermarks,
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | core_types.h | 419 struct dcn_watermark_set watermarks; member
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| /drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | smu_helper.h | 45 struct watermarks { struct
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| D | smu7_hwmgr.c | 5281 struct dm_pp_wm_sets_with_clock_ranges *watermarks = in smu7_set_watermarks_for_clocks_ranges() local
5293 for (k = 0; k < watermarks->num_wm_sets; k++) { in smu7_set_watermarks_for_clocks_ranges()
5294 if (dep_sclk_table->entries[i].clk >= watermarks->wm_clk_ranges[k].wm_min_eng_clk_in_khz / 10 && in smu7_set_watermarks_for_clocks_ranges()
5295 dep_sclk_table->entries[i].clk < watermarks->wm_clk_ranges[k].wm_max_eng_clk_in_khz / 10 && in smu7_set_watermarks_for_clocks_ranges()
5296 dep_mclk_table->entries[i].clk >= watermarks->wm_clk_ranges[k].wm_min_mem_clk_in_khz / 10 && in smu7_set_watermarks_for_clocks_ranges()
5297 dep_mclk_table->entries[i].clk < watermarks->wm_clk_ranges[k].wm_max_mem_clk_in_khz / 10) { in smu7_set_watermarks_for_clocks_ranges()
5299 table->DisplayWatermark[i][j] = watermarks->wm_clk_ranges[k].wm_set_id; in smu7_set_watermarks_for_clocks_ranges()
5305 table->DisplayWatermark[i][j] = watermarks->wm_clk_ranges[k - 1].wm_set_id); in smu7_set_watermarks_for_clocks_ranges()
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| D | smu_helper.c | 728 struct watermarks *table = wt_table; in smu_set_watermarks_for_clocks_ranges()
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| /drivers/gpu/drm/amd/display/dc/dcn301/ |
| D | dcn301_resource.c | 1682 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d, in dcn301_calculate_wm_and_dlg()
1687 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c, in dcn301_calculate_wm_and_dlg()
1692 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b, in dcn301_calculate_wm_and_dlg()
1698 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a, in dcn301_calculate_wm_and_dlg()
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