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Searched refs:ww (Results 1 – 25 of 66) sorted by relevance

123

/drivers/gpu/drm/i915/
Di915_gem_ww.c9 void i915_gem_ww_ctx_init(struct i915_gem_ww_ctx *ww, bool intr) in i915_gem_ww_ctx_init() argument
11 ww_acquire_init(&ww->ctx, &reservation_ww_class); in i915_gem_ww_ctx_init()
12 INIT_LIST_HEAD(&ww->obj_list); in i915_gem_ww_ctx_init()
13 ww->intr = intr; in i915_gem_ww_ctx_init()
14 ww->contended = NULL; in i915_gem_ww_ctx_init()
17 static void i915_gem_ww_ctx_unlock_all(struct i915_gem_ww_ctx *ww) in i915_gem_ww_ctx_unlock_all() argument
21 while ((obj = list_first_entry_or_null(&ww->obj_list, struct drm_i915_gem_object, obj_link))) { in i915_gem_ww_ctx_unlock_all()
35 void i915_gem_ww_ctx_fini(struct i915_gem_ww_ctx *ww) in i915_gem_ww_ctx_fini() argument
37 i915_gem_ww_ctx_unlock_all(ww); in i915_gem_ww_ctx_fini()
38 WARN_ON(ww->contended); in i915_gem_ww_ctx_fini()
[all …]
Di915_gem_ww.h24 static inline int __i915_gem_ww_fini(struct i915_gem_ww_ctx *ww, int err) in __i915_gem_ww_fini() argument
26 ww->loop = 0; in __i915_gem_ww_fini()
28 err = i915_gem_ww_ctx_backoff(ww); in __i915_gem_ww_fini()
30 ww->loop = 1; in __i915_gem_ww_fini()
33 if (!ww->loop) in __i915_gem_ww_fini()
34 i915_gem_ww_ctx_fini(ww); in __i915_gem_ww_fini()
40 __i915_gem_ww_init(struct i915_gem_ww_ctx *ww, bool intr) in __i915_gem_ww_init() argument
42 i915_gem_ww_ctx_init(ww, intr); in __i915_gem_ww_init()
43 ww->loop = 1; in __i915_gem_ww_init()
Di915_vma.h243 i915_vma_pin_ww(struct i915_vma *vma, struct i915_gem_ww_ctx *ww,
249 struct i915_gem_ww_ctx ww; in i915_vma_pin() local
252 i915_gem_ww_ctx_init(&ww, true); in i915_vma_pin()
254 err = i915_gem_object_lock(vma->obj, &ww); in i915_vma_pin()
256 err = i915_vma_pin_ww(vma, &ww, size, alignment, flags); in i915_vma_pin()
258 err = i915_gem_ww_ctx_backoff(&ww); in i915_vma_pin()
262 i915_gem_ww_ctx_fini(&ww); in i915_vma_pin()
267 int i915_ggtt_pin(struct i915_vma *vma, struct i915_gem_ww_ctx *ww,
Di915_gem.c294 struct i915_gem_ww_ctx ww; in i915_gem_gtt_prepare() local
297 i915_gem_ww_ctx_init(&ww, true); in i915_gem_gtt_prepare()
300 ret = i915_gem_object_lock(obj, &ww); in i915_gem_gtt_prepare()
309 vma = i915_gem_object_ggtt_pin_ww(obj, &ww, NULL, 0, 0, in i915_gem_gtt_prepare()
339 ret = i915_gem_ww_ctx_backoff(&ww); in i915_gem_gtt_prepare()
343 i915_gem_ww_ctx_fini(&ww); in i915_gem_gtt_prepare()
871 struct i915_gem_ww_ctx *ww, in i915_gem_object_ggtt_pin_ww() argument
939 if (ww) in i915_gem_object_ggtt_pin_ww()
940 ret = i915_vma_pin_ww(vma, ww, size, alignment, flags | PIN_GLOBAL); in i915_gem_object_ggtt_pin_ww()
/drivers/staging/vt6655/
Dmac.c253 unsigned short ww; in MACbSoftwareReset() local
258 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { in MACbSoftwareReset()
262 if (ww == W_MAX_TIMEOUT) in MACbSoftwareReset()
316 unsigned short ww; in MACbSafeRxOff() local
323 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { in MACbSafeRxOff()
327 if (ww == W_MAX_TIMEOUT) { in MACbSafeRxOff()
331 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { in MACbSafeRxOff()
335 if (ww == W_MAX_TIMEOUT) { in MACbSafeRxOff()
343 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { in MACbSafeRxOff()
347 if (ww == W_MAX_TIMEOUT) { in MACbSafeRxOff()
[all …]
Dbaseband.c1909 unsigned short ww; in bb_read_embedded() local
1918 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { in bb_read_embedded()
1927 if (ww == W_MAX_TIMEOUT) { in bb_read_embedded()
1952 unsigned short ww; in bb_write_embedded() local
1963 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { in bb_write_embedded()
1969 if (ww == W_MAX_TIMEOUT) { in bb_write_embedded()
/drivers/gpu/drm/i915/gt/
Dintel_context.c101 static int __context_pin_state(struct i915_vma *vma, struct i915_gem_ww_ctx *ww) in __context_pin_state() argument
106 err = i915_ggtt_pin(vma, ww, 0, bias | PIN_HIGH); in __context_pin_state()
136 struct i915_gem_ww_ctx *ww) in __ring_active() argument
140 err = intel_ring_pin(ring, ww); in __ring_active()
162 struct i915_gem_ww_ctx *ww) in intel_context_pre_pin() argument
168 err = __ring_active(ce->ring, ww); in intel_context_pre_pin()
172 err = intel_timeline_pin(ce->timeline, ww); in intel_context_pre_pin()
179 err = __context_pin_state(ce->state, ww); in intel_context_pre_pin()
203 struct i915_gem_ww_ctx *ww) in __intel_context_do_pin_ww() argument
221 err = i915_gem_object_lock(ce->timeline->hwsp_ggtt->obj, ww); in __intel_context_do_pin_ww()
[all …]
Dselftest_migrate.c34 struct i915_gem_ww_ctx *ww, in copy() argument
43 struct i915_gem_ww_ctx ww; in copy() local
56 for_i915_gem_ww(&ww, err, true) { in copy()
57 err = i915_gem_object_lock(src, &ww); in copy()
61 err = i915_gem_object_lock(dst, &ww); in copy()
85 err = fn(migrate, &ww, src, dst, &rq); in copy()
134 struct i915_gem_ww_ctx *ww, in clear() argument
143 struct i915_gem_ww_ctx ww; in clear() local
152 for_i915_gem_ww(&ww, err, true) { in clear()
153 err = i915_gem_object_lock(obj, &ww); in clear()
[all …]
Dintel_renderstate.c165 i915_gem_ww_ctx_init(&so->ww, true); in intel_renderstate_init()
167 err = intel_context_pin_ww(ce, &so->ww); in intel_renderstate_init()
175 err = i915_gem_object_lock(so->vma->obj, &so->ww); in intel_renderstate_init()
179 err = i915_vma_pin_ww(so->vma, &so->ww, 0, 0, PIN_GLOBAL | PIN_HIGH); in intel_renderstate_init()
195 err = i915_gem_ww_ctx_backoff(&so->ww); in intel_renderstate_init()
199 i915_gem_ww_ctx_fini(&so->ww); in intel_renderstate_init()
248 i915_gem_ww_ctx_fini(&so->ww); in intel_renderstate_fini()
Dintel_ring_submission.c458 struct i915_gem_ww_ctx *ww) in ring_context_init_default_state() argument
478 struct i915_gem_ww_ctx *ww, in ring_context_pre_pin() argument
486 err = ring_context_init_default_state(ce, ww); in ring_context_pre_pin()
493 err = gen6_ppgtt_pin(i915_vm_to_ppgtt((vm)), ww); in ring_context_pre_pin()
1239 struct i915_gem_ww_ctx *ww, in gen7_ctx_switch_bb_init() argument
1244 err = i915_vma_pin_ww(vma, ww, 0, 0, PIN_USER | PIN_HIGH); in gen7_ctx_switch_bb_init()
1304 struct i915_gem_ww_ctx ww; in intel_ring_submission_setup() local
1354 i915_gem_ww_ctx_init(&ww, false); in intel_ring_submission_setup()
1357 err = i915_gem_object_lock(timeline->hwsp_ggtt->obj, &ww); in intel_ring_submission_setup()
1359 err = i915_gem_object_lock(gen7_wa_vma->obj, &ww); in intel_ring_submission_setup()
[all …]
Dintel_migrate.h25 struct i915_gem_ww_ctx *ww,
47 struct i915_gem_ww_ctx *ww,
Dintel_migrate.c97 struct i915_gem_ww_ctx ww; in migrate_vm() local
121 for_i915_gem_ww(&ww, err, true) { in migrate_vm()
122 err = i915_vm_lock_objects(&vm->vm, &ww); in migrate_vm()
601 struct i915_gem_ww_ctx *ww, in intel_migrate_copy() argument
623 err = intel_context_pin_ww(ce, ww); in intel_migrate_copy()
640 struct i915_gem_ww_ctx *ww, in intel_migrate_clear() argument
660 err = intel_context_pin_ww(ce, ww); in intel_migrate_clear()
/drivers/gpu/drm/i915/gem/selftests/
Di915_gem_migrate.c45 struct i915_gem_ww_ctx ww; in igt_create_migrate() local
55 for_i915_gem_ww(&ww, err, true) { in igt_create_migrate()
56 err = i915_gem_object_lock(obj, &ww); in igt_create_migrate()
64 err = i915_gem_object_migrate(obj, &ww, dst); in igt_create_migrate()
102 static int lmem_pages_migrate_one(struct i915_gem_ww_ctx *ww, in lmem_pages_migrate_one() argument
107 err = i915_gem_object_lock(obj, ww); in lmem_pages_migrate_one()
112 err = i915_gem_object_migrate(obj, ww, INTEL_REGION_SMEM); in lmem_pages_migrate_one()
130 err = i915_gem_object_migrate(obj, ww, INTEL_REGION_LMEM); in lmem_pages_migrate_one()
156 struct i915_gem_ww_ctx ww; in igt_lmem_pages_migrate() local
168 for_i915_gem_ww(&ww, err, true) { in igt_lmem_pages_migrate()
[all …]
Di915_gem_execbuffer.c35 err = i915_gem_object_lock(obj, &eb->ww); in __igt_gpu_reloc()
39 err = i915_vma_pin_ww(vma, &eb->ww, 0, 0, PIN_USER | PIN_HIGH); in __igt_gpu_reloc()
144 i915_gem_ww_ctx_init(&eb.ww, false); in igt_gpu_reloc()
146 err = intel_context_pin_ww(eb.context, &eb.ww); in igt_gpu_reloc()
153 err = i915_gem_ww_ctx_backoff(&eb.ww); in igt_gpu_reloc()
157 i915_gem_ww_ctx_fini(&eb.ww); in igt_gpu_reloc()
Di915_gem_mman.c532 struct i915_gem_ww_ctx ww; in make_obj_busy() local
539 i915_gem_ww_ctx_init(&ww, false); in make_obj_busy()
541 err = i915_gem_object_lock(obj, &ww); in make_obj_busy()
543 err = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_USER); in make_obj_busy()
563 err = i915_gem_ww_ctx_backoff(&ww); in make_obj_busy()
567 i915_gem_ww_ctx_fini(&ww); in make_obj_busy()
1171 struct i915_gem_ww_ctx ww; in __igt_mmap_gpu() local
1179 i915_gem_ww_ctx_init(&ww, false); in __igt_mmap_gpu()
1181 err = i915_gem_object_lock(obj, &ww); in __igt_mmap_gpu()
1183 err = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_USER); in __igt_mmap_gpu()
[all …]
/drivers/gpu/drm/i915/gem/
Di915_gem_dmabuf.c118 struct i915_gem_ww_ctx ww; in i915_gem_begin_cpu_access() local
121 i915_gem_ww_ctx_init(&ww, true); in i915_gem_begin_cpu_access()
123 err = i915_gem_object_lock(obj, &ww); in i915_gem_begin_cpu_access()
131 err = i915_gem_ww_ctx_backoff(&ww); in i915_gem_begin_cpu_access()
135 i915_gem_ww_ctx_fini(&ww); in i915_gem_begin_cpu_access()
142 struct i915_gem_ww_ctx ww; in i915_gem_end_cpu_access() local
145 i915_gem_ww_ctx_init(&ww, true); in i915_gem_end_cpu_access()
147 err = i915_gem_object_lock(obj, &ww); in i915_gem_end_cpu_access()
155 err = i915_gem_ww_ctx_backoff(&ww); in i915_gem_end_cpu_access()
159 i915_gem_ww_ctx_fini(&ww); in i915_gem_end_cpu_access()
[all …]
Di915_gem_object.h173 struct i915_gem_ww_ctx *ww, in __i915_gem_object_lock() argument
179 ret = dma_resv_lock_interruptible(obj->base.resv, ww ? &ww->ctx : NULL); in __i915_gem_object_lock()
181 ret = dma_resv_lock(obj->base.resv, ww ? &ww->ctx : NULL); in __i915_gem_object_lock()
183 if (!ret && ww) { in __i915_gem_object_lock()
185 list_add_tail(&obj->obj_link, &ww->obj_list); in __i915_gem_object_lock()
192 ww->contended = obj; in __i915_gem_object_lock()
199 struct i915_gem_ww_ctx *ww) in i915_gem_object_lock() argument
201 return __i915_gem_object_lock(obj, ww, ww && ww->intr); in i915_gem_object_lock()
205 struct i915_gem_ww_ctx *ww) in i915_gem_object_lock_interruptible() argument
207 WARN_ON(ww && !ww->intr); in i915_gem_object_lock_interruptible()
[all …]
Di915_gem_mman.c300 struct i915_gem_ww_ctx ww; in vm_fault_gtt() local
314 i915_gem_ww_ctx_init(&ww, true); in vm_fault_gtt()
316 ret = i915_gem_object_lock(obj, &ww); in vm_fault_gtt()
335 vma = i915_gem_object_ggtt_pin_ww(obj, &ww, NULL, 0, 0, in vm_fault_gtt()
354 vma = i915_gem_object_ggtt_pin_ww(obj, &ww, &view, 0, 0, flags); in vm_fault_gtt()
358 vma = i915_gem_object_ggtt_pin_ww(obj, &ww, &view, 0, 0, flags); in vm_fault_gtt()
419 ret = i915_gem_ww_ctx_backoff(&ww); in vm_fault_gtt()
423 i915_gem_ww_ctx_fini(&ww); in vm_fault_gtt()
434 struct i915_gem_ww_ctx ww; in vm_access() local
445 i915_gem_ww_ctx_init(&ww, true); in vm_access()
[all …]
Di915_gem_shrinker.c101 i915_gem_shrink(struct i915_gem_ww_ctx *ww, in i915_gem_shrink() argument
124 bool trylock_vm = !ww && intel_vm_no_concurrent_access_wa(i915); in i915_gem_shrink()
215 if (!ww) { in i915_gem_shrink()
219 err = i915_gem_object_lock(obj, ww); in i915_gem_shrink()
228 if (!ww) in i915_gem_shrink()
/drivers/gpu/drm/i915/selftests/
Di915_gem.c207 struct i915_gem_ww_ctx ww; in igt_gem_ww_ctx() local
220 i915_gem_ww_ctx_init(&ww, true); in igt_gem_ww_ctx()
223 err = i915_gem_object_lock(obj, &ww); in igt_gem_ww_ctx()
225 err = i915_gem_object_lock_interruptible(obj, &ww); in igt_gem_ww_ctx()
227 err = i915_gem_object_lock_interruptible(obj2, &ww); in igt_gem_ww_ctx()
229 err = i915_gem_object_lock(obj2, &ww); in igt_gem_ww_ctx()
232 err = i915_gem_ww_ctx_backoff(&ww); in igt_gem_ww_ctx()
236 i915_gem_ww_ctx_fini(&ww); in igt_gem_ww_ctx()
Digt_spinner.c42 struct i915_gem_ww_ctx *ww, in igt_spinner_pin_obj() argument
53 ret = i915_gem_object_lock(obj, ww); in igt_spinner_pin_obj()
59 if (!ww) in igt_spinner_pin_obj()
65 if (ww) in igt_spinner_pin_obj()
66 ret = i915_vma_pin_ww(*vma, ww, 0, 0, PIN_USER); in igt_spinner_pin_obj()
80 struct i915_gem_ww_ctx *ww) in igt_spinner_pin() argument
89 vaddr = igt_spinner_pin_obj(ce, ww, spin->hws, I915_MAP_WB, &spin->hws_vma); in igt_spinner_pin()
100 vaddr = igt_spinner_pin_obj(ce, ww, spin->obj, mode, &spin->batch_vma); in igt_spinner_pin()
/drivers/scsi/aic94xx/
Daic94xx_reg.c108 #define ASD_READ_SW(ww, type, ord) \ argument
109 static type asd_read_##ww##_##ord(struct asd_ha_struct *asd_ha, \
113 u32 map_offs = (reg - io_handle->ww##_base) + asd_mem_offs_##ww();\
117 #define ASD_WRITE_SW(ww, type, ord) \ argument
118 static void asd_write_##ww##_##ord(struct asd_ha_struct *asd_ha, \
122 u32 map_offs = (reg - io_handle->ww##_base) + asd_mem_offs_##ww();\
/drivers/i2c/busses/
Di2c-sis96x.c245 u16 ww = 0; in sis96x_probe() local
253 pci_read_config_word(dev, PCI_CLASS_DEVICE, &ww); in sis96x_probe()
254 if (PCI_CLASS_SERIAL_SMBUS != ww) { in sis96x_probe()
255 dev_err(&dev->dev, "Unsupported device class 0x%04x!\n", ww); in sis96x_probe()
/drivers/video/fbdev/
Dcg3.c265 int ww, hh; in cg3_rdi_maybe_fixup_var() local
269 ww = simple_strtoul(params, &p, 10); in cg3_rdi_maybe_fixup_var()
270 if (ww && *p == 'x') { in cg3_rdi_maybe_fixup_var()
273 if (var->xres != ww || in cg3_rdi_maybe_fixup_var()
275 var->xres = var->xres_virtual = ww; in cg3_rdi_maybe_fixup_var()
/drivers/md/
Ddm-bow.c953 struct write_work *ww = container_of(work, struct write_work, work); in bow_write() local
954 struct bow_context *bc = ww->bc; in bow_write()
955 struct bio *bio = ww->bio; in bow_write()
959 kfree(ww); in bow_write()
984 struct write_work *ww = kmalloc(sizeof(*ww), GFP_NOIO | __GFP_NORETRY in queue_write() local
986 if (!ww) { in queue_write()
991 INIT_WORK(&ww->work, bow_write); in queue_write()
992 ww->bc = bc; in queue_write()
993 ww->bio = bio; in queue_write()
994 queue_work(bc->workqueue, &ww->work); in queue_write()

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