| /drivers/gpu/drm/radeon/ |
| D | rs600d.h | 33 #define S_000040_SCRATCH_INT_MASK(x) (((x) & 0x1) << 18) argument
34 #define G_000040_SCRATCH_INT_MASK(x) (((x) >> 18) & 0x1) argument
36 #define S_000040_GUI_IDLE_MASK(x) (((x) & 0x1) << 19) argument
37 #define G_000040_GUI_IDLE_MASK(x) (((x) >> 19) & 0x1) argument
39 #define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13) argument
40 #define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1) argument
42 #define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14) argument
43 #define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1) argument
45 #define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15) argument
46 #define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1) argument
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| D | r100d.h | 69 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) argument
70 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) argument
72 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) argument
73 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) argument
75 #define S_0000F0_SOFT_RESET_SE(x) (((x) & 0x1) << 2) argument
76 #define G_0000F0_SOFT_RESET_SE(x) (((x) >> 2) & 0x1) argument
78 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) argument
79 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) argument
81 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) argument
82 #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) argument
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| D | rv515d.h | 210 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) argument
211 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) argument
213 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) argument
214 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) argument
216 #define S_0000F0_SOFT_RESET_VAP(x) (((x) & 0x1) << 2) argument
217 #define G_0000F0_SOFT_RESET_VAP(x) (((x) >> 2) & 0x1) argument
219 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) argument
220 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) argument
222 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) argument
223 #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) argument
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| D | rs690d.h | 34 #define G_00005F_K8_ADDR_EXT(x) (((x) >> 0) & 0xFF) argument
36 #define S_000078_MC_IND_ADDR(x) (((x) & 0x1FF) << 0) argument
37 #define G_000078_MC_IND_ADDR(x) (((x) >> 0) & 0x1FF) argument
39 #define S_000078_MC_IND_WR_EN(x) (((x) & 0x1) << 9) argument
40 #define G_000078_MC_IND_WR_EN(x) (((x) >> 9) & 0x1) argument
43 #define S_00007C_MC_DATA(x) (((x) & 0xFFFFFFFF) << 0) argument
44 #define G_00007C_MC_DATA(x) (((x) >> 0) & 0xFFFFFFFF) argument
47 #define S_0000F8_CONFIG_MEMSIZE(x) (((x) & 0xFFFFFFFF) << 0) argument
48 #define G_0000F8_CONFIG_MEMSIZE(x) (((x) >> 0) & 0xFFFFFFFF) argument
51 #define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0) argument
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| D | r300d.h | 70 #define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0) argument
71 #define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF) argument
73 #define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) argument
74 #define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) argument
77 #define S_00014C_MC_AGP_START(x) (((x) & 0xFFFF) << 0) argument
78 #define G_00014C_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) argument
80 #define S_00014C_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) argument
81 #define G_00014C_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) argument
84 #define S_00015C_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0) argument
85 #define G_00015C_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF) argument
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| D | r420d.h | 32 #define S_0001F8_MC_IND_ADDR(x) (((x) & 0x7F) << 0) argument
33 #define G_0001F8_MC_IND_ADDR(x) (((x) >> 0) & 0x7F) argument
35 #define S_0001F8_MC_IND_WR_EN(x) (((x) & 0x1) << 8) argument
36 #define G_0001F8_MC_IND_WR_EN(x) (((x) >> 8) & 0x1) argument
39 #define S_0001FC_MC_IND_DATA(x) (((x) & 0xFFFFFFFF) << 0) argument
40 #define G_0001FC_MC_IND_DATA(x) (((x) >> 0) & 0xFFFFFFFF) argument
43 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
44 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
46 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument
47 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument
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| D | r600d.h | 60 #define BACKEND_DISABLE(x) ((x) << 16) argument
63 #define S_028808_SPECIAL_OP(x) (((x) & 0x7) << 4) argument
64 #define G_028808_SPECIAL_OP(x) (((x) >> 4) & 0x7) argument
83 #define S_028080_SLICE_START(x) (((x) & 0x7FF) << 0) argument
84 #define G_028080_SLICE_START(x) (((x) >> 0) & 0x7FF) argument
86 #define S_028080_SLICE_MAX(x) (((x) & 0x7FF) << 13) argument
87 #define G_028080_SLICE_MAX(x) (((x) >> 13) & 0x7FF) argument
97 #define S_028100_CMASK_BLOCK_MAX(x) (((x) & 0xFFF) << 0) argument
98 #define G_028100_CMASK_BLOCK_MAX(x) (((x) >> 0) & 0xFFF) argument
100 #define S_028100_FMASK_TILE_MAX(x) (((x) & 0xFFFFF) << 12) argument
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| D | r520d.h | 33 #define S_0000F8_CONFIG_MEMSIZE(x) (((x) & 0xFFFFFFFF) << 0) argument
34 #define G_0000F8_CONFIG_MEMSIZE(x) (((x) >> 0) & 0xFFFFFFFF) argument
37 #define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0) argument
38 #define G_000134_HDP_FB_START(x) (((x) >> 0) & 0xFFFF) argument
41 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
42 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
44 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument
45 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument
47 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) argument
48 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) argument
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| D | evergreend.h | 53 #define HOST_SMC_MSG(x) ((x) << 0) argument
56 #define HOST_SMC_RESP(x) ((x) << 8) argument
59 #define SMC_HOST_MSG(x) ((x) << 16) argument
62 #define SMC_HOST_RESP(x) ((x) << 24) argument
67 #define DCCG_DISP1_SLOW_SELECT(x) ((x) << 0) argument
70 #define DCCG_DISP2_SLOW_SELECT(x) ((x) << 4) argument
78 #define SPLL_REF_DIV(x) ((x) << 4) argument
80 #define SPLL_PDIV_A(x) ((x) << 20) argument
83 #define SCLK_MUX_SEL(x) ((x) << 0) argument
87 #define SPLL_FB_DIV(x) ((x) << 0) argument
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| D | rs400d.h | 33 #define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0) argument
34 #define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF) argument
36 #define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) argument
37 #define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) argument
40 #define S_00015C_MC_FB_START(x) (((x) & 0xFFFF) << 0) argument
41 #define G_00015C_MC_FB_START(x) (((x) >> 0) & 0xFFFF) argument
43 #define S_00015C_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) argument
44 #define G_00015C_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) argument
47 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
48 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
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| D | rv770d.h | 47 # define UPLL_REF_DIV(x) ((x) << 16) argument
52 # define UPLL_SW_HILEN(x) ((x) << 0) argument
53 # define UPLL_SW_LOLEN(x) ((x) << 4) argument
54 # define UPLL_SW_HILEN2(x) ((x) << 8) argument
55 # define UPLL_SW_LOLEN2(x) ((x) << 12) argument
57 # define VCLK_SRC_SEL(x) ((x) << 20) argument
59 # define DCLK_SRC_SEL(x) ((x) << 25) argument
62 # define UPLL_FB_DIV(x) ((x) << 0) argument
74 #define HOST_SMC_MSG(x) ((x) << 0) argument
77 #define HOST_SMC_RESP(x) ((x) << 8) argument
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| D | rv250d.h | 32 #define S_00000D_SCLK_SRC_SEL(x) (((x) & 0x7) << 0) argument
33 #define G_00000D_SCLK_SRC_SEL(x) (((x) >> 0) & 0x7) argument
35 #define S_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 3) argument
36 #define G_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) >> 3) & 0x1) argument
38 #define S_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 4) argument
39 #define G_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) >> 4) & 0x1) argument
41 #define S_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 5) argument
42 #define G_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) >> 5) & 0x1) argument
44 #define S_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 6) argument
45 #define G_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) >> 6) & 0x1) argument
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| /drivers/staging/media/hantro/ |
| D | rockchip_vpu2_regs.h | 14 #define VEPU_REG_VP8_QUT_DC_Y2(x) (((x) & 0x3fff) << 16) argument
15 #define VEPU_REG_VP8_QUT_DC_Y1(x) (((x) & 0x3fff) << 0) argument
17 #define VEPU_REG_VP8_QUT_AC_Y1(x) (((x) & 0x3fff) << 16) argument
18 #define VEPU_REG_VP8_QUT_DC_CHR(x) (((x) & 0x3fff) << 0) argument
20 #define VEPU_REG_VP8_QUT_AC_CHR(x) (((x) & 0x3fff) << 16) argument
21 #define VEPU_REG_VP8_QUT_AC_Y2(x) (((x) & 0x3fff) << 0) argument
23 #define VEPU_REG_VP8_QUT_ZB_DC_CHR(x) (((x) & 0x1ff) << 18) argument
24 #define VEPU_REG_VP8_QUT_ZB_DC_Y2(x) (((x) & 0x1ff) << 9) argument
25 #define VEPU_REG_VP8_QUT_ZB_DC_Y1(x) (((x) & 0x1ff) << 0) argument
27 #define VEPU_REG_VP8_QUT_ZB_AC_CHR(x) (((x) & 0x1ff) << 18) argument
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| D | hantro_g1_regs.h | 28 #define G1_REG_CONFIG_DEC_AXI_RD_ID(x) (((x) & 0xff) << 24) argument
37 #define G1_REG_CONFIG_DEC_LATENCY(x) (((x) & 0x3f) << 11) argument
41 #define G1_REG_CONFIG_PRIORITY_MODE(x) (((x) & 0x7) << 5) argument
45 #define G1_REG_CONFIG_DEC_MAX_BURST(x) (((x) & 0x1f) << 0) argument
47 #define G1_REG_DEC_CTRL0_DEC_MODE(x) (((x) & 0xf) << 28) argument
70 #define G1_REG_DEC_CTRL0_DEC_AXI_WR_ID(x) (((x) & 0xff) << 0) argument
72 #define G1_REG_DEC_CTRL1_PIC_MB_WIDTH(x) (((x) & 0x1ff) << 23) argument
73 #define G1_REG_DEC_CTRL1_MB_WIDTH_OFF(x) (((x) & 0xf) << 19) argument
74 #define G1_REG_DEC_CTRL1_PIC_MB_HEIGHT_P(x) (((x) & 0xff) << 11) argument
75 #define G1_REG_DEC_CTRL1_MB_HEIGHT_OFF(x) (((x) & 0xf) << 7) argument
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| /drivers/net/ethernet/chelsio/cxgb/ |
| D | regs.h | 45 #define V_CMDQ0_ENABLE(x) ((x) << S_CMDQ0_ENABLE) argument
49 #define V_CMDQ1_ENABLE(x) ((x) << S_CMDQ1_ENABLE) argument
53 #define V_FL0_ENABLE(x) ((x) << S_FL0_ENABLE) argument
57 #define V_FL1_ENABLE(x) ((x) << S_FL1_ENABLE) argument
61 #define V_CPL_ENABLE(x) ((x) << S_CPL_ENABLE) argument
65 #define V_RESPONSE_QUEUE_ENABLE(x) ((x) << S_RESPONSE_QUEUE_ENABLE) argument
70 #define V_CMDQ_PRIORITY(x) ((x) << S_CMDQ_PRIORITY) argument
71 #define G_CMDQ_PRIORITY(x) (((x) >> S_CMDQ_PRIORITY) & M_CMDQ_PRIORITY) argument
74 #define V_DISABLE_CMDQ0_GTS(x) ((x) << S_DISABLE_CMDQ0_GTS) argument
78 #define V_DISABLE_CMDQ1_GTS(x) ((x) << S_DISABLE_CMDQ1_GTS) argument
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| /drivers/phy/microchip/ |
| D | sparx5_serdes_regs.h | 35 #define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\ argument
36 FIELD_PREP(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, x)
37 #define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_GET(x)\ argument
38 FIELD_GET(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, x)
41 #define SD10G_LANE_LANE_01_CFG_RXDET_EN_SET(x)\ argument
42 FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_EN, x)
43 #define SD10G_LANE_LANE_01_CFG_RXDET_EN_GET(x)\ argument
44 FIELD_GET(SD10G_LANE_LANE_01_CFG_RXDET_EN, x)
47 #define SD10G_LANE_LANE_01_CFG_RXDET_STR_SET(x)\ argument
48 FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_STR, x)
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| /drivers/net/ethernet/microchip/sparx5/ |
| D | sparx5_main_regs.h | 60 #define ANA_AC_RAM_INIT_RAM_INIT_SET(x)\ argument
61 FIELD_PREP(ANA_AC_RAM_INIT_RAM_INIT, x)
62 #define ANA_AC_RAM_INIT_RAM_INIT_GET(x)\ argument
63 FIELD_GET(ANA_AC_RAM_INIT_RAM_INIT, x)
66 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_SET(x)\ argument
67 FIELD_PREP(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x)
68 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_GET(x)\ argument
69 FIELD_GET(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x)
75 #define ANA_AC_OWN_UPSID_OWN_UPSID_SET(x)\ argument
76 FIELD_PREP(ANA_AC_OWN_UPSID_OWN_UPSID, x)
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| /drivers/net/ethernet/chelsio/cxgb3/ |
| D | regs.h | 5 #define V_CONGMODE(x) ((x) << S_CONGMODE) argument
9 #define V_TNLFLMODE(x) ((x) << S_TNLFLMODE) argument
13 #define V_FATLPERREN(x) ((x) << S_FATLPERREN) argument
17 #define V_DROPPKT(x) ((x) << S_DROPPKT) argument
21 #define V_EGRGENCTRL(x) ((x) << S_EGRGENCTRL) argument
26 #define V_USERSPACESIZE(x) ((x) << S_USERSPACESIZE) argument
30 #define V_HOSTPAGESIZE(x) ((x) << S_HOSTPAGESIZE) argument
33 #define V_FLMODE(x) ((x) << S_FLMODE) argument
38 #define V_PKTSHIFT(x) ((x) << S_PKTSHIFT) argument
41 #define V_ONEINTMULTQ(x) ((x) << S_ONEINTMULTQ) argument
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| D | sge_defs.h | 11 #define V_EC_CREDITS(x) ((x) << S_EC_CREDITS) argument
12 #define G_EC_CREDITS(x) (((x) >> S_EC_CREDITS) & M_EC_CREDITS) argument
15 #define V_EC_GTS(x) ((x) << S_EC_GTS) argument
20 #define V_EC_INDEX(x) ((x) << S_EC_INDEX) argument
21 #define G_EC_INDEX(x) (((x) >> S_EC_INDEX) & M_EC_INDEX) argument
25 #define V_EC_SIZE(x) ((x) << S_EC_SIZE) argument
26 #define G_EC_SIZE(x) (((x) >> S_EC_SIZE) & M_EC_SIZE) argument
30 #define V_EC_BASE_LO(x) ((x) << S_EC_BASE_LO) argument
31 #define G_EC_BASE_LO(x) (((x) >> S_EC_BASE_LO) & M_EC_BASE_LO) argument
35 #define V_EC_BASE_HI(x) ((x) << S_EC_BASE_HI) argument
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| /drivers/net/ethernet/chelsio/cxgb4/ |
| D | t4_regs.h | 77 #define QID_V(x) ((x) << QID_S) argument
80 #define DBPRIO_V(x) ((x) << DBPRIO_S) argument
84 #define PIDX_V(x) ((x) << PIDX_S) argument
89 #define DBTYPE_V(x) ((x) << DBTYPE_S) argument
94 #define PIDX_T5_V(x) ((x) << PIDX_T5_S) argument
95 #define PIDX_T5_G(x) (((x) >> PIDX_T5_S) & PIDX_T5_M) argument
100 #define INGRESSQID_V(x) ((x) << INGRESSQID_S) argument
103 #define TIMERREG_V(x) ((x) << TIMERREG_S) argument
106 #define SEINTARM_V(x) ((x) << SEINTARM_S) argument
110 #define CIDXINC_V(x) ((x) << CIDXINC_S) argument
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| D | t4_msg.h | 196 #define CPL_OPCODE_V(x) ((x) << CPL_OPCODE_S) argument
197 #define CPL_OPCODE_G(x) (((x) >> CPL_OPCODE_S) & 0xFF) argument
198 #define TID_G(x) ((x) & 0xFFFFFF) argument
211 #define TID_TID_V(x) ((x) << TID_TID_S) argument
212 #define TID_TID_G(x) (((x) >> TID_TID_S) & TID_TID_M) argument
216 #define TID_QID_V(x) ((x) << TID_QID_S) argument
217 #define TID_QID_G(x) (((x) >> TID_QID_S) & TID_QID_M) argument
248 #define WR_OP_V(x) ((__u64)(x) << WR_OP_S) argument
254 #define TX_CHAN_V(x) ((x) << TX_CHAN_S) argument
257 #define ULP_MODE_V(x) ((x) << ULP_MODE_S) argument
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | navi10_sdma_pkt_open.h | 77 #define SDMA_GCR_SEQ(x) (((x) & 0x3) << 16) argument
81 #define SDMA_GCR_GL2_RANGE(x) (((x) & 0x3) << 11) argument
89 #define SDMA_GCR_GL1_RANGE(x) (((x) & 0x3) << 2) argument
90 #define SDMA_GCR_GLI_INV(x) (((x) & 0x3) << 0) argument
96 #define SDMA_PKT_HEADER_OP(x) (((x) & SDMA_PKT_HEADER_op_mask) << SDMA_PKT_HEADER_op_shift) argument
102 #define SDMA_PKT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_HEADER_sub_op_mask) << SDMA_PKT_HEADER_sub_op_sh… argument
113 #define SDMA_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_PKT_… argument
119 #define SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask) << S… argument
125 #define SDMA_PKT_COPY_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask) <<… argument
131 #define SDMA_PKT_COPY_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask) << SDMA_PK… argument
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| D | tonga_sdma_pkt_open.h | 57 #define SDMA_PKT_HEADER_OP(x) (((x) & SDMA_PKT_HEADER_op_mask) << SDMA_PKT_HEADER_op_shift) argument
63 #define SDMA_PKT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_HEADER_sub_op_mask) << SDMA_PKT_HEADER_sub_op_sh… argument
74 #define SDMA_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_PKT_… argument
80 #define SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask) << S… argument
86 #define SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask… argument
93 #define SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_… argument
100 #define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask… argument
106 #define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_mask… argument
112 #define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask… argument
118 #define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_mask… argument
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| D | vega10_sdma_pkt_open.h | 72 #define SDMA_PKT_HEADER_OP(x) (((x) & SDMA_PKT_HEADER_op_mask) << SDMA_PKT_HEADER_op_shift) argument
78 #define SDMA_PKT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_HEADER_sub_op_mask) << SDMA_PKT_HEADER_sub_op_sh… argument
90 #define SDMA_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_PKT_… argument
96 #define SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask) << S… argument
102 #define SDMA_PKT_COPY_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask) <<… argument
108 #define SDMA_PKT_COPY_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask) << SDMA_PK… argument
114 #define SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask… argument
121 #define SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_… argument
128 #define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask… argument
134 #define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask… argument
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| D | iceland_sdma_pkt_open.h | 57 #define SDMA_PKT_HEADER_OP(x) (((x) & SDMA_PKT_HEADER_op_mask) << SDMA_PKT_HEADER_op_shift) argument
63 #define SDMA_PKT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_HEADER_sub_op_mask) << SDMA_PKT_HEADER_sub_op_sh… argument
74 #define SDMA_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_PKT_… argument
80 #define SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask) << S… argument
86 #define SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask… argument
93 #define SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_… argument
100 #define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask… argument
106 #define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_mask… argument
112 #define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask… argument
118 #define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_mask… argument
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