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1  /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2  /*
3   * Performance events:
4   *
5   *    Copyright (C) 2008-2009, Thomas Gleixner <tglx@linutronix.de>
6   *    Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar
7   *    Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra
8   *
9   * Data type definitions, declarations, prototypes.
10   *
11   *    Started by: Thomas Gleixner and Ingo Molnar
12   *
13   * For licencing details see kernel-base/COPYING
14   */
15  #ifndef _UAPI_LINUX_PERF_EVENT_H
16  #define _UAPI_LINUX_PERF_EVENT_H
17  
18  #include <linux/types.h>
19  #include <linux/ioctl.h>
20  #include <asm/byteorder.h>
21  
22  /*
23   * User-space ABI bits:
24   */
25  
26  /*
27   * attr.type
28   */
29  enum perf_type_id {
30  	PERF_TYPE_HARDWARE			= 0,
31  	PERF_TYPE_SOFTWARE			= 1,
32  	PERF_TYPE_TRACEPOINT			= 2,
33  	PERF_TYPE_HW_CACHE			= 3,
34  	PERF_TYPE_RAW				= 4,
35  	PERF_TYPE_BREAKPOINT			= 5,
36  
37  	PERF_TYPE_MAX,				/* non-ABI */
38  };
39  
40  /*
41   * attr.config layout for type PERF_TYPE_HARDWARE and PERF_TYPE_HW_CACHE
42   * PERF_TYPE_HARDWARE:			0xEEEEEEEE000000AA
43   *					AA: hardware event ID
44   *					EEEEEEEE: PMU type ID
45   * PERF_TYPE_HW_CACHE:			0xEEEEEEEE00DDCCBB
46   *					BB: hardware cache ID
47   *					CC: hardware cache op ID
48   *					DD: hardware cache op result ID
49   *					EEEEEEEE: PMU type ID
50   * If the PMU type ID is 0, the PERF_TYPE_RAW will be applied.
51   */
52  #define PERF_PMU_TYPE_SHIFT		32
53  #define PERF_HW_EVENT_MASK		0xffffffff
54  
55  /*
56   * Generalized performance event event_id types, used by the
57   * attr.event_id parameter of the sys_perf_event_open()
58   * syscall:
59   */
60  enum perf_hw_id {
61  	/*
62  	 * Common hardware events, generalized by the kernel:
63  	 */
64  	PERF_COUNT_HW_CPU_CYCLES		= 0,
65  	PERF_COUNT_HW_INSTRUCTIONS		= 1,
66  	PERF_COUNT_HW_CACHE_REFERENCES		= 2,
67  	PERF_COUNT_HW_CACHE_MISSES		= 3,
68  	PERF_COUNT_HW_BRANCH_INSTRUCTIONS	= 4,
69  	PERF_COUNT_HW_BRANCH_MISSES		= 5,
70  	PERF_COUNT_HW_BUS_CYCLES		= 6,
71  	PERF_COUNT_HW_STALLED_CYCLES_FRONTEND	= 7,
72  	PERF_COUNT_HW_STALLED_CYCLES_BACKEND	= 8,
73  	PERF_COUNT_HW_REF_CPU_CYCLES		= 9,
74  
75  	PERF_COUNT_HW_MAX,			/* non-ABI */
76  };
77  
78  /*
79   * Generalized hardware cache events:
80   *
81   *       { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x
82   *       { read, write, prefetch } x
83   *       { accesses, misses }
84   */
85  enum perf_hw_cache_id {
86  	PERF_COUNT_HW_CACHE_L1D			= 0,
87  	PERF_COUNT_HW_CACHE_L1I			= 1,
88  	PERF_COUNT_HW_CACHE_LL			= 2,
89  	PERF_COUNT_HW_CACHE_DTLB		= 3,
90  	PERF_COUNT_HW_CACHE_ITLB		= 4,
91  	PERF_COUNT_HW_CACHE_BPU			= 5,
92  	PERF_COUNT_HW_CACHE_NODE		= 6,
93  
94  	PERF_COUNT_HW_CACHE_MAX,		/* non-ABI */
95  };
96  
97  enum perf_hw_cache_op_id {
98  	PERF_COUNT_HW_CACHE_OP_READ		= 0,
99  	PERF_COUNT_HW_CACHE_OP_WRITE		= 1,
100  	PERF_COUNT_HW_CACHE_OP_PREFETCH		= 2,
101  
102  	PERF_COUNT_HW_CACHE_OP_MAX,		/* non-ABI */
103  };
104  
105  enum perf_hw_cache_op_result_id {
106  	PERF_COUNT_HW_CACHE_RESULT_ACCESS	= 0,
107  	PERF_COUNT_HW_CACHE_RESULT_MISS		= 1,
108  
109  	PERF_COUNT_HW_CACHE_RESULT_MAX,		/* non-ABI */
110  };
111  
112  /*
113   * Special "software" events provided by the kernel, even if the hardware
114   * does not support performance events. These events measure various
115   * physical and sw events of the kernel (and allow the profiling of them as
116   * well):
117   */
118  enum perf_sw_ids {
119  	PERF_COUNT_SW_CPU_CLOCK			= 0,
120  	PERF_COUNT_SW_TASK_CLOCK		= 1,
121  	PERF_COUNT_SW_PAGE_FAULTS		= 2,
122  	PERF_COUNT_SW_CONTEXT_SWITCHES		= 3,
123  	PERF_COUNT_SW_CPU_MIGRATIONS		= 4,
124  	PERF_COUNT_SW_PAGE_FAULTS_MIN		= 5,
125  	PERF_COUNT_SW_PAGE_FAULTS_MAJ		= 6,
126  	PERF_COUNT_SW_ALIGNMENT_FAULTS		= 7,
127  	PERF_COUNT_SW_EMULATION_FAULTS		= 8,
128  	PERF_COUNT_SW_DUMMY			= 9,
129  	PERF_COUNT_SW_BPF_OUTPUT		= 10,
130  	PERF_COUNT_SW_CGROUP_SWITCHES		= 11,
131  
132  	PERF_COUNT_SW_MAX,			/* non-ABI */
133  };
134  
135  /*
136   * Bits that can be set in attr.sample_type to request information
137   * in the overflow packets.
138   */
139  enum perf_event_sample_format {
140  	PERF_SAMPLE_IP				= 1U << 0,
141  	PERF_SAMPLE_TID				= 1U << 1,
142  	PERF_SAMPLE_TIME			= 1U << 2,
143  	PERF_SAMPLE_ADDR			= 1U << 3,
144  	PERF_SAMPLE_READ			= 1U << 4,
145  	PERF_SAMPLE_CALLCHAIN			= 1U << 5,
146  	PERF_SAMPLE_ID				= 1U << 6,
147  	PERF_SAMPLE_CPU				= 1U << 7,
148  	PERF_SAMPLE_PERIOD			= 1U << 8,
149  	PERF_SAMPLE_STREAM_ID			= 1U << 9,
150  	PERF_SAMPLE_RAW				= 1U << 10,
151  	PERF_SAMPLE_BRANCH_STACK		= 1U << 11,
152  	PERF_SAMPLE_REGS_USER			= 1U << 12,
153  	PERF_SAMPLE_STACK_USER			= 1U << 13,
154  	PERF_SAMPLE_WEIGHT			= 1U << 14,
155  	PERF_SAMPLE_DATA_SRC			= 1U << 15,
156  	PERF_SAMPLE_IDENTIFIER			= 1U << 16,
157  	PERF_SAMPLE_TRANSACTION			= 1U << 17,
158  	PERF_SAMPLE_REGS_INTR			= 1U << 18,
159  	PERF_SAMPLE_PHYS_ADDR			= 1U << 19,
160  	PERF_SAMPLE_AUX				= 1U << 20,
161  	PERF_SAMPLE_CGROUP			= 1U << 21,
162  	PERF_SAMPLE_DATA_PAGE_SIZE		= 1U << 22,
163  	PERF_SAMPLE_CODE_PAGE_SIZE		= 1U << 23,
164  	PERF_SAMPLE_WEIGHT_STRUCT		= 1U << 24,
165  
166  	PERF_SAMPLE_MAX = 1U << 25,		/* non-ABI */
167  
168  	__PERF_SAMPLE_CALLCHAIN_EARLY		= 1ULL << 63, /* non-ABI; internal use */
169  };
170  
171  #define PERF_SAMPLE_WEIGHT_TYPE	(PERF_SAMPLE_WEIGHT | PERF_SAMPLE_WEIGHT_STRUCT)
172  /*
173   * values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set
174   *
175   * If the user does not pass priv level information via branch_sample_type,
176   * the kernel uses the event's priv level. Branch and event priv levels do
177   * not have to match. Branch priv level is checked for permissions.
178   *
179   * The branch types can be combined, however BRANCH_ANY covers all types
180   * of branches and therefore it supersedes all the other types.
181   */
182  enum perf_branch_sample_type_shift {
183  	PERF_SAMPLE_BRANCH_USER_SHIFT		= 0, /* user branches */
184  	PERF_SAMPLE_BRANCH_KERNEL_SHIFT		= 1, /* kernel branches */
185  	PERF_SAMPLE_BRANCH_HV_SHIFT		= 2, /* hypervisor branches */
186  
187  	PERF_SAMPLE_BRANCH_ANY_SHIFT		= 3, /* any branch types */
188  	PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT	= 4, /* any call branch */
189  	PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT	= 5, /* any return branch */
190  	PERF_SAMPLE_BRANCH_IND_CALL_SHIFT	= 6, /* indirect calls */
191  	PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT	= 7, /* transaction aborts */
192  	PERF_SAMPLE_BRANCH_IN_TX_SHIFT		= 8, /* in transaction */
193  	PERF_SAMPLE_BRANCH_NO_TX_SHIFT		= 9, /* not in transaction */
194  	PERF_SAMPLE_BRANCH_COND_SHIFT		= 10, /* conditional branches */
195  
196  	PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT	= 11, /* call/ret stack */
197  	PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT	= 12, /* indirect jumps */
198  	PERF_SAMPLE_BRANCH_CALL_SHIFT		= 13, /* direct call */
199  
200  	PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT	= 14, /* no flags */
201  	PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT	= 15, /* no cycles */
202  
203  	PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT	= 16, /* save branch type */
204  
205  	PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT	= 17, /* save low level index of raw branch records */
206  
207  	PERF_SAMPLE_BRANCH_MAX_SHIFT		/* non-ABI */
208  };
209  
210  enum perf_branch_sample_type {
211  	PERF_SAMPLE_BRANCH_USER		= 1U << PERF_SAMPLE_BRANCH_USER_SHIFT,
212  	PERF_SAMPLE_BRANCH_KERNEL	= 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT,
213  	PERF_SAMPLE_BRANCH_HV		= 1U << PERF_SAMPLE_BRANCH_HV_SHIFT,
214  
215  	PERF_SAMPLE_BRANCH_ANY		= 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT,
216  	PERF_SAMPLE_BRANCH_ANY_CALL	= 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT,
217  	PERF_SAMPLE_BRANCH_ANY_RETURN	= 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT,
218  	PERF_SAMPLE_BRANCH_IND_CALL	= 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT,
219  	PERF_SAMPLE_BRANCH_ABORT_TX	= 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT,
220  	PERF_SAMPLE_BRANCH_IN_TX	= 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT,
221  	PERF_SAMPLE_BRANCH_NO_TX	= 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT,
222  	PERF_SAMPLE_BRANCH_COND		= 1U << PERF_SAMPLE_BRANCH_COND_SHIFT,
223  
224  	PERF_SAMPLE_BRANCH_CALL_STACK	= 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT,
225  	PERF_SAMPLE_BRANCH_IND_JUMP	= 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT,
226  	PERF_SAMPLE_BRANCH_CALL		= 1U << PERF_SAMPLE_BRANCH_CALL_SHIFT,
227  
228  	PERF_SAMPLE_BRANCH_NO_FLAGS	= 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT,
229  	PERF_SAMPLE_BRANCH_NO_CYCLES	= 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT,
230  
231  	PERF_SAMPLE_BRANCH_TYPE_SAVE	=
232  		1U << PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT,
233  
234  	PERF_SAMPLE_BRANCH_HW_INDEX	= 1U << PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT,
235  
236  	PERF_SAMPLE_BRANCH_MAX		= 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT,
237  };
238  
239  /*
240   * Common flow change classification
241   */
242  enum {
243  	PERF_BR_UNKNOWN		= 0,	/* unknown */
244  	PERF_BR_COND		= 1,	/* conditional */
245  	PERF_BR_UNCOND		= 2,	/* unconditional  */
246  	PERF_BR_IND		= 3,	/* indirect */
247  	PERF_BR_CALL		= 4,	/* function call */
248  	PERF_BR_IND_CALL	= 5,	/* indirect function call */
249  	PERF_BR_RET		= 6,	/* function return */
250  	PERF_BR_SYSCALL		= 7,	/* syscall */
251  	PERF_BR_SYSRET		= 8,	/* syscall return */
252  	PERF_BR_COND_CALL	= 9,	/* conditional function call */
253  	PERF_BR_COND_RET	= 10,	/* conditional function return */
254  	PERF_BR_ERET		= 11,	/* exception return */
255  	PERF_BR_IRQ		= 12,	/* irq */
256  	PERF_BR_MAX,
257  };
258  
259  #define PERF_SAMPLE_BRANCH_PLM_ALL \
260  	(PERF_SAMPLE_BRANCH_USER|\
261  	 PERF_SAMPLE_BRANCH_KERNEL|\
262  	 PERF_SAMPLE_BRANCH_HV)
263  
264  /*
265   * Values to determine ABI of the registers dump.
266   */
267  enum perf_sample_regs_abi {
268  	PERF_SAMPLE_REGS_ABI_NONE	= 0,
269  	PERF_SAMPLE_REGS_ABI_32		= 1,
270  	PERF_SAMPLE_REGS_ABI_64		= 2,
271  };
272  
273  /*
274   * Values for the memory transaction event qualifier, mostly for
275   * abort events. Multiple bits can be set.
276   */
277  enum {
278  	PERF_TXN_ELISION        = (1 << 0), /* From elision */
279  	PERF_TXN_TRANSACTION    = (1 << 1), /* From transaction */
280  	PERF_TXN_SYNC           = (1 << 2), /* Instruction is related */
281  	PERF_TXN_ASYNC          = (1 << 3), /* Instruction not related */
282  	PERF_TXN_RETRY          = (1 << 4), /* Retry possible */
283  	PERF_TXN_CONFLICT       = (1 << 5), /* Conflict abort */
284  	PERF_TXN_CAPACITY_WRITE = (1 << 6), /* Capacity write abort */
285  	PERF_TXN_CAPACITY_READ  = (1 << 7), /* Capacity read abort */
286  
287  	PERF_TXN_MAX	        = (1 << 8), /* non-ABI */
288  
289  	/* bits 32..63 are reserved for the abort code */
290  
291  	PERF_TXN_ABORT_MASK  = (0xffffffffULL << 32),
292  	PERF_TXN_ABORT_SHIFT = 32,
293  };
294  
295  /*
296   * The format of the data returned by read() on a perf event fd,
297   * as specified by attr.read_format:
298   *
299   * struct read_format {
300   *	{ u64		value;
301   *	  { u64		time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED
302   *	  { u64		time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING
303   *	  { u64		id;           } && PERF_FORMAT_ID
304   *	} && !PERF_FORMAT_GROUP
305   *
306   *	{ u64		nr;
307   *	  { u64		time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED
308   *	  { u64		time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING
309   *	  { u64		value;
310   *	    { u64	id;           } && PERF_FORMAT_ID
311   *	  }		cntr[nr];
312   *	} && PERF_FORMAT_GROUP
313   * };
314   */
315  enum perf_event_read_format {
316  	PERF_FORMAT_TOTAL_TIME_ENABLED		= 1U << 0,
317  	PERF_FORMAT_TOTAL_TIME_RUNNING		= 1U << 1,
318  	PERF_FORMAT_ID				= 1U << 2,
319  	PERF_FORMAT_GROUP			= 1U << 3,
320  
321  	PERF_FORMAT_MAX = 1U << 4,		/* non-ABI */
322  };
323  
324  #define PERF_ATTR_SIZE_VER0	64	/* sizeof first published struct */
325  #define PERF_ATTR_SIZE_VER1	72	/* add: config2 */
326  #define PERF_ATTR_SIZE_VER2	80	/* add: branch_sample_type */
327  #define PERF_ATTR_SIZE_VER3	96	/* add: sample_regs_user */
328  					/* add: sample_stack_user */
329  #define PERF_ATTR_SIZE_VER4	104	/* add: sample_regs_intr */
330  #define PERF_ATTR_SIZE_VER5	112	/* add: aux_watermark */
331  #define PERF_ATTR_SIZE_VER6	120	/* add: aux_sample_size */
332  #define PERF_ATTR_SIZE_VER7	128	/* add: sig_data */
333  
334  /*
335   * Hardware event_id to monitor via a performance monitoring event:
336   *
337   * @sample_max_stack: Max number of frame pointers in a callchain,
338   *		      should be < /proc/sys/kernel/perf_event_max_stack
339   */
340  struct perf_event_attr {
341  
342  	/*
343  	 * Major type: hardware/software/tracepoint/etc.
344  	 */
345  	__u32			type;
346  
347  	/*
348  	 * Size of the attr structure, for fwd/bwd compat.
349  	 */
350  	__u32			size;
351  
352  	/*
353  	 * Type specific configuration information.
354  	 */
355  	__u64			config;
356  
357  	union {
358  		__u64		sample_period;
359  		__u64		sample_freq;
360  	};
361  
362  	__u64			sample_type;
363  	__u64			read_format;
364  
365  	__u64			disabled       :  1, /* off by default        */
366  				inherit	       :  1, /* children inherit it   */
367  				pinned	       :  1, /* must always be on PMU */
368  				exclusive      :  1, /* only group on PMU     */
369  				exclude_user   :  1, /* don't count user      */
370  				exclude_kernel :  1, /* ditto kernel          */
371  				exclude_hv     :  1, /* ditto hypervisor      */
372  				exclude_idle   :  1, /* don't count when idle */
373  				mmap           :  1, /* include mmap data     */
374  				comm	       :  1, /* include comm data     */
375  				freq           :  1, /* use freq, not period  */
376  				inherit_stat   :  1, /* per task counts       */
377  				enable_on_exec :  1, /* next exec enables     */
378  				task           :  1, /* trace fork/exit       */
379  				watermark      :  1, /* wakeup_watermark      */
380  				/*
381  				 * precise_ip:
382  				 *
383  				 *  0 - SAMPLE_IP can have arbitrary skid
384  				 *  1 - SAMPLE_IP must have constant skid
385  				 *  2 - SAMPLE_IP requested to have 0 skid
386  				 *  3 - SAMPLE_IP must have 0 skid
387  				 *
388  				 *  See also PERF_RECORD_MISC_EXACT_IP
389  				 */
390  				precise_ip     :  2, /* skid constraint       */
391  				mmap_data      :  1, /* non-exec mmap data    */
392  				sample_id_all  :  1, /* sample_type all events */
393  
394  				exclude_host   :  1, /* don't count in host   */
395  				exclude_guest  :  1, /* don't count in guest  */
396  
397  				exclude_callchain_kernel : 1, /* exclude kernel callchains */
398  				exclude_callchain_user   : 1, /* exclude user callchains */
399  				mmap2          :  1, /* include mmap with inode data     */
400  				comm_exec      :  1, /* flag comm events that are due to an exec */
401  				use_clockid    :  1, /* use @clockid for time fields */
402  				context_switch :  1, /* context switch data */
403  				write_backward :  1, /* Write ring buffer from end to beginning */
404  				namespaces     :  1, /* include namespaces data */
405  				ksymbol        :  1, /* include ksymbol events */
406  				bpf_event      :  1, /* include bpf events */
407  				aux_output     :  1, /* generate AUX records instead of events */
408  				cgroup         :  1, /* include cgroup events */
409  				text_poke      :  1, /* include text poke events */
410  				build_id       :  1, /* use build id in mmap2 events */
411  				inherit_thread :  1, /* children only inherit if cloned with CLONE_THREAD */
412  				remove_on_exec :  1, /* event is removed from task on exec */
413  				sigtrap        :  1, /* send synchronous SIGTRAP on event */
414  				__reserved_1   : 26;
415  
416  	union {
417  		__u32		wakeup_events;	  /* wakeup every n events */
418  		__u32		wakeup_watermark; /* bytes before wakeup   */
419  	};
420  
421  	__u32			bp_type;
422  	union {
423  		__u64		bp_addr;
424  		__u64		kprobe_func; /* for perf_kprobe */
425  		__u64		uprobe_path; /* for perf_uprobe */
426  		__u64		config1; /* extension of config */
427  	};
428  	union {
429  		__u64		bp_len;
430  		__u64		kprobe_addr; /* when kprobe_func == NULL */
431  		__u64		probe_offset; /* for perf_[k,u]probe */
432  		__u64		config2; /* extension of config1 */
433  	};
434  	__u64	branch_sample_type; /* enum perf_branch_sample_type */
435  
436  	/*
437  	 * Defines set of user regs to dump on samples.
438  	 * See asm/perf_regs.h for details.
439  	 */
440  	__u64	sample_regs_user;
441  
442  	/*
443  	 * Defines size of the user stack to dump on samples.
444  	 */
445  	__u32	sample_stack_user;
446  
447  	__s32	clockid;
448  	/*
449  	 * Defines set of regs to dump for each sample
450  	 * state captured on:
451  	 *  - precise = 0: PMU interrupt
452  	 *  - precise > 0: sampled instruction
453  	 *
454  	 * See asm/perf_regs.h for details.
455  	 */
456  	__u64	sample_regs_intr;
457  
458  	/*
459  	 * Wakeup watermark for AUX area
460  	 */
461  	__u32	aux_watermark;
462  	__u16	sample_max_stack;
463  	__u16	__reserved_2;
464  	__u32	aux_sample_size;
465  	__u32	__reserved_3;
466  
467  	/*
468  	 * User provided data if sigtrap=1, passed back to user via
469  	 * siginfo_t::si_perf_data, e.g. to permit user to identify the event.
470  	 */
471  	__u64	sig_data;
472  };
473  
474  /*
475   * Structure used by below PERF_EVENT_IOC_QUERY_BPF command
476   * to query bpf programs attached to the same perf tracepoint
477   * as the given perf event.
478   */
479  struct perf_event_query_bpf {
480  	/*
481  	 * The below ids array length
482  	 */
483  	__u32	ids_len;
484  	/*
485  	 * Set by the kernel to indicate the number of
486  	 * available programs
487  	 */
488  	__u32	prog_cnt;
489  	/*
490  	 * User provided buffer to store program ids
491  	 */
492  	__u32	ids[0];
493  };
494  
495  /*
496   * Ioctls that can be done on a perf event fd:
497   */
498  #define PERF_EVENT_IOC_ENABLE			_IO ('$', 0)
499  #define PERF_EVENT_IOC_DISABLE			_IO ('$', 1)
500  #define PERF_EVENT_IOC_REFRESH			_IO ('$', 2)
501  #define PERF_EVENT_IOC_RESET			_IO ('$', 3)
502  #define PERF_EVENT_IOC_PERIOD			_IOW('$', 4, __u64)
503  #define PERF_EVENT_IOC_SET_OUTPUT		_IO ('$', 5)
504  #define PERF_EVENT_IOC_SET_FILTER		_IOW('$', 6, char *)
505  #define PERF_EVENT_IOC_ID			_IOR('$', 7, __u64 *)
506  #define PERF_EVENT_IOC_SET_BPF			_IOW('$', 8, __u32)
507  #define PERF_EVENT_IOC_PAUSE_OUTPUT		_IOW('$', 9, __u32)
508  #define PERF_EVENT_IOC_QUERY_BPF		_IOWR('$', 10, struct perf_event_query_bpf *)
509  #define PERF_EVENT_IOC_MODIFY_ATTRIBUTES	_IOW('$', 11, struct perf_event_attr *)
510  
511  enum perf_event_ioc_flags {
512  	PERF_IOC_FLAG_GROUP		= 1U << 0,
513  };
514  
515  /*
516   * Structure of the page that can be mapped via mmap
517   */
518  struct perf_event_mmap_page {
519  	__u32	version;		/* version number of this structure */
520  	__u32	compat_version;		/* lowest version this is compat with */
521  
522  	/*
523  	 * Bits needed to read the hw events in user-space.
524  	 *
525  	 *   u32 seq, time_mult, time_shift, index, width;
526  	 *   u64 count, enabled, running;
527  	 *   u64 cyc, time_offset;
528  	 *   s64 pmc = 0;
529  	 *
530  	 *   do {
531  	 *     seq = pc->lock;
532  	 *     barrier()
533  	 *
534  	 *     enabled = pc->time_enabled;
535  	 *     running = pc->time_running;
536  	 *
537  	 *     if (pc->cap_usr_time && enabled != running) {
538  	 *       cyc = rdtsc();
539  	 *       time_offset = pc->time_offset;
540  	 *       time_mult   = pc->time_mult;
541  	 *       time_shift  = pc->time_shift;
542  	 *     }
543  	 *
544  	 *     index = pc->index;
545  	 *     count = pc->offset;
546  	 *     if (pc->cap_user_rdpmc && index) {
547  	 *       width = pc->pmc_width;
548  	 *       pmc = rdpmc(index - 1);
549  	 *     }
550  	 *
551  	 *     barrier();
552  	 *   } while (pc->lock != seq);
553  	 *
554  	 * NOTE: for obvious reason this only works on self-monitoring
555  	 *       processes.
556  	 */
557  	__u32	lock;			/* seqlock for synchronization */
558  	__u32	index;			/* hardware event identifier */
559  	__s64	offset;			/* add to hardware event value */
560  	__u64	time_enabled;		/* time event active */
561  	__u64	time_running;		/* time event on cpu */
562  	union {
563  		__u64	capabilities;
564  		struct {
565  			__u64	cap_bit0		: 1, /* Always 0, deprecated, see commit 860f085b74e9 */
566  				cap_bit0_is_deprecated	: 1, /* Always 1, signals that bit 0 is zero */
567  
568  				cap_user_rdpmc		: 1, /* The RDPMC instruction can be used to read counts */
569  				cap_user_time		: 1, /* The time_{shift,mult,offset} fields are used */
570  				cap_user_time_zero	: 1, /* The time_zero field is used */
571  				cap_user_time_short	: 1, /* the time_{cycle,mask} fields are used */
572  				cap_____res		: 58;
573  		};
574  	};
575  
576  	/*
577  	 * If cap_user_rdpmc this field provides the bit-width of the value
578  	 * read using the rdpmc() or equivalent instruction. This can be used
579  	 * to sign extend the result like:
580  	 *
581  	 *   pmc <<= 64 - width;
582  	 *   pmc >>= 64 - width; // signed shift right
583  	 *   count += pmc;
584  	 */
585  	__u16	pmc_width;
586  
587  	/*
588  	 * If cap_usr_time the below fields can be used to compute the time
589  	 * delta since time_enabled (in ns) using rdtsc or similar.
590  	 *
591  	 *   u64 quot, rem;
592  	 *   u64 delta;
593  	 *
594  	 *   quot = (cyc >> time_shift);
595  	 *   rem = cyc & (((u64)1 << time_shift) - 1);
596  	 *   delta = time_offset + quot * time_mult +
597  	 *              ((rem * time_mult) >> time_shift);
598  	 *
599  	 * Where time_offset,time_mult,time_shift and cyc are read in the
600  	 * seqcount loop described above. This delta can then be added to
601  	 * enabled and possible running (if index), improving the scaling:
602  	 *
603  	 *   enabled += delta;
604  	 *   if (index)
605  	 *     running += delta;
606  	 *
607  	 *   quot = count / running;
608  	 *   rem  = count % running;
609  	 *   count = quot * enabled + (rem * enabled) / running;
610  	 */
611  	__u16	time_shift;
612  	__u32	time_mult;
613  	__u64	time_offset;
614  	/*
615  	 * If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated
616  	 * from sample timestamps.
617  	 *
618  	 *   time = timestamp - time_zero;
619  	 *   quot = time / time_mult;
620  	 *   rem  = time % time_mult;
621  	 *   cyc = (quot << time_shift) + (rem << time_shift) / time_mult;
622  	 *
623  	 * And vice versa:
624  	 *
625  	 *   quot = cyc >> time_shift;
626  	 *   rem  = cyc & (((u64)1 << time_shift) - 1);
627  	 *   timestamp = time_zero + quot * time_mult +
628  	 *               ((rem * time_mult) >> time_shift);
629  	 */
630  	__u64	time_zero;
631  
632  	__u32	size;			/* Header size up to __reserved[] fields. */
633  	__u32	__reserved_1;
634  
635  	/*
636  	 * If cap_usr_time_short, the hardware clock is less than 64bit wide
637  	 * and we must compute the 'cyc' value, as used by cap_usr_time, as:
638  	 *
639  	 *   cyc = time_cycles + ((cyc - time_cycles) & time_mask)
640  	 *
641  	 * NOTE: this form is explicitly chosen such that cap_usr_time_short
642  	 *       is a correction on top of cap_usr_time, and code that doesn't
643  	 *       know about cap_usr_time_short still works under the assumption
644  	 *       the counter doesn't wrap.
645  	 */
646  	__u64	time_cycles;
647  	__u64	time_mask;
648  
649  		/*
650  		 * Hole for extension of the self monitor capabilities
651  		 */
652  
653  	__u8	__reserved[116*8];	/* align to 1k. */
654  
655  	/*
656  	 * Control data for the mmap() data buffer.
657  	 *
658  	 * User-space reading the @data_head value should issue an smp_rmb(),
659  	 * after reading this value.
660  	 *
661  	 * When the mapping is PROT_WRITE the @data_tail value should be
662  	 * written by userspace to reflect the last read data, after issueing
663  	 * an smp_mb() to separate the data read from the ->data_tail store.
664  	 * In this case the kernel will not over-write unread data.
665  	 *
666  	 * See perf_output_put_handle() for the data ordering.
667  	 *
668  	 * data_{offset,size} indicate the location and size of the perf record
669  	 * buffer within the mmapped area.
670  	 */
671  	__u64   data_head;		/* head in the data section */
672  	__u64	data_tail;		/* user-space written tail */
673  	__u64	data_offset;		/* where the buffer starts */
674  	__u64	data_size;		/* data buffer size */
675  
676  	/*
677  	 * AUX area is defined by aux_{offset,size} fields that should be set
678  	 * by the userspace, so that
679  	 *
680  	 *   aux_offset >= data_offset + data_size
681  	 *
682  	 * prior to mmap()ing it. Size of the mmap()ed area should be aux_size.
683  	 *
684  	 * Ring buffer pointers aux_{head,tail} have the same semantics as
685  	 * data_{head,tail} and same ordering rules apply.
686  	 */
687  	__u64	aux_head;
688  	__u64	aux_tail;
689  	__u64	aux_offset;
690  	__u64	aux_size;
691  };
692  
693  /*
694   * The current state of perf_event_header::misc bits usage:
695   * ('|' used bit, '-' unused bit)
696   *
697   *  012         CDEF
698   *  |||---------||||
699   *
700   *  Where:
701   *    0-2     CPUMODE_MASK
702   *
703   *    C       PROC_MAP_PARSE_TIMEOUT
704   *    D       MMAP_DATA / COMM_EXEC / FORK_EXEC / SWITCH_OUT
705   *    E       MMAP_BUILD_ID / EXACT_IP / SCHED_OUT_PREEMPT
706   *    F       (reserved)
707   */
708  
709  #define PERF_RECORD_MISC_CPUMODE_MASK		(7 << 0)
710  #define PERF_RECORD_MISC_CPUMODE_UNKNOWN	(0 << 0)
711  #define PERF_RECORD_MISC_KERNEL			(1 << 0)
712  #define PERF_RECORD_MISC_USER			(2 << 0)
713  #define PERF_RECORD_MISC_HYPERVISOR		(3 << 0)
714  #define PERF_RECORD_MISC_GUEST_KERNEL		(4 << 0)
715  #define PERF_RECORD_MISC_GUEST_USER		(5 << 0)
716  
717  /*
718   * Indicates that /proc/PID/maps parsing are truncated by time out.
719   */
720  #define PERF_RECORD_MISC_PROC_MAP_PARSE_TIMEOUT	(1 << 12)
721  /*
722   * Following PERF_RECORD_MISC_* are used on different
723   * events, so can reuse the same bit position:
724   *
725   *   PERF_RECORD_MISC_MMAP_DATA  - PERF_RECORD_MMAP* events
726   *   PERF_RECORD_MISC_COMM_EXEC  - PERF_RECORD_COMM event
727   *   PERF_RECORD_MISC_FORK_EXEC  - PERF_RECORD_FORK event (perf internal)
728   *   PERF_RECORD_MISC_SWITCH_OUT - PERF_RECORD_SWITCH* events
729   */
730  #define PERF_RECORD_MISC_MMAP_DATA		(1 << 13)
731  #define PERF_RECORD_MISC_COMM_EXEC		(1 << 13)
732  #define PERF_RECORD_MISC_FORK_EXEC		(1 << 13)
733  #define PERF_RECORD_MISC_SWITCH_OUT		(1 << 13)
734  /*
735   * These PERF_RECORD_MISC_* flags below are safely reused
736   * for the following events:
737   *
738   *   PERF_RECORD_MISC_EXACT_IP           - PERF_RECORD_SAMPLE of precise events
739   *   PERF_RECORD_MISC_SWITCH_OUT_PREEMPT - PERF_RECORD_SWITCH* events
740   *   PERF_RECORD_MISC_MMAP_BUILD_ID      - PERF_RECORD_MMAP2 event
741   *
742   *
743   * PERF_RECORD_MISC_EXACT_IP:
744   *   Indicates that the content of PERF_SAMPLE_IP points to
745   *   the actual instruction that triggered the event. See also
746   *   perf_event_attr::precise_ip.
747   *
748   * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT:
749   *   Indicates that thread was preempted in TASK_RUNNING state.
750   *
751   * PERF_RECORD_MISC_MMAP_BUILD_ID:
752   *   Indicates that mmap2 event carries build id data.
753   */
754  #define PERF_RECORD_MISC_EXACT_IP		(1 << 14)
755  #define PERF_RECORD_MISC_SWITCH_OUT_PREEMPT	(1 << 14)
756  #define PERF_RECORD_MISC_MMAP_BUILD_ID		(1 << 14)
757  /*
758   * Reserve the last bit to indicate some extended misc field
759   */
760  #define PERF_RECORD_MISC_EXT_RESERVED		(1 << 15)
761  
762  struct perf_event_header {
763  	__u32	type;
764  	__u16	misc;
765  	__u16	size;
766  };
767  
768  struct perf_ns_link_info {
769  	__u64	dev;
770  	__u64	ino;
771  };
772  
773  enum {
774  	NET_NS_INDEX		= 0,
775  	UTS_NS_INDEX		= 1,
776  	IPC_NS_INDEX		= 2,
777  	PID_NS_INDEX		= 3,
778  	USER_NS_INDEX		= 4,
779  	MNT_NS_INDEX		= 5,
780  	CGROUP_NS_INDEX		= 6,
781  
782  	NR_NAMESPACES,		/* number of available namespaces */
783  };
784  
785  enum perf_event_type {
786  
787  	/*
788  	 * If perf_event_attr.sample_id_all is set then all event types will
789  	 * have the sample_type selected fields related to where/when
790  	 * (identity) an event took place (TID, TIME, ID, STREAM_ID, CPU,
791  	 * IDENTIFIER) described in PERF_RECORD_SAMPLE below, it will be stashed
792  	 * just after the perf_event_header and the fields already present for
793  	 * the existing fields, i.e. at the end of the payload. That way a newer
794  	 * perf.data file will be supported by older perf tools, with these new
795  	 * optional fields being ignored.
796  	 *
797  	 * struct sample_id {
798  	 * 	{ u32			pid, tid; } && PERF_SAMPLE_TID
799  	 * 	{ u64			time;     } && PERF_SAMPLE_TIME
800  	 * 	{ u64			id;       } && PERF_SAMPLE_ID
801  	 * 	{ u64			stream_id;} && PERF_SAMPLE_STREAM_ID
802  	 * 	{ u32			cpu, res; } && PERF_SAMPLE_CPU
803  	 *	{ u64			id;	  } && PERF_SAMPLE_IDENTIFIER
804  	 * } && perf_event_attr::sample_id_all
805  	 *
806  	 * Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID.  The
807  	 * advantage of PERF_SAMPLE_IDENTIFIER is that its position is fixed
808  	 * relative to header.size.
809  	 */
810  
811  	/*
812  	 * The MMAP events record the PROT_EXEC mappings so that we can
813  	 * correlate userspace IPs to code. They have the following structure:
814  	 *
815  	 * struct {
816  	 *	struct perf_event_header	header;
817  	 *
818  	 *	u32				pid, tid;
819  	 *	u64				addr;
820  	 *	u64				len;
821  	 *	u64				pgoff;
822  	 *	char				filename[];
823  	 * 	struct sample_id		sample_id;
824  	 * };
825  	 */
826  	PERF_RECORD_MMAP			= 1,
827  
828  	/*
829  	 * struct {
830  	 *	struct perf_event_header	header;
831  	 *	u64				id;
832  	 *	u64				lost;
833  	 * 	struct sample_id		sample_id;
834  	 * };
835  	 */
836  	PERF_RECORD_LOST			= 2,
837  
838  	/*
839  	 * struct {
840  	 *	struct perf_event_header	header;
841  	 *
842  	 *	u32				pid, tid;
843  	 *	char				comm[];
844  	 * 	struct sample_id		sample_id;
845  	 * };
846  	 */
847  	PERF_RECORD_COMM			= 3,
848  
849  	/*
850  	 * struct {
851  	 *	struct perf_event_header	header;
852  	 *	u32				pid, ppid;
853  	 *	u32				tid, ptid;
854  	 *	u64				time;
855  	 * 	struct sample_id		sample_id;
856  	 * };
857  	 */
858  	PERF_RECORD_EXIT			= 4,
859  
860  	/*
861  	 * struct {
862  	 *	struct perf_event_header	header;
863  	 *	u64				time;
864  	 *	u64				id;
865  	 *	u64				stream_id;
866  	 * 	struct sample_id		sample_id;
867  	 * };
868  	 */
869  	PERF_RECORD_THROTTLE			= 5,
870  	PERF_RECORD_UNTHROTTLE			= 6,
871  
872  	/*
873  	 * struct {
874  	 *	struct perf_event_header	header;
875  	 *	u32				pid, ppid;
876  	 *	u32				tid, ptid;
877  	 *	u64				time;
878  	 * 	struct sample_id		sample_id;
879  	 * };
880  	 */
881  	PERF_RECORD_FORK			= 7,
882  
883  	/*
884  	 * struct {
885  	 *	struct perf_event_header	header;
886  	 *	u32				pid, tid;
887  	 *
888  	 *	struct read_format		values;
889  	 * 	struct sample_id		sample_id;
890  	 * };
891  	 */
892  	PERF_RECORD_READ			= 8,
893  
894  	/*
895  	 * struct {
896  	 *	struct perf_event_header	header;
897  	 *
898  	 *	#
899  	 *	# Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID.
900  	 *	# The advantage of PERF_SAMPLE_IDENTIFIER is that its position
901  	 *	# is fixed relative to header.
902  	 *	#
903  	 *
904  	 *	{ u64			id;	  } && PERF_SAMPLE_IDENTIFIER
905  	 *	{ u64			ip;	  } && PERF_SAMPLE_IP
906  	 *	{ u32			pid, tid; } && PERF_SAMPLE_TID
907  	 *	{ u64			time;     } && PERF_SAMPLE_TIME
908  	 *	{ u64			addr;     } && PERF_SAMPLE_ADDR
909  	 *	{ u64			id;	  } && PERF_SAMPLE_ID
910  	 *	{ u64			stream_id;} && PERF_SAMPLE_STREAM_ID
911  	 *	{ u32			cpu, res; } && PERF_SAMPLE_CPU
912  	 *	{ u64			period;   } && PERF_SAMPLE_PERIOD
913  	 *
914  	 *	{ struct read_format	values;	  } && PERF_SAMPLE_READ
915  	 *
916  	 *	{ u64			nr,
917  	 *	  u64			ips[nr];  } && PERF_SAMPLE_CALLCHAIN
918  	 *
919  	 *	#
920  	 *	# The RAW record below is opaque data wrt the ABI
921  	 *	#
922  	 *	# That is, the ABI doesn't make any promises wrt to
923  	 *	# the stability of its content, it may vary depending
924  	 *	# on event, hardware, kernel version and phase of
925  	 *	# the moon.
926  	 *	#
927  	 *	# In other words, PERF_SAMPLE_RAW contents are not an ABI.
928  	 *	#
929  	 *
930  	 *	{ u32			size;
931  	 *	  char                  data[size];}&& PERF_SAMPLE_RAW
932  	 *
933  	 *	{ u64                   nr;
934  	 *	  { u64	hw_idx; } && PERF_SAMPLE_BRANCH_HW_INDEX
935  	 *        { u64 from, to, flags } lbr[nr];
936  	 *      } && PERF_SAMPLE_BRANCH_STACK
937  	 *
938  	 * 	{ u64			abi; # enum perf_sample_regs_abi
939  	 * 	  u64			regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER
940  	 *
941  	 * 	{ u64			size;
942  	 * 	  char			data[size];
943  	 * 	  u64			dyn_size; } && PERF_SAMPLE_STACK_USER
944  	 *
945  	 *	{ union perf_sample_weight
946  	 *	 {
947  	 *		u64		full; && PERF_SAMPLE_WEIGHT
948  	 *	#if defined(__LITTLE_ENDIAN_BITFIELD)
949  	 *		struct {
950  	 *			u32	var1_dw;
951  	 *			u16	var2_w;
952  	 *			u16	var3_w;
953  	 *		} && PERF_SAMPLE_WEIGHT_STRUCT
954  	 *	#elif defined(__BIG_ENDIAN_BITFIELD)
955  	 *		struct {
956  	 *			u16	var3_w;
957  	 *			u16	var2_w;
958  	 *			u32	var1_dw;
959  	 *		} && PERF_SAMPLE_WEIGHT_STRUCT
960  	 *	#endif
961  	 *	 }
962  	 *	}
963  	 *	{ u64			data_src; } && PERF_SAMPLE_DATA_SRC
964  	 *	{ u64			transaction; } && PERF_SAMPLE_TRANSACTION
965  	 *	{ u64			abi; # enum perf_sample_regs_abi
966  	 *	  u64			regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR
967  	 *	{ u64			phys_addr;} && PERF_SAMPLE_PHYS_ADDR
968  	 *	{ u64			size;
969  	 *	  char			data[size]; } && PERF_SAMPLE_AUX
970  	 *	{ u64			data_page_size;} && PERF_SAMPLE_DATA_PAGE_SIZE
971  	 *	{ u64			code_page_size;} && PERF_SAMPLE_CODE_PAGE_SIZE
972  	 * };
973  	 */
974  	PERF_RECORD_SAMPLE			= 9,
975  
976  	/*
977  	 * The MMAP2 records are an augmented version of MMAP, they add
978  	 * maj, min, ino numbers to be used to uniquely identify each mapping
979  	 *
980  	 * struct {
981  	 *	struct perf_event_header	header;
982  	 *
983  	 *	u32				pid, tid;
984  	 *	u64				addr;
985  	 *	u64				len;
986  	 *	u64				pgoff;
987  	 *	union {
988  	 *		struct {
989  	 *			u32		maj;
990  	 *			u32		min;
991  	 *			u64		ino;
992  	 *			u64		ino_generation;
993  	 *		};
994  	 *		struct {
995  	 *			u8		build_id_size;
996  	 *			u8		__reserved_1;
997  	 *			u16		__reserved_2;
998  	 *			u8		build_id[20];
999  	 *		};
1000  	 *	};
1001  	 *	u32				prot, flags;
1002  	 *	char				filename[];
1003  	 * 	struct sample_id		sample_id;
1004  	 * };
1005  	 */
1006  	PERF_RECORD_MMAP2			= 10,
1007  
1008  	/*
1009  	 * Records that new data landed in the AUX buffer part.
1010  	 *
1011  	 * struct {
1012  	 * 	struct perf_event_header	header;
1013  	 *
1014  	 * 	u64				aux_offset;
1015  	 * 	u64				aux_size;
1016  	 *	u64				flags;
1017  	 * 	struct sample_id		sample_id;
1018  	 * };
1019  	 */
1020  	PERF_RECORD_AUX				= 11,
1021  
1022  	/*
1023  	 * Indicates that instruction trace has started
1024  	 *
1025  	 * struct {
1026  	 *	struct perf_event_header	header;
1027  	 *	u32				pid;
1028  	 *	u32				tid;
1029  	 *	struct sample_id		sample_id;
1030  	 * };
1031  	 */
1032  	PERF_RECORD_ITRACE_START		= 12,
1033  
1034  	/*
1035  	 * Records the dropped/lost sample number.
1036  	 *
1037  	 * struct {
1038  	 *	struct perf_event_header	header;
1039  	 *
1040  	 *	u64				lost;
1041  	 *	struct sample_id		sample_id;
1042  	 * };
1043  	 */
1044  	PERF_RECORD_LOST_SAMPLES		= 13,
1045  
1046  	/*
1047  	 * Records a context switch in or out (flagged by
1048  	 * PERF_RECORD_MISC_SWITCH_OUT). See also
1049  	 * PERF_RECORD_SWITCH_CPU_WIDE.
1050  	 *
1051  	 * struct {
1052  	 *	struct perf_event_header	header;
1053  	 *	struct sample_id		sample_id;
1054  	 * };
1055  	 */
1056  	PERF_RECORD_SWITCH			= 14,
1057  
1058  	/*
1059  	 * CPU-wide version of PERF_RECORD_SWITCH with next_prev_pid and
1060  	 * next_prev_tid that are the next (switching out) or previous
1061  	 * (switching in) pid/tid.
1062  	 *
1063  	 * struct {
1064  	 *	struct perf_event_header	header;
1065  	 *	u32				next_prev_pid;
1066  	 *	u32				next_prev_tid;
1067  	 *	struct sample_id		sample_id;
1068  	 * };
1069  	 */
1070  	PERF_RECORD_SWITCH_CPU_WIDE		= 15,
1071  
1072  	/*
1073  	 * struct {
1074  	 *	struct perf_event_header	header;
1075  	 *	u32				pid;
1076  	 *	u32				tid;
1077  	 *	u64				nr_namespaces;
1078  	 *	{ u64				dev, inode; } [nr_namespaces];
1079  	 *	struct sample_id		sample_id;
1080  	 * };
1081  	 */
1082  	PERF_RECORD_NAMESPACES			= 16,
1083  
1084  	/*
1085  	 * Record ksymbol register/unregister events:
1086  	 *
1087  	 * struct {
1088  	 *	struct perf_event_header	header;
1089  	 *	u64				addr;
1090  	 *	u32				len;
1091  	 *	u16				ksym_type;
1092  	 *	u16				flags;
1093  	 *	char				name[];
1094  	 *	struct sample_id		sample_id;
1095  	 * };
1096  	 */
1097  	PERF_RECORD_KSYMBOL			= 17,
1098  
1099  	/*
1100  	 * Record bpf events:
1101  	 *  enum perf_bpf_event_type {
1102  	 *	PERF_BPF_EVENT_UNKNOWN		= 0,
1103  	 *	PERF_BPF_EVENT_PROG_LOAD	= 1,
1104  	 *	PERF_BPF_EVENT_PROG_UNLOAD	= 2,
1105  	 *  };
1106  	 *
1107  	 * struct {
1108  	 *	struct perf_event_header	header;
1109  	 *	u16				type;
1110  	 *	u16				flags;
1111  	 *	u32				id;
1112  	 *	u8				tag[BPF_TAG_SIZE];
1113  	 *	struct sample_id		sample_id;
1114  	 * };
1115  	 */
1116  	PERF_RECORD_BPF_EVENT			= 18,
1117  
1118  	/*
1119  	 * struct {
1120  	 *	struct perf_event_header	header;
1121  	 *	u64				id;
1122  	 *	char				path[];
1123  	 *	struct sample_id		sample_id;
1124  	 * };
1125  	 */
1126  	PERF_RECORD_CGROUP			= 19,
1127  
1128  	/*
1129  	 * Records changes to kernel text i.e. self-modified code. 'old_len' is
1130  	 * the number of old bytes, 'new_len' is the number of new bytes. Either
1131  	 * 'old_len' or 'new_len' may be zero to indicate, for example, the
1132  	 * addition or removal of a trampoline. 'bytes' contains the old bytes
1133  	 * followed immediately by the new bytes.
1134  	 *
1135  	 * struct {
1136  	 *	struct perf_event_header	header;
1137  	 *	u64				addr;
1138  	 *	u16				old_len;
1139  	 *	u16				new_len;
1140  	 *	u8				bytes[];
1141  	 *	struct sample_id		sample_id;
1142  	 * };
1143  	 */
1144  	PERF_RECORD_TEXT_POKE			= 20,
1145  
1146  	PERF_RECORD_MAX,			/* non-ABI */
1147  };
1148  
1149  enum perf_record_ksymbol_type {
1150  	PERF_RECORD_KSYMBOL_TYPE_UNKNOWN	= 0,
1151  	PERF_RECORD_KSYMBOL_TYPE_BPF		= 1,
1152  	/*
1153  	 * Out of line code such as kprobe-replaced instructions or optimized
1154  	 * kprobes or ftrace trampolines.
1155  	 */
1156  	PERF_RECORD_KSYMBOL_TYPE_OOL		= 2,
1157  	PERF_RECORD_KSYMBOL_TYPE_MAX		/* non-ABI */
1158  };
1159  
1160  #define PERF_RECORD_KSYMBOL_FLAGS_UNREGISTER	(1 << 0)
1161  
1162  enum perf_bpf_event_type {
1163  	PERF_BPF_EVENT_UNKNOWN		= 0,
1164  	PERF_BPF_EVENT_PROG_LOAD	= 1,
1165  	PERF_BPF_EVENT_PROG_UNLOAD	= 2,
1166  	PERF_BPF_EVENT_MAX,		/* non-ABI */
1167  };
1168  
1169  #define PERF_MAX_STACK_DEPTH		127
1170  #define PERF_MAX_CONTEXTS_PER_STACK	  8
1171  
1172  enum perf_callchain_context {
1173  	PERF_CONTEXT_HV			= (__u64)-32,
1174  	PERF_CONTEXT_KERNEL		= (__u64)-128,
1175  	PERF_CONTEXT_USER		= (__u64)-512,
1176  
1177  	PERF_CONTEXT_GUEST		= (__u64)-2048,
1178  	PERF_CONTEXT_GUEST_KERNEL	= (__u64)-2176,
1179  	PERF_CONTEXT_GUEST_USER		= (__u64)-2560,
1180  
1181  	PERF_CONTEXT_MAX		= (__u64)-4095,
1182  };
1183  
1184  /**
1185   * PERF_RECORD_AUX::flags bits
1186   */
1187  #define PERF_AUX_FLAG_TRUNCATED			0x01	/* record was truncated to fit */
1188  #define PERF_AUX_FLAG_OVERWRITE			0x02	/* snapshot from overwrite mode */
1189  #define PERF_AUX_FLAG_PARTIAL			0x04	/* record contains gaps */
1190  #define PERF_AUX_FLAG_COLLISION			0x08	/* sample collided with another */
1191  #define PERF_AUX_FLAG_PMU_FORMAT_TYPE_MASK	0xff00	/* PMU specific trace format type */
1192  
1193  /* CoreSight PMU AUX buffer formats */
1194  #define PERF_AUX_FLAG_CORESIGHT_FORMAT_CORESIGHT	0x0000 /* Default for backward compatibility */
1195  #define PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW		0x0100 /* Raw format of the source */
1196  
1197  #define PERF_FLAG_FD_NO_GROUP		(1UL << 0)
1198  #define PERF_FLAG_FD_OUTPUT		(1UL << 1)
1199  #define PERF_FLAG_PID_CGROUP		(1UL << 2) /* pid=cgroup id, per-cpu mode only */
1200  #define PERF_FLAG_FD_CLOEXEC		(1UL << 3) /* O_CLOEXEC */
1201  
1202  #if defined(__LITTLE_ENDIAN_BITFIELD)
1203  union perf_mem_data_src {
1204  	__u64 val;
1205  	struct {
1206  		__u64   mem_op:5,	/* type of opcode */
1207  			mem_lvl:14,	/* memory hierarchy level */
1208  			mem_snoop:5,	/* snoop mode */
1209  			mem_lock:2,	/* lock instr */
1210  			mem_dtlb:7,	/* tlb access */
1211  			mem_lvl_num:4,	/* memory hierarchy level number */
1212  			mem_remote:1,   /* remote */
1213  			mem_snoopx:2,	/* snoop mode, ext */
1214  			mem_blk:3,	/* access blocked */
1215  			mem_rsvd:21;
1216  	};
1217  };
1218  #elif defined(__BIG_ENDIAN_BITFIELD)
1219  union perf_mem_data_src {
1220  	__u64 val;
1221  	struct {
1222  		__u64	mem_rsvd:21,
1223  			mem_blk:3,	/* access blocked */
1224  			mem_snoopx:2,	/* snoop mode, ext */
1225  			mem_remote:1,   /* remote */
1226  			mem_lvl_num:4,	/* memory hierarchy level number */
1227  			mem_dtlb:7,	/* tlb access */
1228  			mem_lock:2,	/* lock instr */
1229  			mem_snoop:5,	/* snoop mode */
1230  			mem_lvl:14,	/* memory hierarchy level */
1231  			mem_op:5;	/* type of opcode */
1232  	};
1233  };
1234  #else
1235  #error "Unknown endianness"
1236  #endif
1237  
1238  /* type of opcode (load/store/prefetch,code) */
1239  #define PERF_MEM_OP_NA		0x01 /* not available */
1240  #define PERF_MEM_OP_LOAD	0x02 /* load instruction */
1241  #define PERF_MEM_OP_STORE	0x04 /* store instruction */
1242  #define PERF_MEM_OP_PFETCH	0x08 /* prefetch */
1243  #define PERF_MEM_OP_EXEC	0x10 /* code (execution) */
1244  #define PERF_MEM_OP_SHIFT	0
1245  
1246  /* memory hierarchy (memory level, hit or miss) */
1247  #define PERF_MEM_LVL_NA		0x01  /* not available */
1248  #define PERF_MEM_LVL_HIT	0x02  /* hit level */
1249  #define PERF_MEM_LVL_MISS	0x04  /* miss level  */
1250  #define PERF_MEM_LVL_L1		0x08  /* L1 */
1251  #define PERF_MEM_LVL_LFB	0x10  /* Line Fill Buffer */
1252  #define PERF_MEM_LVL_L2		0x20  /* L2 */
1253  #define PERF_MEM_LVL_L3		0x40  /* L3 */
1254  #define PERF_MEM_LVL_LOC_RAM	0x80  /* Local DRAM */
1255  #define PERF_MEM_LVL_REM_RAM1	0x100 /* Remote DRAM (1 hop) */
1256  #define PERF_MEM_LVL_REM_RAM2	0x200 /* Remote DRAM (2 hops) */
1257  #define PERF_MEM_LVL_REM_CCE1	0x400 /* Remote Cache (1 hop) */
1258  #define PERF_MEM_LVL_REM_CCE2	0x800 /* Remote Cache (2 hops) */
1259  #define PERF_MEM_LVL_IO		0x1000 /* I/O memory */
1260  #define PERF_MEM_LVL_UNC	0x2000 /* Uncached memory */
1261  #define PERF_MEM_LVL_SHIFT	5
1262  
1263  #define PERF_MEM_REMOTE_REMOTE	0x01  /* Remote */
1264  #define PERF_MEM_REMOTE_SHIFT	37
1265  
1266  #define PERF_MEM_LVLNUM_L1	0x01 /* L1 */
1267  #define PERF_MEM_LVLNUM_L2	0x02 /* L2 */
1268  #define PERF_MEM_LVLNUM_L3	0x03 /* L3 */
1269  #define PERF_MEM_LVLNUM_L4	0x04 /* L4 */
1270  /* 5-0xa available */
1271  #define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */
1272  #define PERF_MEM_LVLNUM_LFB	0x0c /* LFB */
1273  #define PERF_MEM_LVLNUM_RAM	0x0d /* RAM */
1274  #define PERF_MEM_LVLNUM_PMEM	0x0e /* PMEM */
1275  #define PERF_MEM_LVLNUM_NA	0x0f /* N/A */
1276  
1277  #define PERF_MEM_LVLNUM_SHIFT	33
1278  
1279  /* snoop mode */
1280  #define PERF_MEM_SNOOP_NA	0x01 /* not available */
1281  #define PERF_MEM_SNOOP_NONE	0x02 /* no snoop */
1282  #define PERF_MEM_SNOOP_HIT	0x04 /* snoop hit */
1283  #define PERF_MEM_SNOOP_MISS	0x08 /* snoop miss */
1284  #define PERF_MEM_SNOOP_HITM	0x10 /* snoop hit modified */
1285  #define PERF_MEM_SNOOP_SHIFT	19
1286  
1287  #define PERF_MEM_SNOOPX_FWD	0x01 /* forward */
1288  /* 1 free */
1289  #define PERF_MEM_SNOOPX_SHIFT  38
1290  
1291  /* locked instruction */
1292  #define PERF_MEM_LOCK_NA	0x01 /* not available */
1293  #define PERF_MEM_LOCK_LOCKED	0x02 /* locked transaction */
1294  #define PERF_MEM_LOCK_SHIFT	24
1295  
1296  /* TLB access */
1297  #define PERF_MEM_TLB_NA		0x01 /* not available */
1298  #define PERF_MEM_TLB_HIT	0x02 /* hit level */
1299  #define PERF_MEM_TLB_MISS	0x04 /* miss level */
1300  #define PERF_MEM_TLB_L1		0x08 /* L1 */
1301  #define PERF_MEM_TLB_L2		0x10 /* L2 */
1302  #define PERF_MEM_TLB_WK		0x20 /* Hardware Walker*/
1303  #define PERF_MEM_TLB_OS		0x40 /* OS fault handler */
1304  #define PERF_MEM_TLB_SHIFT	26
1305  
1306  /* Access blocked */
1307  #define PERF_MEM_BLK_NA		0x01 /* not available */
1308  #define PERF_MEM_BLK_DATA	0x02 /* data could not be forwarded */
1309  #define PERF_MEM_BLK_ADDR	0x04 /* address conflict */
1310  #define PERF_MEM_BLK_SHIFT	40
1311  
1312  #define PERF_MEM_S(a, s) \
1313  	(((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT)
1314  
1315  /*
1316   * single taken branch record layout:
1317   *
1318   *      from: source instruction (may not always be a branch insn)
1319   *        to: branch target
1320   *   mispred: branch target was mispredicted
1321   * predicted: branch target was predicted
1322   *
1323   * support for mispred, predicted is optional. In case it
1324   * is not supported mispred = predicted = 0.
1325   *
1326   *     in_tx: running in a hardware transaction
1327   *     abort: aborting a hardware transaction
1328   *    cycles: cycles from last branch (or 0 if not supported)
1329   *      type: branch type
1330   */
1331  struct perf_branch_entry {
1332  	__u64	from;
1333  	__u64	to;
1334  	__u64	mispred:1,  /* target mispredicted */
1335  		predicted:1,/* target predicted */
1336  		in_tx:1,    /* in transaction */
1337  		abort:1,    /* transaction abort */
1338  		cycles:16,  /* cycle count to last branch */
1339  		type:4,     /* branch type */
1340  		reserved:40;
1341  };
1342  
1343  union perf_sample_weight {
1344  	__u64		full;
1345  #if defined(__LITTLE_ENDIAN_BITFIELD)
1346  	struct {
1347  		__u32	var1_dw;
1348  		__u16	var2_w;
1349  		__u16	var3_w;
1350  	};
1351  #elif defined(__BIG_ENDIAN_BITFIELD)
1352  	struct {
1353  		__u16	var3_w;
1354  		__u16	var2_w;
1355  		__u32	var1_dw;
1356  	};
1357  #else
1358  #error "Unknown endianness"
1359  #endif
1360  };
1361  
1362  #endif /* _UAPI_LINUX_PERF_EVENT_H */
1363