| /tools/testing/selftests/bpf/progs/ |
| D | btf_dump_test_case_namespacing.c | 24 enum E { enum
28 typedef enum E E; typedef
59 enum E _5; in f()
60 E _6; in f()
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| D | test_global_func9.c | 22 enum E { enum
52 __noinline int qux(enum E *e) in qux()
114 enum E e = E_ITEM; in test_cls()
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| D | btf_dump_test_case_syntax.c | 17 E = 0, enumerator
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| /tools/perf/arch/arm64/util/ |
| D | mem-events.c | 5 #define E(t, n, s) { .tag = t, .name = n, .sysfs_name = s } macro
8 E("spe-load", "arm_spe_0/ts_enable=1,load_filter=1,store_filter=0,min_latency=%u/", "arm_spe_0"),
9 E("spe-store", "arm_spe_0/ts_enable=1,load_filter=0,store_filter=1/", "arm_spe_0"),
10 E("spe-ldst", "arm_spe_0/ts_enable=1,load_filter=1,store_filter=1,min_latency=%u/", "arm_spe_0"),
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| /tools/perf/arch/x86/util/ |
| D | mem-events.c | 13 #define E(t, n, s) { .tag = t, .name = n, .sysfs_name = s } macro
16 E("ldlat-loads", "%s/mem-loads,ldlat=%u/P", "%s/events/mem-loads"),
17 E("ldlat-stores", "%s/mem-stores/P", "%s/events/mem-stores"),
18 E(NULL, NULL, NULL),
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| /tools/perf/pmu-events/arch/x86/ |
| D | mapfile.csv | 18 GenuineIntel-6-3E,v19,ivytown,core
22 GenuineIntel-6-1E,v2,nehalemep,core
25 GenuineIntel-6-2E,v2,nehalemex,core
26 GenuineIntel-6-[4589]E,v24,skylake,core
38 GenuineIntel-6-7E,v1,icelake,core
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| /tools/testing/selftests/powerpc/benchmarks/ |
| D | futex_bench.c | 18 #define futex(A, B, C, D, E, F) syscall(__NR_futex, A, B, C, D, E, F) argument
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| /tools/memory-model/Documentation/ |
| D | references.txt | 52 o Shaked Flur, Kathryn E. Gray, Christopher Pulte, Susmit
60 Luc Maranget, Kathryn E. Gray, Ali Sezgin, Mark Batty, and Peter
77 Lustig, Luc Maranget, Paul E. McKenney, Andrea Parri, Nicholas
83 Lustig, Luc Maranget, Paul E. McKenney, Andrea Parri, Nicholas
88 o Jade Alglave, Luc Maranget, Paul E. McKenney, Andrea Parri, and
95 o Jade Alglave, Luc Maranget, Paul E. McKenney, Andrea Parri, and
99 o Jade Alglave, Luc Maranget, Paul E. McKenney, Andrea Parri, and
103 o Jade Alglave, Luc Maranget, Paul E. McKenney, Andrea Parri, and
129 o Paul E. McKenney, Ulrich Weigand, Andrea Parri, and Boqun
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| D | explanation.txt | 835 defined to link memory access events E and F whenever:
837 E and F are both stores on the same CPU and an smp_wmb() fence
841 where either X = E or else E ->rf X; or
844 order, where either X = E or else E ->rf X.
1354 features of strong fences. It links two events E and F whenever some
1355 store is coherence-later than E and propagates to every CPU and to RAM
1356 before F executes. The formal definition requires that E be linked to
1361 Consider first the case where E is a store (implying that the sequence
1365 E ->coe W ->cumul-fence* X ->rfe? Y ->strong-fence Z ->hb* F,
1374 Thus W, which comes later than E in the coherence order, will
[all …]
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| D | litmus-tests.txt | 781 10 // E
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| /tools/testing/selftests/drivers/net/mlxsw/ |
| D | devlink_trap_control.sh | 220 $MZ $h1 -c 1 -a own -b 01:00:5E:00:00:01 \
228 "igmp_v1_report" $MZ $h1 -c 1 -a own -b 01:00:5E:00:00:01 \
236 "igmp_v2_report" $MZ $h1 -c 1 -a own -b 01:00:5E:00:00:01 \
244 "igmp_v3_report" $MZ $h1 -c 1 -a own -b 01:00:5E:00:00:01 \
252 "igmp_v2_leave" $MZ $h1 -c 1 -a own -b 01:00:5E:00:00:02 \
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| /tools/perf/util/ |
| D | mem-events.c | 20 #define E(t, n, s) { .tag = t, .name = n, .sysfs_name = s } macro
23 E("ldlat-loads", "cpu/mem-loads,ldlat=%u/P", "cpu/events/mem-loads"),
24 E("ldlat-stores", "cpu/mem-stores/P", "cpu/events/mem-stores"),
25 E(NULL, NULL, NULL),
27 #undef E
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| /tools/perf/Documentation/ |
| D | perf.data-directory-format.txt | 52 Using CPUID GenuineIntel-6-8E-A
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| D | perf-top.txt | 45 -E <entries>::
299 E.g.:
364 [E]::
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| D | perf-script.txt | 260 PERF_RECORD_MISC_COMM_EXEC E
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| /tools/perf/pmu-events/ |
| D | README | 131 CPUID == 'GenuineIntel-6-2E' (on x86).
|