1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright 2018 NXP
3
4 #include <linux/clk.h>
5 #include <linux/device.h>
6 #include <linux/interrupt.h>
7 #include <linux/kobject.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/of_address.h>
12 #include <linux/of_irq.h>
13 #include <linux/of_platform.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regmap.h>
16 #include <linux/sysfs.h>
17 #include <linux/types.h>
18 #include <sound/dmaengine_pcm.h>
19 #include <sound/pcm.h>
20 #include <sound/soc.h>
21 #include <sound/tlv.h>
22 #include <sound/core.h>
23
24 #include "fsl_micfil.h"
25 #include "imx-pcm.h"
26
27 #define FSL_MICFIL_RATES SNDRV_PCM_RATE_8000_48000
28 #define FSL_MICFIL_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
29
30 struct fsl_micfil {
31 struct platform_device *pdev;
32 struct regmap *regmap;
33 const struct fsl_micfil_soc_data *soc;
34 struct clk *busclk;
35 struct clk *mclk;
36 struct snd_dmaengine_dai_dma_data dma_params_rx;
37 unsigned int dataline;
38 char name[32];
39 int irq[MICFIL_IRQ_LINES];
40 unsigned int mclk_streams;
41 int quality; /*QUALITY 2-0 bits */
42 bool slave_mode;
43 int channel_gain[8];
44 };
45
46 struct fsl_micfil_soc_data {
47 unsigned int fifos;
48 unsigned int fifo_depth;
49 unsigned int dataline;
50 bool imx;
51 };
52
53 static struct fsl_micfil_soc_data fsl_micfil_imx8mm = {
54 .imx = true,
55 .fifos = 8,
56 .fifo_depth = 8,
57 .dataline = 0xf,
58 };
59
60 static const struct of_device_id fsl_micfil_dt_ids[] = {
61 { .compatible = "fsl,imx8mm-micfil", .data = &fsl_micfil_imx8mm },
62 {}
63 };
64 MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids);
65
66 /* Table 5. Quality Modes
67 * Medium 0 0 0
68 * High 0 0 1
69 * Very Low 2 1 0 0
70 * Very Low 1 1 0 1
71 * Very Low 0 1 1 0
72 * Low 1 1 1
73 */
74 static const char * const micfil_quality_select_texts[] = {
75 "Medium", "High",
76 "N/A", "N/A",
77 "VLow2", "VLow1",
78 "VLow0", "Low",
79 };
80
81 static const struct soc_enum fsl_micfil_quality_enum =
82 SOC_ENUM_SINGLE(REG_MICFIL_CTRL2,
83 MICFIL_CTRL2_QSEL_SHIFT,
84 ARRAY_SIZE(micfil_quality_select_texts),
85 micfil_quality_select_texts);
86
87 static DECLARE_TLV_DB_SCALE(gain_tlv, 0, 100, 0);
88
89 static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = {
90 SOC_SINGLE_SX_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL,
91 MICFIL_OUTGAIN_CHX_SHIFT(0), 0x8, 0xF, gain_tlv),
92 SOC_SINGLE_SX_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL,
93 MICFIL_OUTGAIN_CHX_SHIFT(1), 0x8, 0xF, gain_tlv),
94 SOC_SINGLE_SX_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL,
95 MICFIL_OUTGAIN_CHX_SHIFT(2), 0x8, 0xF, gain_tlv),
96 SOC_SINGLE_SX_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL,
97 MICFIL_OUTGAIN_CHX_SHIFT(3), 0x8, 0xF, gain_tlv),
98 SOC_SINGLE_SX_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL,
99 MICFIL_OUTGAIN_CHX_SHIFT(4), 0x8, 0xF, gain_tlv),
100 SOC_SINGLE_SX_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL,
101 MICFIL_OUTGAIN_CHX_SHIFT(5), 0x8, 0xF, gain_tlv),
102 SOC_SINGLE_SX_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL,
103 MICFIL_OUTGAIN_CHX_SHIFT(6), 0x8, 0xF, gain_tlv),
104 SOC_SINGLE_SX_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL,
105 MICFIL_OUTGAIN_CHX_SHIFT(7), 0x8, 0xF, gain_tlv),
106 SOC_ENUM_EXT("MICFIL Quality Select",
107 fsl_micfil_quality_enum,
108 snd_soc_get_enum_double, snd_soc_put_enum_double),
109 };
110
get_pdm_clk(struct fsl_micfil * micfil,unsigned int rate)111 static inline int get_pdm_clk(struct fsl_micfil *micfil,
112 unsigned int rate)
113 {
114 u32 ctrl2_reg;
115 int qsel, osr;
116 int bclk;
117
118 regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
119 osr = 16 - ((ctrl2_reg & MICFIL_CTRL2_CICOSR_MASK)
120 >> MICFIL_CTRL2_CICOSR_SHIFT);
121
122 regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
123 qsel = ctrl2_reg & MICFIL_CTRL2_QSEL_MASK;
124
125 switch (qsel) {
126 case MICFIL_HIGH_QUALITY:
127 bclk = rate * 8 * osr / 2; /* kfactor = 0.5 */
128 break;
129 case MICFIL_MEDIUM_QUALITY:
130 case MICFIL_VLOW0_QUALITY:
131 bclk = rate * 4 * osr * 1; /* kfactor = 1 */
132 break;
133 case MICFIL_LOW_QUALITY:
134 case MICFIL_VLOW1_QUALITY:
135 bclk = rate * 2 * osr * 2; /* kfactor = 2 */
136 break;
137 case MICFIL_VLOW2_QUALITY:
138 bclk = rate * osr * 4; /* kfactor = 4 */
139 break;
140 default:
141 dev_err(&micfil->pdev->dev,
142 "Please make sure you select a valid quality.\n");
143 bclk = -1;
144 break;
145 }
146
147 return bclk;
148 }
149
get_clk_div(struct fsl_micfil * micfil,unsigned int rate)150 static inline int get_clk_div(struct fsl_micfil *micfil,
151 unsigned int rate)
152 {
153 u32 ctrl2_reg;
154 long mclk_rate;
155 int clk_div;
156
157 regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
158
159 mclk_rate = clk_get_rate(micfil->mclk);
160
161 clk_div = mclk_rate / (get_pdm_clk(micfil, rate) * 2);
162
163 return clk_div;
164 }
165
166 /* The SRES is a self-negated bit which provides the CPU with the
167 * capability to initialize the PDM Interface module through the
168 * slave-bus interface. This bit always reads as zero, and this
169 * bit is only effective when MDIS is cleared
170 */
fsl_micfil_reset(struct device * dev)171 static int fsl_micfil_reset(struct device *dev)
172 {
173 struct fsl_micfil *micfil = dev_get_drvdata(dev);
174 int ret;
175
176 ret = regmap_update_bits(micfil->regmap,
177 REG_MICFIL_CTRL1,
178 MICFIL_CTRL1_MDIS_MASK,
179 0);
180 if (ret) {
181 dev_err(dev, "failed to clear MDIS bit %d\n", ret);
182 return ret;
183 }
184
185 ret = regmap_update_bits(micfil->regmap,
186 REG_MICFIL_CTRL1,
187 MICFIL_CTRL1_SRES_MASK,
188 MICFIL_CTRL1_SRES);
189 if (ret) {
190 dev_err(dev, "failed to reset MICFIL: %d\n", ret);
191 return ret;
192 }
193
194 /*
195 * SRES is self-cleared bit, but REG_MICFIL_CTRL1 is defined
196 * as non-volatile register, so SRES still remain in regmap
197 * cache after set, that every update of REG_MICFIL_CTRL1,
198 * software reset happens. so clear it explicitly.
199 */
200 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
201 MICFIL_CTRL1_SRES);
202 if (ret)
203 return ret;
204
205 /*
206 * Set SRES should clear CHnF flags, But even add delay here
207 * the CHnF may not be cleared sometimes, so clear CHnF explicitly.
208 */
209 ret = regmap_write_bits(micfil->regmap, REG_MICFIL_STAT, 0xFF, 0xFF);
210 if (ret)
211 return ret;
212
213 return 0;
214 }
215
fsl_micfil_set_mclk_rate(struct fsl_micfil * micfil,unsigned int freq)216 static int fsl_micfil_set_mclk_rate(struct fsl_micfil *micfil,
217 unsigned int freq)
218 {
219 struct device *dev = &micfil->pdev->dev;
220 int ret;
221
222 clk_disable_unprepare(micfil->mclk);
223
224 ret = clk_set_rate(micfil->mclk, freq * 1024);
225 if (ret)
226 dev_warn(dev, "failed to set rate (%u): %d\n",
227 freq * 1024, ret);
228
229 clk_prepare_enable(micfil->mclk);
230
231 return ret;
232 }
233
fsl_micfil_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)234 static int fsl_micfil_startup(struct snd_pcm_substream *substream,
235 struct snd_soc_dai *dai)
236 {
237 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
238
239 if (!micfil) {
240 dev_err(dai->dev, "micfil dai priv_data not set\n");
241 return -EINVAL;
242 }
243
244 return 0;
245 }
246
fsl_micfil_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)247 static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
248 struct snd_soc_dai *dai)
249 {
250 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
251 struct device *dev = &micfil->pdev->dev;
252 int ret;
253
254 switch (cmd) {
255 case SNDRV_PCM_TRIGGER_START:
256 case SNDRV_PCM_TRIGGER_RESUME:
257 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
258 ret = fsl_micfil_reset(dev);
259 if (ret) {
260 dev_err(dev, "failed to soft reset\n");
261 return ret;
262 }
263
264 /* DMA Interrupt Selection - DISEL bits
265 * 00 - DMA and IRQ disabled
266 * 01 - DMA req enabled
267 * 10 - IRQ enabled
268 * 11 - reserved
269 */
270 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
271 MICFIL_CTRL1_DISEL_MASK,
272 (1 << MICFIL_CTRL1_DISEL_SHIFT));
273 if (ret) {
274 dev_err(dev, "failed to update DISEL bits\n");
275 return ret;
276 }
277
278 /* Enable the module */
279 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
280 MICFIL_CTRL1_PDMIEN_MASK,
281 MICFIL_CTRL1_PDMIEN);
282 if (ret) {
283 dev_err(dev, "failed to enable the module\n");
284 return ret;
285 }
286
287 break;
288 case SNDRV_PCM_TRIGGER_STOP:
289 case SNDRV_PCM_TRIGGER_SUSPEND:
290 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
291 /* Disable the module */
292 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
293 MICFIL_CTRL1_PDMIEN_MASK,
294 0);
295 if (ret) {
296 dev_err(dev, "failed to enable the module\n");
297 return ret;
298 }
299
300 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
301 MICFIL_CTRL1_DISEL_MASK,
302 (0 << MICFIL_CTRL1_DISEL_SHIFT));
303 if (ret) {
304 dev_err(dev, "failed to update DISEL bits\n");
305 return ret;
306 }
307 break;
308 default:
309 return -EINVAL;
310 }
311 return 0;
312 }
313
fsl_set_clock_params(struct device * dev,unsigned int rate)314 static int fsl_set_clock_params(struct device *dev, unsigned int rate)
315 {
316 struct fsl_micfil *micfil = dev_get_drvdata(dev);
317 int clk_div;
318 int ret;
319
320 ret = fsl_micfil_set_mclk_rate(micfil, rate);
321 if (ret < 0)
322 dev_err(dev, "failed to set mclk[%lu] to rate %u\n",
323 clk_get_rate(micfil->mclk), rate);
324
325 /* set CICOSR */
326 ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
327 MICFIL_CTRL2_CICOSR_MASK,
328 MICFIL_CTRL2_OSR_DEFAULT);
329 if (ret)
330 dev_err(dev, "failed to set CICOSR in reg 0x%X\n",
331 REG_MICFIL_CTRL2);
332
333 /* set CLK_DIV */
334 clk_div = get_clk_div(micfil, rate);
335 if (clk_div < 0)
336 ret = -EINVAL;
337
338 ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
339 MICFIL_CTRL2_CLKDIV_MASK, clk_div);
340 if (ret)
341 dev_err(dev, "failed to set CLKDIV in reg 0x%X\n",
342 REG_MICFIL_CTRL2);
343
344 return ret;
345 }
346
fsl_micfil_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)347 static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
348 struct snd_pcm_hw_params *params,
349 struct snd_soc_dai *dai)
350 {
351 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
352 unsigned int channels = params_channels(params);
353 unsigned int rate = params_rate(params);
354 struct device *dev = &micfil->pdev->dev;
355 int ret;
356
357 /* 1. Disable the module */
358 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
359 MICFIL_CTRL1_PDMIEN_MASK, 0);
360 if (ret) {
361 dev_err(dev, "failed to disable the module\n");
362 return ret;
363 }
364
365 /* enable channels */
366 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
367 0xFF, ((1 << channels) - 1));
368 if (ret) {
369 dev_err(dev, "failed to enable channels %d, reg 0x%X\n", ret,
370 REG_MICFIL_CTRL1);
371 return ret;
372 }
373
374 ret = fsl_set_clock_params(dev, rate);
375 if (ret < 0) {
376 dev_err(dev, "Failed to set clock parameters [%d]\n", ret);
377 return ret;
378 }
379
380 micfil->dma_params_rx.maxburst = channels * MICFIL_DMA_MAXBURST_RX;
381
382 return 0;
383 }
384
fsl_micfil_set_dai_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)385 static int fsl_micfil_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
386 unsigned int freq, int dir)
387 {
388 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
389 struct device *dev = &micfil->pdev->dev;
390
391 int ret;
392
393 if (!freq)
394 return 0;
395
396 ret = fsl_micfil_set_mclk_rate(micfil, freq);
397 if (ret < 0)
398 dev_err(dev, "failed to set mclk[%lu] to rate %u\n",
399 clk_get_rate(micfil->mclk), freq);
400
401 return ret;
402 }
403
404 static const struct snd_soc_dai_ops fsl_micfil_dai_ops = {
405 .startup = fsl_micfil_startup,
406 .trigger = fsl_micfil_trigger,
407 .hw_params = fsl_micfil_hw_params,
408 .set_sysclk = fsl_micfil_set_dai_sysclk,
409 };
410
fsl_micfil_dai_probe(struct snd_soc_dai * cpu_dai)411 static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
412 {
413 struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev);
414 struct device *dev = cpu_dai->dev;
415 unsigned int val;
416 int ret;
417 int i;
418
419 /* set qsel to medium */
420 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
421 MICFIL_CTRL2_QSEL_MASK, MICFIL_MEDIUM_QUALITY);
422 if (ret) {
423 dev_err(dev, "failed to set quality mode bits, reg 0x%X\n",
424 REG_MICFIL_CTRL2);
425 return ret;
426 }
427
428 /* set default gain to max_gain */
429 regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x77777777);
430 for (i = 0; i < 8; i++)
431 micfil->channel_gain[i] = 0xF;
432
433 snd_soc_dai_init_dma_data(cpu_dai, NULL,
434 &micfil->dma_params_rx);
435
436 /* FIFO Watermark Control - FIFOWMK*/
437 val = MICFIL_FIFO_CTRL_FIFOWMK(micfil->soc->fifo_depth) - 1;
438 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL,
439 MICFIL_FIFO_CTRL_FIFOWMK_MASK,
440 val);
441 if (ret) {
442 dev_err(dev, "failed to set FIFOWMK\n");
443 return ret;
444 }
445
446 return 0;
447 }
448
449 static struct snd_soc_dai_driver fsl_micfil_dai = {
450 .probe = fsl_micfil_dai_probe,
451 .capture = {
452 .stream_name = "CPU-Capture",
453 .channels_min = 1,
454 .channels_max = 8,
455 .rates = FSL_MICFIL_RATES,
456 .formats = FSL_MICFIL_FORMATS,
457 },
458 .ops = &fsl_micfil_dai_ops,
459 };
460
461 static const struct snd_soc_component_driver fsl_micfil_component = {
462 .name = "fsl-micfil-dai",
463 .controls = fsl_micfil_snd_controls,
464 .num_controls = ARRAY_SIZE(fsl_micfil_snd_controls),
465
466 };
467
468 /* REGMAP */
469 static const struct reg_default fsl_micfil_reg_defaults[] = {
470 {REG_MICFIL_CTRL1, 0x00000000},
471 {REG_MICFIL_CTRL2, 0x00000000},
472 {REG_MICFIL_STAT, 0x00000000},
473 {REG_MICFIL_FIFO_CTRL, 0x00000007},
474 {REG_MICFIL_FIFO_STAT, 0x00000000},
475 {REG_MICFIL_DATACH0, 0x00000000},
476 {REG_MICFIL_DATACH1, 0x00000000},
477 {REG_MICFIL_DATACH2, 0x00000000},
478 {REG_MICFIL_DATACH3, 0x00000000},
479 {REG_MICFIL_DATACH4, 0x00000000},
480 {REG_MICFIL_DATACH5, 0x00000000},
481 {REG_MICFIL_DATACH6, 0x00000000},
482 {REG_MICFIL_DATACH7, 0x00000000},
483 {REG_MICFIL_DC_CTRL, 0x00000000},
484 {REG_MICFIL_OUT_CTRL, 0x00000000},
485 {REG_MICFIL_OUT_STAT, 0x00000000},
486 {REG_MICFIL_VAD0_CTRL1, 0x00000000},
487 {REG_MICFIL_VAD0_CTRL2, 0x000A0000},
488 {REG_MICFIL_VAD0_STAT, 0x00000000},
489 {REG_MICFIL_VAD0_SCONFIG, 0x00000000},
490 {REG_MICFIL_VAD0_NCONFIG, 0x80000000},
491 {REG_MICFIL_VAD0_NDATA, 0x00000000},
492 {REG_MICFIL_VAD0_ZCD, 0x00000004},
493 };
494
fsl_micfil_readable_reg(struct device * dev,unsigned int reg)495 static bool fsl_micfil_readable_reg(struct device *dev, unsigned int reg)
496 {
497 switch (reg) {
498 case REG_MICFIL_CTRL1:
499 case REG_MICFIL_CTRL2:
500 case REG_MICFIL_STAT:
501 case REG_MICFIL_FIFO_CTRL:
502 case REG_MICFIL_FIFO_STAT:
503 case REG_MICFIL_DATACH0:
504 case REG_MICFIL_DATACH1:
505 case REG_MICFIL_DATACH2:
506 case REG_MICFIL_DATACH3:
507 case REG_MICFIL_DATACH4:
508 case REG_MICFIL_DATACH5:
509 case REG_MICFIL_DATACH6:
510 case REG_MICFIL_DATACH7:
511 case REG_MICFIL_DC_CTRL:
512 case REG_MICFIL_OUT_CTRL:
513 case REG_MICFIL_OUT_STAT:
514 case REG_MICFIL_VAD0_CTRL1:
515 case REG_MICFIL_VAD0_CTRL2:
516 case REG_MICFIL_VAD0_STAT:
517 case REG_MICFIL_VAD0_SCONFIG:
518 case REG_MICFIL_VAD0_NCONFIG:
519 case REG_MICFIL_VAD0_NDATA:
520 case REG_MICFIL_VAD0_ZCD:
521 return true;
522 default:
523 return false;
524 }
525 }
526
fsl_micfil_writeable_reg(struct device * dev,unsigned int reg)527 static bool fsl_micfil_writeable_reg(struct device *dev, unsigned int reg)
528 {
529 switch (reg) {
530 case REG_MICFIL_CTRL1:
531 case REG_MICFIL_CTRL2:
532 case REG_MICFIL_STAT: /* Write 1 to Clear */
533 case REG_MICFIL_FIFO_CTRL:
534 case REG_MICFIL_FIFO_STAT: /* Write 1 to Clear */
535 case REG_MICFIL_DC_CTRL:
536 case REG_MICFIL_OUT_CTRL:
537 case REG_MICFIL_OUT_STAT: /* Write 1 to Clear */
538 case REG_MICFIL_VAD0_CTRL1:
539 case REG_MICFIL_VAD0_CTRL2:
540 case REG_MICFIL_VAD0_STAT: /* Write 1 to Clear */
541 case REG_MICFIL_VAD0_SCONFIG:
542 case REG_MICFIL_VAD0_NCONFIG:
543 case REG_MICFIL_VAD0_ZCD:
544 return true;
545 default:
546 return false;
547 }
548 }
549
fsl_micfil_volatile_reg(struct device * dev,unsigned int reg)550 static bool fsl_micfil_volatile_reg(struct device *dev, unsigned int reg)
551 {
552 switch (reg) {
553 case REG_MICFIL_STAT:
554 case REG_MICFIL_DATACH0:
555 case REG_MICFIL_DATACH1:
556 case REG_MICFIL_DATACH2:
557 case REG_MICFIL_DATACH3:
558 case REG_MICFIL_DATACH4:
559 case REG_MICFIL_DATACH5:
560 case REG_MICFIL_DATACH6:
561 case REG_MICFIL_DATACH7:
562 case REG_MICFIL_VAD0_STAT:
563 case REG_MICFIL_VAD0_NDATA:
564 return true;
565 default:
566 return false;
567 }
568 }
569
570 static const struct regmap_config fsl_micfil_regmap_config = {
571 .reg_bits = 32,
572 .reg_stride = 4,
573 .val_bits = 32,
574
575 .max_register = REG_MICFIL_VAD0_ZCD,
576 .reg_defaults = fsl_micfil_reg_defaults,
577 .num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults),
578 .readable_reg = fsl_micfil_readable_reg,
579 .volatile_reg = fsl_micfil_volatile_reg,
580 .writeable_reg = fsl_micfil_writeable_reg,
581 .cache_type = REGCACHE_RBTREE,
582 };
583
584 /* END OF REGMAP */
585
micfil_isr(int irq,void * devid)586 static irqreturn_t micfil_isr(int irq, void *devid)
587 {
588 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
589 struct platform_device *pdev = micfil->pdev;
590 u32 stat_reg;
591 u32 fifo_stat_reg;
592 u32 ctrl1_reg;
593 bool dma_enabled;
594 int i;
595
596 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
597 regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg);
598 regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg);
599
600 dma_enabled = MICFIL_DMA_ENABLED(ctrl1_reg);
601
602 /* Channel 0-7 Output Data Flags */
603 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) {
604 if (stat_reg & MICFIL_STAT_CHXF_MASK(i))
605 dev_dbg(&pdev->dev,
606 "Data available in Data Channel %d\n", i);
607 /* if DMA is not enabled, field must be written with 1
608 * to clear
609 */
610 if (!dma_enabled)
611 regmap_write_bits(micfil->regmap,
612 REG_MICFIL_STAT,
613 MICFIL_STAT_CHXF_MASK(i),
614 1);
615 }
616
617 for (i = 0; i < MICFIL_FIFO_NUM; i++) {
618 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER_MASK(i))
619 dev_dbg(&pdev->dev,
620 "FIFO Overflow Exception flag for channel %d\n",
621 i);
622
623 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER_MASK(i))
624 dev_dbg(&pdev->dev,
625 "FIFO Underflow Exception flag for channel %d\n",
626 i);
627 }
628
629 return IRQ_HANDLED;
630 }
631
micfil_err_isr(int irq,void * devid)632 static irqreturn_t micfil_err_isr(int irq, void *devid)
633 {
634 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
635 struct platform_device *pdev = micfil->pdev;
636 u32 stat_reg;
637
638 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
639
640 if (stat_reg & MICFIL_STAT_BSY_FIL_MASK)
641 dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n");
642
643 if (stat_reg & MICFIL_STAT_FIR_RDY_MASK)
644 dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n");
645
646 if (stat_reg & MICFIL_STAT_LOWFREQF_MASK) {
647 dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n");
648 regmap_write_bits(micfil->regmap, REG_MICFIL_STAT,
649 MICFIL_STAT_LOWFREQF_MASK, 1);
650 }
651
652 return IRQ_HANDLED;
653 }
654
fsl_micfil_probe(struct platform_device * pdev)655 static int fsl_micfil_probe(struct platform_device *pdev)
656 {
657 struct device_node *np = pdev->dev.of_node;
658 struct fsl_micfil *micfil;
659 struct resource *res;
660 void __iomem *regs;
661 int ret, i;
662 unsigned long irqflag = 0;
663
664 micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL);
665 if (!micfil)
666 return -ENOMEM;
667
668 micfil->pdev = pdev;
669 strncpy(micfil->name, np->name, sizeof(micfil->name) - 1);
670
671 micfil->soc = of_device_get_match_data(&pdev->dev);
672
673 /* ipg_clk is used to control the registers
674 * ipg_clk_app is used to operate the filter
675 */
676 micfil->mclk = devm_clk_get(&pdev->dev, "ipg_clk_app");
677 if (IS_ERR(micfil->mclk)) {
678 dev_err(&pdev->dev, "failed to get core clock: %ld\n",
679 PTR_ERR(micfil->mclk));
680 return PTR_ERR(micfil->mclk);
681 }
682
683 micfil->busclk = devm_clk_get(&pdev->dev, "ipg_clk");
684 if (IS_ERR(micfil->busclk)) {
685 dev_err(&pdev->dev, "failed to get ipg clock: %ld\n",
686 PTR_ERR(micfil->busclk));
687 return PTR_ERR(micfil->busclk);
688 }
689
690 /* init regmap */
691 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
692 if (IS_ERR(regs))
693 return PTR_ERR(regs);
694
695 micfil->regmap = devm_regmap_init_mmio(&pdev->dev,
696 regs,
697 &fsl_micfil_regmap_config);
698 if (IS_ERR(micfil->regmap)) {
699 dev_err(&pdev->dev, "failed to init MICFIL regmap: %ld\n",
700 PTR_ERR(micfil->regmap));
701 return PTR_ERR(micfil->regmap);
702 }
703
704 /* dataline mask for RX */
705 ret = of_property_read_u32_index(np,
706 "fsl,dataline",
707 0,
708 &micfil->dataline);
709 if (ret)
710 micfil->dataline = 1;
711
712 if (micfil->dataline & ~micfil->soc->dataline) {
713 dev_err(&pdev->dev, "dataline setting error, Mask is 0x%X\n",
714 micfil->soc->dataline);
715 return -EINVAL;
716 }
717
718 /* get IRQs */
719 for (i = 0; i < MICFIL_IRQ_LINES; i++) {
720 micfil->irq[i] = platform_get_irq(pdev, i);
721 dev_err(&pdev->dev, "GET IRQ: %d\n", micfil->irq[i]);
722 if (micfil->irq[i] < 0)
723 return micfil->irq[i];
724 }
725
726 if (of_property_read_bool(np, "fsl,shared-interrupt"))
727 irqflag = IRQF_SHARED;
728
729 /* Digital Microphone interface interrupt */
730 ret = devm_request_irq(&pdev->dev, micfil->irq[0],
731 micfil_isr, irqflag,
732 micfil->name, micfil);
733 if (ret) {
734 dev_err(&pdev->dev, "failed to claim mic interface irq %u\n",
735 micfil->irq[0]);
736 return ret;
737 }
738
739 /* Digital Microphone interface error interrupt */
740 ret = devm_request_irq(&pdev->dev, micfil->irq[1],
741 micfil_err_isr, irqflag,
742 micfil->name, micfil);
743 if (ret) {
744 dev_err(&pdev->dev, "failed to claim mic interface error irq %u\n",
745 micfil->irq[1]);
746 return ret;
747 }
748
749 micfil->dma_params_rx.chan_name = "rx";
750 micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0;
751 micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX;
752
753
754 platform_set_drvdata(pdev, micfil);
755
756 pm_runtime_enable(&pdev->dev);
757 regcache_cache_only(micfil->regmap, true);
758
759 /*
760 * Register platform component before registering cpu dai for there
761 * is not defer probe for platform component in snd_soc_add_pcm_runtime().
762 */
763 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
764 if (ret) {
765 dev_err(&pdev->dev, "failed to pcm register\n");
766 goto err_pm_disable;
767 }
768
769 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_micfil_component,
770 &fsl_micfil_dai, 1);
771 if (ret) {
772 dev_err(&pdev->dev, "failed to register component %s\n",
773 fsl_micfil_component.name);
774 goto err_pm_disable;
775 }
776
777 return ret;
778
779 err_pm_disable:
780 pm_runtime_disable(&pdev->dev);
781
782 return ret;
783 }
784
fsl_micfil_remove(struct platform_device * pdev)785 static void fsl_micfil_remove(struct platform_device *pdev)
786 {
787 pm_runtime_disable(&pdev->dev);
788 }
789
fsl_micfil_runtime_suspend(struct device * dev)790 static int __maybe_unused fsl_micfil_runtime_suspend(struct device *dev)
791 {
792 struct fsl_micfil *micfil = dev_get_drvdata(dev);
793
794 regcache_cache_only(micfil->regmap, true);
795
796 clk_disable_unprepare(micfil->mclk);
797 clk_disable_unprepare(micfil->busclk);
798
799 return 0;
800 }
801
fsl_micfil_runtime_resume(struct device * dev)802 static int __maybe_unused fsl_micfil_runtime_resume(struct device *dev)
803 {
804 struct fsl_micfil *micfil = dev_get_drvdata(dev);
805 int ret;
806
807 ret = clk_prepare_enable(micfil->busclk);
808 if (ret < 0)
809 return ret;
810
811 ret = clk_prepare_enable(micfil->mclk);
812 if (ret < 0) {
813 clk_disable_unprepare(micfil->busclk);
814 return ret;
815 }
816
817 regcache_cache_only(micfil->regmap, false);
818 regcache_mark_dirty(micfil->regmap);
819 regcache_sync(micfil->regmap);
820
821 return 0;
822 }
823
fsl_micfil_suspend(struct device * dev)824 static int __maybe_unused fsl_micfil_suspend(struct device *dev)
825 {
826 pm_runtime_force_suspend(dev);
827
828 return 0;
829 }
830
fsl_micfil_resume(struct device * dev)831 static int __maybe_unused fsl_micfil_resume(struct device *dev)
832 {
833 pm_runtime_force_resume(dev);
834
835 return 0;
836 }
837
838 static const struct dev_pm_ops fsl_micfil_pm_ops = {
839 SET_RUNTIME_PM_OPS(fsl_micfil_runtime_suspend,
840 fsl_micfil_runtime_resume,
841 NULL)
842 SET_SYSTEM_SLEEP_PM_OPS(fsl_micfil_suspend,
843 fsl_micfil_resume)
844 };
845
846 static struct platform_driver fsl_micfil_driver = {
847 .probe = fsl_micfil_probe,
848 .remove_new = fsl_micfil_remove,
849 .driver = {
850 .name = "fsl-micfil-dai",
851 .pm = &fsl_micfil_pm_ops,
852 .of_match_table = fsl_micfil_dt_ids,
853 },
854 };
855 module_platform_driver(fsl_micfil_driver);
856
857 MODULE_AUTHOR("Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>");
858 MODULE_DESCRIPTION("NXP PDM Microphone Interface (MICFIL) driver");
859 MODULE_LICENSE("GPL v2");
860