| /drivers/scsi/aacraid/ |
| D | aacraid.h | 1082 #define sa_readw(AEP, CSR) readl(&((AEP)->regs.sa->CSR)) argument
1083 #define sa_readl(AEP, CSR) readl(&((AEP)->regs.sa->CSR)) argument
1084 #define sa_writew(AEP, CSR, value) writew(value, &((AEP)->regs.sa->CSR)) argument
1085 #define sa_writel(AEP, CSR, value) writel(value, &((AEP)->regs.sa->CSR)) argument
1144 #define rx_readb(AEP, CSR) readb(&((AEP)->regs.rx->CSR)) argument
1145 #define rx_readl(AEP, CSR) readl(&((AEP)->regs.rx->CSR)) argument
1146 #define rx_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rx->CSR)) argument
1147 #define rx_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rx->CSR)) argument
1162 #define rkt_readb(AEP, CSR) readb(&((AEP)->regs.rkt->CSR)) argument
1163 #define rkt_readl(AEP, CSR) readl(&((AEP)->regs.rkt->CSR)) argument
[all …]
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| /drivers/dma/ |
| D | txx9dmac.c | 296 channel64_readl(dc, CSR)); in txx9dmac_dump_regs()
308 channel32_readl(dc, CSR)); in txx9dmac_dump_regs()
339 if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) { in txx9dmac_dostart()
349 channel64_writel(dc, CSR, 0xffffffff); in txx9dmac_dostart()
370 channel32_writel(dc, CSR, 0xffffffff); in txx9dmac_dostart()
480 desc->SAIR, desc->DAIR, desc->CCR, desc->CSR); in txx9dmac_dump_desc()
493 d->SAIR, d->DAIR, d->CCR, d->CSR); in txx9dmac_dump_desc()
519 channel_writel(dc, CSR, errors); in txx9dmac_handle_error()
545 csr = channel64_readl(dc, CSR); in txx9dmac_scan_descriptors()
546 channel64_writel(dc, CSR, csr); in txx9dmac_scan_descriptors()
[all …]
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| D | txx9dmac.h | 78 TXX9_DMA_REG32(CSR); /* Channel Status Register */
88 u32 CSR; member
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| /drivers/staging/qlge/ |
| D | qlge_mpi.c | 9 tmp = qlge_read32(qdev, CSR); in qlge_unpause_mpi_risc()
13 qlge_write32(qdev, CSR, CSR_CMD_CLR_PAUSE); in qlge_unpause_mpi_risc()
23 qlge_write32(qdev, CSR, CSR_CMD_SET_PAUSE); in qlge_pause_mpi_risc()
25 tmp = qlge_read32(qdev, CSR); in qlge_pause_mpi_risc()
39 qlge_write32(qdev, CSR, CSR_CMD_SET_RST); in qlge_hard_reset_mpi_risc()
41 tmp = qlge_read32(qdev, CSR); in qlge_hard_reset_mpi_risc()
43 qlge_write32(qdev, CSR, CSR_CMD_CLR_RST); in qlge_hard_reset_mpi_risc()
170 if (qlge_read32(qdev, CSR) & CSR_HRI) in qlge_exec_mb_cmd()
189 qlge_write32(qdev, CSR, CSR_CMD_SET_H2R_INT); in qlge_exec_mb_cmd()
513 qlge_write32(qdev, CSR, CSR_CMD_CLR_R2PCI_INT); in qlge_mpi_handler()
[all …]
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| D | qlge.h | 810 CSR = 0x14, enumerator
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| /drivers/soc/litex/ |
| D | Kconfig | 15 LiteX CSR access and provides common litex_[read|write]*
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| /drivers/dma/ti/ |
| D | omap-dma.c | 386 omap_dma_chan_read(c, CSR); in omap_dma_clear_csr()
388 omap_dma_chan_write(c, CSR, ~0); in omap_dma_clear_csr()
393 unsigned val = omap_dma_chan_read(c, CSR); in omap_dma_get_csr()
396 omap_dma_chan_write(c, CSR, val); in omap_dma_get_csr()
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| /drivers/misc/eeprom/ |
| D | Kconfig | 114 tristate "IDT 89HPESx PCIe-swtiches EEPROM / CSR support"
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| /drivers/net/ethernet/renesas/ |
| D | ravb.h | 52 CSR = 0x000C, enumerator
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| D | ravb_main.c | 78 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG); in ravb_config()
727 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, in ravb_stop_dma()
736 error = ravb_wait(ndev, CSR, CSR_RPO, 0); in ravb_stop_dma()
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| /drivers/spi/ |
| D | spi-at91-usart.c | 294 aus->status = at91_usart_spi_readl(aus, CSR); in at91_usart_spi_read_status()
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| /drivers/bluetooth/ |
| D | Kconfig | 140 USB Bluetooth devices based on CSR BlueCore chip, including PCMCIA and
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| /drivers/mmc/host/ |
| D | Kconfig | 924 the Cypress Astoria chip with firmware compliant with CSR's
927 CSR boards with this device include: USB<>SDIO (M1985v2),
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