| /drivers/gpu/drm/amd/amdgpu/ |
| D | gfxhub_v1_0.c | 221 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v1_0_enable_system_domain()
264 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v1_0_setup_vmid_config()
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| D | gfxhub_v2_0.c | 259 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v2_0_enable_system_domain()
291 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v2_0_setup_vmid_config()
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| D | gfxhub_v2_1.c | 262 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v2_1_enable_system_domain()
300 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v2_1_setup_vmid_config()
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| D | mmhub_v2_0.c | 334 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in mmhub_v2_0_enable_system_domain()
375 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in mmhub_v2_0_setup_vmid_config()
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| D | mmhub_v2_3.c | 253 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in mmhub_v2_3_enable_system_domain()
288 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in mmhub_v2_3_setup_vmid_config()
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| D | mmhub_v1_0.c | 202 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in mmhub_v1_0_enable_system_domain()
246 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in mmhub_v1_0_setup_vmid_config()
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| D | gmc_v7_0.c | 666 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gmc_v7_0_gart_enable()
696 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in gmc_v7_0_gart_enable()
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| D | mmhub_v1_7.c | 231 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in mmhub_v1_7_enable_system_domain()
278 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in mmhub_v1_7_setup_vmid_config()
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| D | gmc_v8_0.c | 905 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gmc_v8_0_gart_enable()
935 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in gmc_v8_0_gart_enable()
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| D | mmhub_v9_4.c | 262 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in mmhub_v9_4_enable_system_domain()
305 ENABLE_CONTEXT, 1); in mmhub_v9_4_setup_vmid_config()
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| D | sid.h | 394 #define ENABLE_CONTEXT (1 << 0) macro
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| /drivers/gpu/drm/radeon/ |
| D | rv770d.h | 635 #define ENABLE_CONTEXT (1 << 0) macro
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| D | ni.c | 1298 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in cayman_pcie_gart_enable()
1322 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | in cayman_pcie_gart_enable()
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| D | nid.h | 128 #define ENABLE_CONTEXT (1 << 0) macro
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| D | sid.h | 393 #define ENABLE_CONTEXT (1 << 0) macro
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| D | cikd.h | 511 #define ENABLE_CONTEXT (1 << 0) macro
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| D | rv770.c | 939 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in rv770_pcie_gart_enable()
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| D | evergreend.h | 1137 #define ENABLE_CONTEXT (1 << 0) macro
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| D | r600d.h | 574 #define ENABLE_CONTEXT (1 << 0) macro
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| D | si.c | 4321 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in si_pcie_gart_enable()
4349 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | in si_pcie_gart_enable()
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| D | cik.c | 5456 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in cik_pcie_gart_enable()
5480 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | in cik_pcie_gart_enable()
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| D | r600.c | 1171 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in r600_pcie_gart_enable()
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| D | evergreen.c | 2442 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in evergreen_pcie_gart_enable()
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