1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Neuros Technologies OSD2 board support
4 *
5 * Modified from original 644X-EVM board support.
6 * 2008 (c) Neuros Technology, LLC.
7 * 2009 (c) Jorge Luis Zapata Muga <jorgeluis.zapata@gmail.com>
8 * 2009 (c) Andrey A. Porodko <Andrey.Porodko@gmail.com>
9 *
10 * The Neuros OSD 2.0 is the hardware component of the Neuros Open
11 * Internet Television Platform. Hardware is very close to TI
12 * DM644X-EVM board. It has:
13 * DM6446M02 module with 256MB NAND, 256MB RAM, TLV320AIC32 AIC,
14 * USB, Ethernet, SD/MMC, UART, THS8200, TVP7000 for video.
15 * Additionally realtime clock, IR remote control receiver,
16 * IR Blaster based on MSP430 (firmware although is different
17 * from used in DM644X-EVM), internal ATA-6 3.5” HDD drive
18 * with PATA interface, two muxed red-green leds.
19 *
20 * For more information please refer to
21 * http://wiki.neurostechnology.com/index.php/OSD_2.0_HD
22 */
23 #include <linux/platform_device.h>
24 #include <linux/gpio.h>
25 #include <linux/leds.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/platform_data/gpio-davinci.h>
28 #include <linux/platform_data/i2c-davinci.h>
29 #include <linux/platform_data/mmc-davinci.h>
30 #include <linux/platform_data/mtd-davinci.h>
31 #include <linux/platform_data/usb-davinci.h>
32
33 #include <asm/mach-types.h>
34 #include <asm/mach/arch.h>
35
36 #include <mach/common.h>
37 #include <mach/serial.h>
38 #include <mach/mux.h>
39
40 #include "davinci.h"
41
42 #define NEUROS_OSD2_PHY_ID "davinci_mdio-0:01"
43 #define LXT971_PHY_ID 0x001378e2
44 #define LXT971_PHY_MASK 0xfffffff0
45
46 #define NTOSD2_AUDIOSOC_I2C_ADDR 0x18
47 #define NTOSD2_MSP430_I2C_ADDR 0x59
48 #define NTOSD2_MSP430_IRQ 2
49
50 /* Neuros OSD2 has a Samsung 256 MByte NAND flash (Dev ID of 0xAA,
51 * 2048 blocks in the device, 64 pages per block, 2048 bytes per
52 * page.
53 */
54
55 #define NAND_BLOCK_SIZE SZ_128K
56
57 static struct mtd_partition davinci_ntosd2_nandflash_partition[] = {
58 {
59 /* UBL (a few copies) plus U-Boot */
60 .name = "bootloader",
61 .offset = 0,
62 .size = 15 * NAND_BLOCK_SIZE,
63 .mask_flags = MTD_WRITEABLE, /* force read-only */
64 }, {
65 /* U-Boot environment */
66 .name = "params",
67 .offset = MTDPART_OFS_APPEND,
68 .size = 1 * NAND_BLOCK_SIZE,
69 .mask_flags = 0,
70 }, {
71 /* Kernel */
72 .name = "kernel",
73 .offset = MTDPART_OFS_APPEND,
74 .size = SZ_4M,
75 .mask_flags = 0,
76 }, {
77 /* File System */
78 .name = "filesystem",
79 .offset = MTDPART_OFS_APPEND,
80 .size = MTDPART_SIZ_FULL,
81 .mask_flags = 0,
82 }
83 /* A few blocks at end hold a flash Bad Block Table. */
84 };
85
86 static struct davinci_nand_pdata davinci_ntosd2_nandflash_data = {
87 .core_chipsel = 0,
88 .parts = davinci_ntosd2_nandflash_partition,
89 .nr_parts = ARRAY_SIZE(davinci_ntosd2_nandflash_partition),
90 .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
91 .ecc_bits = 1,
92 .bbt_options = NAND_BBT_USE_FLASH,
93 };
94
95 static struct resource davinci_ntosd2_nandflash_resource[] = {
96 {
97 .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
98 .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
99 .flags = IORESOURCE_MEM,
100 }, {
101 .start = DM644X_ASYNC_EMIF_CONTROL_BASE,
102 .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
103 .flags = IORESOURCE_MEM,
104 },
105 };
106
107 static struct platform_device davinci_ntosd2_nandflash_device = {
108 .name = "davinci_nand",
109 .id = 0,
110 .dev = {
111 .platform_data = &davinci_ntosd2_nandflash_data,
112 },
113 .num_resources = ARRAY_SIZE(davinci_ntosd2_nandflash_resource),
114 .resource = davinci_ntosd2_nandflash_resource,
115 };
116
117 static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32);
118
119 static struct platform_device davinci_fb_device = {
120 .name = "davincifb",
121 .id = -1,
122 .dev = {
123 .dma_mask = &davinci_fb_dma_mask,
124 .coherent_dma_mask = DMA_BIT_MASK(32),
125 },
126 .num_resources = 0,
127 };
128
129 static const struct gpio_led ntosd2_leds[] = {
130 { .name = "led1_green", .gpio = 10, },
131 { .name = "led1_red", .gpio = 11, },
132 { .name = "led2_green", .gpio = 12, },
133 { .name = "led2_red", .gpio = 13, },
134 };
135
136 static struct gpio_led_platform_data ntosd2_leds_data = {
137 .num_leds = ARRAY_SIZE(ntosd2_leds),
138 .leds = ntosd2_leds,
139 };
140
141 static struct platform_device ntosd2_leds_dev = {
142 .name = "leds-gpio",
143 .id = -1,
144 .dev = {
145 .platform_data = &ntosd2_leds_data,
146 },
147 };
148
149
150 static struct platform_device *davinci_ntosd2_devices[] __initdata = {
151 &davinci_fb_device,
152 &ntosd2_leds_dev,
153 };
154
davinci_ntosd2_map_io(void)155 static void __init davinci_ntosd2_map_io(void)
156 {
157 dm644x_init();
158 }
159
160 static struct davinci_mmc_config davinci_ntosd2_mmc_config = {
161 .wires = 4,
162 };
163
164 #define HAS_ATA (IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
165 IS_ENABLED(CONFIG_PATA_BK3710))
166
167 #define HAS_NAND IS_ENABLED(CONFIG_MTD_NAND_DAVINCI)
168
davinci_ntosd2_init(void)169 static __init void davinci_ntosd2_init(void)
170 {
171 int ret;
172 struct clk *aemif_clk;
173 struct davinci_soc_info *soc_info = &davinci_soc_info;
174
175 dm644x_register_clocks();
176
177 dm644x_init_devices();
178
179 ret = dm644x_gpio_register();
180 if (ret)
181 pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
182
183 aemif_clk = clk_get(NULL, "aemif");
184 clk_prepare_enable(aemif_clk);
185
186 if (HAS_ATA) {
187 if (HAS_NAND)
188 pr_warn("WARNING: both IDE and Flash are enabled, but they share AEMIF pins\n"
189 "\tDisable IDE for NAND/NOR support\n");
190 davinci_init_ide();
191 } else if (HAS_NAND) {
192 davinci_cfg_reg(DM644X_HPIEN_DISABLE);
193 davinci_cfg_reg(DM644X_ATAEN_DISABLE);
194
195 /* only one device will be jumpered and detected */
196 if (HAS_NAND)
197 platform_device_register(
198 &davinci_ntosd2_nandflash_device);
199 }
200
201 platform_add_devices(davinci_ntosd2_devices,
202 ARRAY_SIZE(davinci_ntosd2_devices));
203
204 davinci_serial_init(dm644x_serial_device);
205 dm644x_init_asp();
206
207 soc_info->emac_pdata->phy_id = NEUROS_OSD2_PHY_ID;
208
209 davinci_setup_usb(1000, 8);
210 /*
211 * Mux the pins to be GPIOs, VLYNQEN is already done at startup.
212 * The AEAWx are five new AEAW pins that can be muxed by separately.
213 * They are a bitmask for GPIO management. According TI
214 * documentation (https://www.ti.com/lit/gpn/tms320dm6446) to employ
215 * gpio(10,11,12,13) for leds any combination of bits works except
216 * four last. So we are to reset all five.
217 */
218 davinci_cfg_reg(DM644X_AEAW0);
219 davinci_cfg_reg(DM644X_AEAW1);
220 davinci_cfg_reg(DM644X_AEAW2);
221 davinci_cfg_reg(DM644X_AEAW3);
222 davinci_cfg_reg(DM644X_AEAW4);
223
224 davinci_setup_mmc(0, &davinci_ntosd2_mmc_config);
225 }
226
227 MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
228 /* Maintainer: Neuros Technologies <neuros@groups.google.com> */
229 .atag_offset = 0x100,
230 .map_io = davinci_ntosd2_map_io,
231 .init_irq = dm644x_init_irq,
232 .init_time = dm644x_init_time,
233 .init_machine = davinci_ntosd2_init,
234 .init_late = davinci_init_late,
235 .dma_zone_size = SZ_128M,
236 MACHINE_END
237