1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * This header defines architecture specific interfaces, x86 version
6 */
7
8 #ifndef _ASM_X86_KVM_HOST_H
9 #define _ASM_X86_KVM_HOST_H
10
11 #include <linux/types.h>
12 #include <linux/mm.h>
13 #include <linux/mmu_notifier.h>
14 #include <linux/tracepoint.h>
15 #include <linux/cpumask.h>
16 #include <linux/irq_work.h>
17 #include <linux/irq.h>
18
19 #include <linux/kvm.h>
20 #include <linux/kvm_para.h>
21 #include <linux/kvm_types.h>
22 #include <linux/perf_event.h>
23 #include <linux/pvclock_gtod.h>
24 #include <linux/clocksource.h>
25 #include <linux/irqbypass.h>
26 #include <linux/hyperv.h>
27
28 #include <asm/apic.h>
29 #include <asm/pvclock-abi.h>
30 #include <asm/desc.h>
31 #include <asm/mtrr.h>
32 #include <asm/msr-index.h>
33 #include <asm/asm.h>
34 #include <asm/kvm_page_track.h>
35 #include <asm/kvm_vcpu_regs.h>
36 #include <asm/hyperv-tlfs.h>
37
38 #define __KVM_HAVE_ARCH_VCPU_DEBUGFS
39
40 #define KVM_MAX_VCPUS 1024
41 #define KVM_SOFT_MAX_VCPUS 710
42
43 /*
44 * In x86, the VCPU ID corresponds to the APIC ID, and APIC IDs
45 * might be larger than the actual number of VCPUs because the
46 * APIC ID encodes CPU topology information.
47 *
48 * In the worst case, we'll need less than one extra bit for the
49 * Core ID, and less than one extra bit for the Package (Die) ID,
50 * so ratio of 4 should be enough.
51 */
52 #define KVM_VCPU_ID_RATIO 4
53 #define KVM_MAX_VCPU_ID (KVM_MAX_VCPUS * KVM_VCPU_ID_RATIO)
54
55 /* memory slots that are not exposed to userspace */
56 #define KVM_PRIVATE_MEM_SLOTS 3
57
58 #define KVM_HALT_POLL_NS_DEFAULT 200000
59
60 #define KVM_IRQCHIP_NUM_PINS KVM_IOAPIC_NUM_PINS
61
62 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \
63 KVM_DIRTY_LOG_INITIALLY_SET)
64
65 #define KVM_BUS_LOCK_DETECTION_VALID_MODE (KVM_BUS_LOCK_DETECTION_OFF | \
66 KVM_BUS_LOCK_DETECTION_EXIT)
67
68 /* x86-specific vcpu->requests bit members */
69 #define KVM_REQ_MIGRATE_TIMER KVM_ARCH_REQ(0)
70 #define KVM_REQ_REPORT_TPR_ACCESS KVM_ARCH_REQ(1)
71 #define KVM_REQ_TRIPLE_FAULT KVM_ARCH_REQ(2)
72 #define KVM_REQ_MMU_SYNC KVM_ARCH_REQ(3)
73 #define KVM_REQ_CLOCK_UPDATE KVM_ARCH_REQ(4)
74 #define KVM_REQ_LOAD_MMU_PGD KVM_ARCH_REQ(5)
75 #define KVM_REQ_EVENT KVM_ARCH_REQ(6)
76 #define KVM_REQ_APF_HALT KVM_ARCH_REQ(7)
77 #define KVM_REQ_STEAL_UPDATE KVM_ARCH_REQ(8)
78 #define KVM_REQ_NMI KVM_ARCH_REQ(9)
79 #define KVM_REQ_PMU KVM_ARCH_REQ(10)
80 #define KVM_REQ_PMI KVM_ARCH_REQ(11)
81 #define KVM_REQ_SMI KVM_ARCH_REQ(12)
82 #define KVM_REQ_MASTERCLOCK_UPDATE KVM_ARCH_REQ(13)
83 #define KVM_REQ_MCLOCK_INPROGRESS \
84 KVM_ARCH_REQ_FLAGS(14, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
85 #define KVM_REQ_SCAN_IOAPIC \
86 KVM_ARCH_REQ_FLAGS(15, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
87 #define KVM_REQ_GLOBAL_CLOCK_UPDATE KVM_ARCH_REQ(16)
88 #define KVM_REQ_APIC_PAGE_RELOAD \
89 KVM_ARCH_REQ_FLAGS(17, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
90 #define KVM_REQ_HV_CRASH KVM_ARCH_REQ(18)
91 #define KVM_REQ_IOAPIC_EOI_EXIT KVM_ARCH_REQ(19)
92 #define KVM_REQ_HV_RESET KVM_ARCH_REQ(20)
93 #define KVM_REQ_HV_EXIT KVM_ARCH_REQ(21)
94 #define KVM_REQ_HV_STIMER KVM_ARCH_REQ(22)
95 #define KVM_REQ_LOAD_EOI_EXITMAP KVM_ARCH_REQ(23)
96 #define KVM_REQ_GET_NESTED_STATE_PAGES KVM_ARCH_REQ(24)
97 #define KVM_REQ_APICV_UPDATE \
98 KVM_ARCH_REQ_FLAGS(25, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
99 #define KVM_REQ_TLB_FLUSH_CURRENT KVM_ARCH_REQ(26)
100 #define KVM_REQ_TLB_FLUSH_GUEST \
101 KVM_ARCH_REQ_FLAGS(27, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
102 #define KVM_REQ_APF_READY KVM_ARCH_REQ(28)
103 #define KVM_REQ_MSR_FILTER_CHANGED KVM_ARCH_REQ(29)
104 #define KVM_REQ_UPDATE_CPU_DIRTY_LOGGING \
105 KVM_ARCH_REQ_FLAGS(30, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
106
107 #define CR0_RESERVED_BITS \
108 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
109 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
110 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
111
112 #define CR4_RESERVED_BITS \
113 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
114 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
115 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \
116 | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \
117 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \
118 | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP))
119
120 #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
121
122
123
124 #define INVALID_PAGE (~(hpa_t)0)
125 #define VALID_PAGE(x) ((x) != INVALID_PAGE)
126
127 #define UNMAPPED_GVA (~(gpa_t)0)
128 #define INVALID_GPA (~(gpa_t)0)
129
130 /* KVM Hugepage definitions for x86 */
131 #define KVM_MAX_HUGEPAGE_LEVEL PG_LEVEL_1G
132 #define KVM_NR_PAGE_SIZES (KVM_MAX_HUGEPAGE_LEVEL - PG_LEVEL_4K + 1)
133 #define KVM_HPAGE_GFN_SHIFT(x) (((x) - 1) * 9)
134 #define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x))
135 #define KVM_HPAGE_SIZE(x) (1UL << KVM_HPAGE_SHIFT(x))
136 #define KVM_HPAGE_MASK(x) (~(KVM_HPAGE_SIZE(x) - 1))
137 #define KVM_PAGES_PER_HPAGE(x) (KVM_HPAGE_SIZE(x) / PAGE_SIZE)
138
139 #define KVM_PERMILLE_MMU_PAGES 20
140 #define KVM_MIN_ALLOC_MMU_PAGES 64UL
141 #define KVM_MMU_HASH_SHIFT 12
142 #define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT)
143 #define KVM_MIN_FREE_MMU_PAGES 5
144 #define KVM_REFILL_PAGES 25
145 #define KVM_MAX_CPUID_ENTRIES 256
146 #define KVM_NR_FIXED_MTRR_REGION 88
147 #define KVM_NR_VAR_MTRR 8
148
149 #define ASYNC_PF_PER_VCPU 64
150
151 enum kvm_reg {
152 VCPU_REGS_RAX = __VCPU_REGS_RAX,
153 VCPU_REGS_RCX = __VCPU_REGS_RCX,
154 VCPU_REGS_RDX = __VCPU_REGS_RDX,
155 VCPU_REGS_RBX = __VCPU_REGS_RBX,
156 VCPU_REGS_RSP = __VCPU_REGS_RSP,
157 VCPU_REGS_RBP = __VCPU_REGS_RBP,
158 VCPU_REGS_RSI = __VCPU_REGS_RSI,
159 VCPU_REGS_RDI = __VCPU_REGS_RDI,
160 #ifdef CONFIG_X86_64
161 VCPU_REGS_R8 = __VCPU_REGS_R8,
162 VCPU_REGS_R9 = __VCPU_REGS_R9,
163 VCPU_REGS_R10 = __VCPU_REGS_R10,
164 VCPU_REGS_R11 = __VCPU_REGS_R11,
165 VCPU_REGS_R12 = __VCPU_REGS_R12,
166 VCPU_REGS_R13 = __VCPU_REGS_R13,
167 VCPU_REGS_R14 = __VCPU_REGS_R14,
168 VCPU_REGS_R15 = __VCPU_REGS_R15,
169 #endif
170 VCPU_REGS_RIP,
171 NR_VCPU_REGS,
172
173 VCPU_EXREG_PDPTR = NR_VCPU_REGS,
174 VCPU_EXREG_CR0,
175 VCPU_EXREG_CR3,
176 VCPU_EXREG_CR4,
177 VCPU_EXREG_RFLAGS,
178 VCPU_EXREG_SEGMENTS,
179 VCPU_EXREG_EXIT_INFO_1,
180 VCPU_EXREG_EXIT_INFO_2,
181 };
182
183 enum {
184 VCPU_SREG_ES,
185 VCPU_SREG_CS,
186 VCPU_SREG_SS,
187 VCPU_SREG_DS,
188 VCPU_SREG_FS,
189 VCPU_SREG_GS,
190 VCPU_SREG_TR,
191 VCPU_SREG_LDTR,
192 };
193
194 enum exit_fastpath_completion {
195 EXIT_FASTPATH_NONE,
196 EXIT_FASTPATH_REENTER_GUEST,
197 EXIT_FASTPATH_EXIT_HANDLED,
198 };
199 typedef enum exit_fastpath_completion fastpath_t;
200
201 struct x86_emulate_ctxt;
202 struct x86_exception;
203 enum x86_intercept;
204 enum x86_intercept_stage;
205
206 #define KVM_NR_DB_REGS 4
207
208 #define DR6_BUS_LOCK (1 << 11)
209 #define DR6_BD (1 << 13)
210 #define DR6_BS (1 << 14)
211 #define DR6_BT (1 << 15)
212 #define DR6_RTM (1 << 16)
213 /*
214 * DR6_ACTIVE_LOW combines fixed-1 and active-low bits.
215 * We can regard all the bits in DR6_FIXED_1 as active_low bits;
216 * they will never be 0 for now, but when they are defined
217 * in the future it will require no code change.
218 *
219 * DR6_ACTIVE_LOW is also used as the init/reset value for DR6.
220 */
221 #define DR6_ACTIVE_LOW 0xffff0ff0
222 #define DR6_VOLATILE 0x0001e80f
223 #define DR6_FIXED_1 (DR6_ACTIVE_LOW & ~DR6_VOLATILE)
224
225 #define DR7_BP_EN_MASK 0x000000ff
226 #define DR7_GE (1 << 9)
227 #define DR7_GD (1 << 13)
228 #define DR7_FIXED_1 0x00000400
229 #define DR7_VOLATILE 0xffff2bff
230
231 #define KVM_GUESTDBG_VALID_MASK \
232 (KVM_GUESTDBG_ENABLE | \
233 KVM_GUESTDBG_SINGLESTEP | \
234 KVM_GUESTDBG_USE_HW_BP | \
235 KVM_GUESTDBG_USE_SW_BP | \
236 KVM_GUESTDBG_INJECT_BP | \
237 KVM_GUESTDBG_INJECT_DB | \
238 KVM_GUESTDBG_BLOCKIRQ)
239
240
241 #define PFERR_PRESENT_BIT 0
242 #define PFERR_WRITE_BIT 1
243 #define PFERR_USER_BIT 2
244 #define PFERR_RSVD_BIT 3
245 #define PFERR_FETCH_BIT 4
246 #define PFERR_PK_BIT 5
247 #define PFERR_SGX_BIT 15
248 #define PFERR_GUEST_FINAL_BIT 32
249 #define PFERR_GUEST_PAGE_BIT 33
250
251 #define PFERR_PRESENT_MASK (1U << PFERR_PRESENT_BIT)
252 #define PFERR_WRITE_MASK (1U << PFERR_WRITE_BIT)
253 #define PFERR_USER_MASK (1U << PFERR_USER_BIT)
254 #define PFERR_RSVD_MASK (1U << PFERR_RSVD_BIT)
255 #define PFERR_FETCH_MASK (1U << PFERR_FETCH_BIT)
256 #define PFERR_PK_MASK (1U << PFERR_PK_BIT)
257 #define PFERR_SGX_MASK (1U << PFERR_SGX_BIT)
258 #define PFERR_GUEST_FINAL_MASK (1ULL << PFERR_GUEST_FINAL_BIT)
259 #define PFERR_GUEST_PAGE_MASK (1ULL << PFERR_GUEST_PAGE_BIT)
260
261 #define PFERR_NESTED_GUEST_PAGE (PFERR_GUEST_PAGE_MASK | \
262 PFERR_WRITE_MASK | \
263 PFERR_PRESENT_MASK)
264
265 /* apic attention bits */
266 #define KVM_APIC_CHECK_VAPIC 0
267 /*
268 * The following bit is set with PV-EOI, unset on EOI.
269 * We detect PV-EOI changes by guest by comparing
270 * this bit with PV-EOI in guest memory.
271 * See the implementation in apic_update_pv_eoi.
272 */
273 #define KVM_APIC_PV_EOI_PENDING 1
274
275 struct kvm_kernel_irq_routing_entry;
276
277 /*
278 * kvm_mmu_page_role tracks the properties of a shadow page (where shadow page
279 * also includes TDP pages) to determine whether or not a page can be used in
280 * the given MMU context. This is a subset of the overall kvm_mmu_role to
281 * minimize the size of kvm_memory_slot.arch.gfn_track, i.e. allows allocating
282 * 2 bytes per gfn instead of 4 bytes per gfn.
283 *
284 * Indirect upper-level shadow pages are tracked for write-protection via
285 * gfn_track. As above, gfn_track is a 16 bit counter, so KVM must not create
286 * more than 2^16-1 upper-level shadow pages at a single gfn, otherwise
287 * gfn_track will overflow and explosions will ensure.
288 *
289 * A unique shadow page (SP) for a gfn is created if and only if an existing SP
290 * cannot be reused. The ability to reuse a SP is tracked by its role, which
291 * incorporates various mode bits and properties of the SP. Roughly speaking,
292 * the number of unique SPs that can theoretically be created is 2^n, where n
293 * is the number of bits that are used to compute the role.
294 *
295 * But, even though there are 18 bits in the mask below, not all combinations
296 * of modes and flags are possible. The maximum number of possible upper-level
297 * shadow pages for a single gfn is in the neighborhood of 2^13.
298 *
299 * - invalid shadow pages are not accounted.
300 * - level is effectively limited to four combinations, not 16 as the number
301 * bits would imply, as 4k SPs are not tracked (allowed to go unsync).
302 * - level is effectively unused for non-PAE paging because there is exactly
303 * one upper level (see 4k SP exception above).
304 * - quadrant is used only for non-PAE paging and is exclusive with
305 * gpte_is_8_bytes.
306 * - execonly and ad_disabled are used only for nested EPT, which makes it
307 * exclusive with quadrant.
308 */
309 union kvm_mmu_page_role {
310 u32 word;
311 struct {
312 unsigned level:4;
313 unsigned gpte_is_8_bytes:1;
314 unsigned quadrant:2;
315 unsigned direct:1;
316 unsigned access:3;
317 unsigned invalid:1;
318 unsigned efer_nx:1;
319 unsigned cr0_wp:1;
320 unsigned smep_andnot_wp:1;
321 unsigned smap_andnot_wp:1;
322 unsigned ad_disabled:1;
323 unsigned guest_mode:1;
324 unsigned :6;
325
326 /*
327 * This is left at the top of the word so that
328 * kvm_memslots_for_spte_role can extract it with a
329 * simple shift. While there is room, give it a whole
330 * byte so it is also faster to load it from memory.
331 */
332 unsigned smm:8;
333 };
334 };
335
336 /*
337 * kvm_mmu_extended_role complements kvm_mmu_page_role, tracking properties
338 * relevant to the current MMU configuration. When loading CR0, CR4, or EFER,
339 * including on nested transitions, if nothing in the full role changes then
340 * MMU re-configuration can be skipped. @valid bit is set on first usage so we
341 * don't treat all-zero structure as valid data.
342 *
343 * The properties that are tracked in the extended role but not the page role
344 * are for things that either (a) do not affect the validity of the shadow page
345 * or (b) are indirectly reflected in the shadow page's role. For example,
346 * CR4.PKE only affects permission checks for software walks of the guest page
347 * tables (because KVM doesn't support Protection Keys with shadow paging), and
348 * CR0.PG, CR4.PAE, and CR4.PSE are indirectly reflected in role.level.
349 *
350 * Note, SMEP and SMAP are not redundant with sm*p_andnot_wp in the page role.
351 * If CR0.WP=1, KVM can reuse shadow pages for the guest regardless of SMEP and
352 * SMAP, but the MMU's permission checks for software walks need to be SMEP and
353 * SMAP aware regardless of CR0.WP.
354 */
355 union kvm_mmu_extended_role {
356 u32 word;
357 struct {
358 unsigned int valid:1;
359 unsigned int execonly:1;
360 unsigned int cr0_pg:1;
361 unsigned int cr4_pae:1;
362 unsigned int cr4_pse:1;
363 unsigned int cr4_pke:1;
364 unsigned int cr4_smap:1;
365 unsigned int cr4_smep:1;
366 unsigned int cr4_la57:1;
367 unsigned int efer_lma:1;
368 };
369 };
370
371 union kvm_mmu_role {
372 u64 as_u64;
373 struct {
374 union kvm_mmu_page_role base;
375 union kvm_mmu_extended_role ext;
376 };
377 };
378
379 struct kvm_rmap_head {
380 unsigned long val;
381 };
382
383 struct kvm_pio_request {
384 unsigned long linear_rip;
385 unsigned long count;
386 int in;
387 int port;
388 int size;
389 };
390
391 #define PT64_ROOT_MAX_LEVEL 5
392
393 struct rsvd_bits_validate {
394 u64 rsvd_bits_mask[2][PT64_ROOT_MAX_LEVEL];
395 u64 bad_mt_xwr;
396 };
397
398 struct kvm_mmu_root_info {
399 gpa_t pgd;
400 hpa_t hpa;
401 };
402
403 #define KVM_MMU_ROOT_INFO_INVALID \
404 ((struct kvm_mmu_root_info) { .pgd = INVALID_PAGE, .hpa = INVALID_PAGE })
405
406 #define KVM_MMU_NUM_PREV_ROOTS 3
407
408 #define KVM_HAVE_MMU_RWLOCK
409
410 struct kvm_mmu_page;
411
412 /*
413 * x86 supports 4 paging modes (5-level 64-bit, 4-level 64-bit, 3-level 32-bit,
414 * and 2-level 32-bit). The kvm_mmu structure abstracts the details of the
415 * current mmu mode.
416 */
417 struct kvm_mmu {
418 unsigned long (*get_guest_pgd)(struct kvm_vcpu *vcpu);
419 u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index);
420 int (*page_fault)(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u32 err,
421 bool prefault);
422 void (*inject_page_fault)(struct kvm_vcpu *vcpu,
423 struct x86_exception *fault);
424 gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gpa_t gva_or_gpa,
425 u32 access, struct x86_exception *exception);
426 gpa_t (*translate_gpa)(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
427 struct x86_exception *exception);
428 int (*sync_page)(struct kvm_vcpu *vcpu,
429 struct kvm_mmu_page *sp);
430 void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root_hpa);
431 hpa_t root_hpa;
432 gpa_t root_pgd;
433 union kvm_mmu_role mmu_role;
434 u8 root_level;
435 u8 shadow_root_level;
436 u8 ept_ad;
437 bool direct_map;
438 struct kvm_mmu_root_info prev_roots[KVM_MMU_NUM_PREV_ROOTS];
439
440 /*
441 * Bitmap; bit set = permission fault
442 * Byte index: page fault error code [4:1]
443 * Bit index: pte permissions in ACC_* format
444 */
445 u8 permissions[16];
446
447 /*
448 * The pkru_mask indicates if protection key checks are needed. It
449 * consists of 16 domains indexed by page fault error code bits [4:1],
450 * with PFEC.RSVD replaced by ACC_USER_MASK from the page tables.
451 * Each domain has 2 bits which are ANDed with AD and WD from PKRU.
452 */
453 u32 pkru_mask;
454
455 u64 *pae_root;
456 u64 *pml4_root;
457 u64 *pml5_root;
458
459 /*
460 * check zero bits on shadow page table entries, these
461 * bits include not only hardware reserved bits but also
462 * the bits spte never used.
463 */
464 struct rsvd_bits_validate shadow_zero_check;
465
466 struct rsvd_bits_validate guest_rsvd_check;
467
468 u64 pdptrs[4]; /* pae */
469 };
470
471 struct kvm_tlb_range {
472 u64 start_gfn;
473 u64 pages;
474 };
475
476 enum pmc_type {
477 KVM_PMC_GP = 0,
478 KVM_PMC_FIXED,
479 };
480
481 struct kvm_pmc {
482 enum pmc_type type;
483 u8 idx;
484 u64 counter;
485 u64 eventsel;
486 struct perf_event *perf_event;
487 struct kvm_vcpu *vcpu;
488 /*
489 * eventsel value for general purpose counters,
490 * ctrl value for fixed counters.
491 */
492 u64 current_config;
493 bool is_paused;
494 };
495
496 struct kvm_pmu {
497 unsigned nr_arch_gp_counters;
498 unsigned nr_arch_fixed_counters;
499 unsigned available_event_types;
500 u64 fixed_ctr_ctrl;
501 u64 fixed_ctr_ctrl_mask;
502 u64 global_ctrl;
503 u64 global_status;
504 u64 global_ovf_ctrl;
505 u64 counter_bitmask[2];
506 u64 global_ctrl_mask;
507 u64 global_ovf_ctrl_mask;
508 u64 reserved_bits;
509 u64 raw_event_mask;
510 u8 version;
511 struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC];
512 struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED];
513 struct irq_work irq_work;
514 DECLARE_BITMAP(reprogram_pmi, X86_PMC_IDX_MAX);
515 DECLARE_BITMAP(all_valid_pmc_idx, X86_PMC_IDX_MAX);
516 DECLARE_BITMAP(pmc_in_use, X86_PMC_IDX_MAX);
517
518 /*
519 * The gate to release perf_events not marked in
520 * pmc_in_use only once in a vcpu time slice.
521 */
522 bool need_cleanup;
523
524 /*
525 * The total number of programmed perf_events and it helps to avoid
526 * redundant check before cleanup if guest don't use vPMU at all.
527 */
528 u8 event_count;
529 };
530
531 struct kvm_pmu_ops;
532
533 enum {
534 KVM_DEBUGREG_BP_ENABLED = 1,
535 KVM_DEBUGREG_WONT_EXIT = 2,
536 };
537
538 struct kvm_mtrr_range {
539 u64 base;
540 u64 mask;
541 struct list_head node;
542 };
543
544 struct kvm_mtrr {
545 struct kvm_mtrr_range var_ranges[KVM_NR_VAR_MTRR];
546 mtrr_type fixed_ranges[KVM_NR_FIXED_MTRR_REGION];
547 u64 deftype;
548
549 struct list_head head;
550 };
551
552 /* Hyper-V SynIC timer */
553 struct kvm_vcpu_hv_stimer {
554 struct hrtimer timer;
555 int index;
556 union hv_stimer_config config;
557 u64 count;
558 u64 exp_time;
559 struct hv_message msg;
560 bool msg_pending;
561 };
562
563 /* Hyper-V synthetic interrupt controller (SynIC)*/
564 struct kvm_vcpu_hv_synic {
565 u64 version;
566 u64 control;
567 u64 msg_page;
568 u64 evt_page;
569 atomic64_t sint[HV_SYNIC_SINT_COUNT];
570 atomic_t sint_to_gsi[HV_SYNIC_SINT_COUNT];
571 DECLARE_BITMAP(auto_eoi_bitmap, 256);
572 DECLARE_BITMAP(vec_bitmap, 256);
573 bool active;
574 bool dont_zero_synic_pages;
575 };
576
577 /* Hyper-V per vcpu emulation context */
578 struct kvm_vcpu_hv {
579 struct kvm_vcpu *vcpu;
580 u32 vp_index;
581 u64 hv_vapic;
582 s64 runtime_offset;
583 struct kvm_vcpu_hv_synic synic;
584 struct kvm_hyperv_exit exit;
585 struct kvm_vcpu_hv_stimer stimer[HV_SYNIC_STIMER_COUNT];
586 DECLARE_BITMAP(stimer_pending_bitmap, HV_SYNIC_STIMER_COUNT);
587 cpumask_t tlb_flush;
588 bool enforce_cpuid;
589 struct {
590 u32 features_eax; /* HYPERV_CPUID_FEATURES.EAX */
591 u32 features_ebx; /* HYPERV_CPUID_FEATURES.EBX */
592 u32 features_edx; /* HYPERV_CPUID_FEATURES.EDX */
593 u32 enlightenments_eax; /* HYPERV_CPUID_ENLIGHTMENT_INFO.EAX */
594 u32 enlightenments_ebx; /* HYPERV_CPUID_ENLIGHTMENT_INFO.EBX */
595 u32 syndbg_cap_eax; /* HYPERV_CPUID_SYNDBG_PLATFORM_CAPABILITIES.EAX */
596 } cpuid_cache;
597 };
598
599 /* Xen HVM per vcpu emulation context */
600 struct kvm_vcpu_xen {
601 u64 hypercall_rip;
602 u32 current_runstate;
603 bool vcpu_info_set;
604 bool vcpu_time_info_set;
605 bool runstate_set;
606 struct gfn_to_hva_cache vcpu_info_cache;
607 struct gfn_to_hva_cache vcpu_time_info_cache;
608 struct gfn_to_hva_cache runstate_cache;
609 u64 last_steal;
610 u64 runstate_entry_time;
611 u64 runstate_times[4];
612 };
613
614 struct kvm_vcpu_arch {
615 /*
616 * rip and regs accesses must go through
617 * kvm_{register,rip}_{read,write} functions.
618 */
619 unsigned long regs[NR_VCPU_REGS];
620 u32 regs_avail;
621 u32 regs_dirty;
622
623 unsigned long cr0;
624 unsigned long cr0_guest_owned_bits;
625 unsigned long cr2;
626 unsigned long cr3;
627 unsigned long cr4;
628 unsigned long cr4_guest_owned_bits;
629 unsigned long cr4_guest_rsvd_bits;
630 unsigned long cr8;
631 u32 host_pkru;
632 u32 pkru;
633 u32 hflags;
634 u64 efer;
635 u64 apic_base;
636 struct kvm_lapic *apic; /* kernel irqchip context */
637 bool apicv_active;
638 bool load_eoi_exitmap_pending;
639 DECLARE_BITMAP(ioapic_handled_vectors, 256);
640 unsigned long apic_attention;
641 int32_t apic_arb_prio;
642 int mp_state;
643 u64 ia32_misc_enable_msr;
644 u64 smbase;
645 u64 smi_count;
646 bool at_instruction_boundary;
647 bool tpr_access_reporting;
648 bool xsaves_enabled;
649 u64 ia32_xss;
650 u64 microcode_version;
651 u64 arch_capabilities;
652 u64 perf_capabilities;
653
654 /*
655 * Paging state of the vcpu
656 *
657 * If the vcpu runs in guest mode with two level paging this still saves
658 * the paging mode of the l1 guest. This context is always used to
659 * handle faults.
660 */
661 struct kvm_mmu *mmu;
662
663 /* Non-nested MMU for L1 */
664 struct kvm_mmu root_mmu;
665
666 /* L1 MMU when running nested */
667 struct kvm_mmu guest_mmu;
668
669 /*
670 * Paging state of an L2 guest (used for nested npt)
671 *
672 * This context will save all necessary information to walk page tables
673 * of an L2 guest. This context is only initialized for page table
674 * walking and not for faulting since we never handle l2 page faults on
675 * the host.
676 */
677 struct kvm_mmu nested_mmu;
678
679 /*
680 * Pointer to the mmu context currently used for
681 * gva_to_gpa translations.
682 */
683 struct kvm_mmu *walk_mmu;
684
685 struct kvm_mmu_memory_cache mmu_pte_list_desc_cache;
686 struct kvm_mmu_memory_cache mmu_shadow_page_cache;
687 struct kvm_mmu_memory_cache mmu_gfn_array_cache;
688 struct kvm_mmu_memory_cache mmu_page_header_cache;
689
690 /*
691 * QEMU userspace and the guest each have their own FPU state.
692 * In vcpu_run, we switch between the user and guest FPU contexts.
693 * While running a VCPU, the VCPU thread will have the guest FPU
694 * context.
695 *
696 * Note that while the PKRU state lives inside the fpu registers,
697 * it is switched out separately at VMENTER and VMEXIT time. The
698 * "guest_fpu" state here contains the guest FPU context, with the
699 * host PRKU bits.
700 */
701 struct fpu *user_fpu;
702 struct fpu *guest_fpu;
703
704 u64 xcr0;
705 u64 guest_supported_xcr0;
706
707 struct kvm_pio_request pio;
708 void *pio_data;
709 void *sev_pio_data;
710 unsigned sev_pio_count;
711
712 u8 event_exit_inst_len;
713
714 struct kvm_queued_exception {
715 bool pending;
716 bool injected;
717 bool has_error_code;
718 u8 nr;
719 u32 error_code;
720 unsigned long payload;
721 bool has_payload;
722 u8 nested_apf;
723 } exception;
724
725 struct kvm_queued_interrupt {
726 bool injected;
727 bool soft;
728 u8 nr;
729 } interrupt;
730
731 int halt_request; /* real mode on Intel only */
732
733 int cpuid_nent;
734 struct kvm_cpuid_entry2 *cpuid_entries;
735
736 u64 reserved_gpa_bits;
737 int maxphyaddr;
738
739 /* emulate context */
740
741 struct x86_emulate_ctxt *emulate_ctxt;
742 bool emulate_regs_need_sync_to_vcpu;
743 bool emulate_regs_need_sync_from_vcpu;
744 int (*complete_userspace_io)(struct kvm_vcpu *vcpu);
745
746 gpa_t time;
747 struct pvclock_vcpu_time_info hv_clock;
748 unsigned int hw_tsc_khz;
749 struct gfn_to_hva_cache pv_time;
750 bool pv_time_enabled;
751 /* set guest stopped flag in pvclock flags field */
752 bool pvclock_set_guest_stopped_request;
753
754 struct {
755 u8 preempted;
756 u64 msr_val;
757 u64 last_steal;
758 struct gfn_to_hva_cache cache;
759 } st;
760
761 u64 l1_tsc_offset;
762 u64 tsc_offset; /* current tsc offset */
763 u64 last_guest_tsc;
764 u64 last_host_tsc;
765 u64 tsc_offset_adjustment;
766 u64 this_tsc_nsec;
767 u64 this_tsc_write;
768 u64 this_tsc_generation;
769 bool tsc_catchup;
770 bool tsc_always_catchup;
771 s8 virtual_tsc_shift;
772 u32 virtual_tsc_mult;
773 u32 virtual_tsc_khz;
774 s64 ia32_tsc_adjust_msr;
775 u64 msr_ia32_power_ctl;
776 u64 l1_tsc_scaling_ratio;
777 u64 tsc_scaling_ratio; /* current scaling ratio */
778
779 atomic_t nmi_queued; /* unprocessed asynchronous NMIs */
780 unsigned nmi_pending; /* NMI queued after currently running handler */
781 bool nmi_injected; /* Trying to inject an NMI this entry */
782 bool smi_pending; /* SMI queued after currently running handler */
783 u8 handling_intr_from_guest;
784
785 struct kvm_mtrr mtrr_state;
786 u64 pat;
787
788 unsigned switch_db_regs;
789 unsigned long db[KVM_NR_DB_REGS];
790 unsigned long dr6;
791 unsigned long dr7;
792 unsigned long eff_db[KVM_NR_DB_REGS];
793 unsigned long guest_debug_dr7;
794 u64 msr_platform_info;
795 u64 msr_misc_features_enables;
796
797 u64 mcg_cap;
798 u64 mcg_status;
799 u64 mcg_ctl;
800 u64 mcg_ext_ctl;
801 u64 *mce_banks;
802
803 /* Cache MMIO info */
804 u64 mmio_gva;
805 unsigned mmio_access;
806 gfn_t mmio_gfn;
807 u64 mmio_gen;
808
809 struct kvm_pmu pmu;
810
811 /* used for guest single stepping over the given code position */
812 unsigned long singlestep_rip;
813
814 bool hyperv_enabled;
815 struct kvm_vcpu_hv *hyperv;
816 struct kvm_vcpu_xen xen;
817
818 cpumask_var_t wbinvd_dirty_mask;
819
820 unsigned long last_retry_eip;
821 unsigned long last_retry_addr;
822
823 struct {
824 bool halted;
825 gfn_t gfns[ASYNC_PF_PER_VCPU];
826 struct gfn_to_hva_cache data;
827 u64 msr_en_val; /* MSR_KVM_ASYNC_PF_EN */
828 u64 msr_int_val; /* MSR_KVM_ASYNC_PF_INT */
829 u16 vec;
830 u32 id;
831 bool send_user_only;
832 u32 host_apf_flags;
833 unsigned long nested_apf_token;
834 bool delivery_as_pf_vmexit;
835 bool pageready_pending;
836 } apf;
837
838 /* OSVW MSRs (AMD only) */
839 struct {
840 u64 length;
841 u64 status;
842 } osvw;
843
844 struct {
845 u64 msr_val;
846 struct gfn_to_hva_cache data;
847 } pv_eoi;
848
849 u64 msr_kvm_poll_control;
850
851 /*
852 * Indicates the guest is trying to write a gfn that contains one or
853 * more of the PTEs used to translate the write itself, i.e. the access
854 * is changing its own translation in the guest page tables. KVM exits
855 * to userspace if emulation of the faulting instruction fails and this
856 * flag is set, as KVM cannot make forward progress.
857 *
858 * If emulation fails for a write to guest page tables, KVM unprotects
859 * (zaps) the shadow page for the target gfn and resumes the guest to
860 * retry the non-emulatable instruction (on hardware). Unprotecting the
861 * gfn doesn't allow forward progress for a self-changing access because
862 * doing so also zaps the translation for the gfn, i.e. retrying the
863 * instruction will hit a !PRESENT fault, which results in a new shadow
864 * page and sends KVM back to square one.
865 */
866 bool write_fault_to_shadow_pgtable;
867
868 /* set at EPT violation at this point */
869 unsigned long exit_qualification;
870
871 /* pv related host specific info */
872 struct {
873 bool pv_unhalted;
874 } pv;
875
876 int pending_ioapic_eoi;
877 int pending_external_vector;
878
879 /* be preempted when it's in kernel-mode(cpl=0) */
880 bool preempted_in_kernel;
881
882 /* Flush the L1 Data cache for L1TF mitigation on VMENTER */
883 bool l1tf_flush_l1d;
884
885 /* Host CPU on which VM-entry was most recently attempted */
886 int last_vmentry_cpu;
887
888 /* AMD MSRC001_0015 Hardware Configuration */
889 u64 msr_hwcr;
890
891 /* pv related cpuid info */
892 struct {
893 /*
894 * value of the eax register in the KVM_CPUID_FEATURES CPUID
895 * leaf.
896 */
897 u32 features;
898
899 /*
900 * indicates whether pv emulation should be disabled if features
901 * are not present in the guest's cpuid
902 */
903 bool enforce;
904 } pv_cpuid;
905
906 /* Protected Guests */
907 bool guest_state_protected;
908
909 /*
910 * Set when PDPTS were loaded directly by the userspace without
911 * reading the guest memory
912 */
913 bool pdptrs_from_userspace;
914
915 #if IS_ENABLED(CONFIG_HYPERV)
916 hpa_t hv_root_tdp;
917 #endif
918 };
919
920 struct kvm_lpage_info {
921 int disallow_lpage;
922 };
923
924 struct kvm_arch_memory_slot {
925 struct kvm_rmap_head *rmap[KVM_NR_PAGE_SIZES];
926 struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1];
927 unsigned short *gfn_track[KVM_PAGE_TRACK_MAX];
928 };
929
930 /*
931 * We use as the mode the number of bits allocated in the LDR for the
932 * logical processor ID. It happens that these are all powers of two.
933 * This makes it is very easy to detect cases where the APICs are
934 * configured for multiple modes; in that case, we cannot use the map and
935 * hence cannot use kvm_irq_delivery_to_apic_fast either.
936 */
937 #define KVM_APIC_MODE_XAPIC_CLUSTER 4
938 #define KVM_APIC_MODE_XAPIC_FLAT 8
939 #define KVM_APIC_MODE_X2APIC 16
940
941 struct kvm_apic_map {
942 struct rcu_head rcu;
943 u8 mode;
944 u32 max_apic_id;
945 union {
946 struct kvm_lapic *xapic_flat_map[8];
947 struct kvm_lapic *xapic_cluster_map[16][4];
948 };
949 struct kvm_lapic *phys_map[];
950 };
951
952 /* Hyper-V synthetic debugger (SynDbg)*/
953 struct kvm_hv_syndbg {
954 struct {
955 u64 control;
956 u64 status;
957 u64 send_page;
958 u64 recv_page;
959 u64 pending_page;
960 } control;
961 u64 options;
962 };
963
964 /* Current state of Hyper-V TSC page clocksource */
965 enum hv_tsc_page_status {
966 /* TSC page was not set up or disabled */
967 HV_TSC_PAGE_UNSET = 0,
968 /* TSC page MSR was written by the guest, update pending */
969 HV_TSC_PAGE_GUEST_CHANGED,
970 /* TSC page MSR was written by KVM userspace, update pending */
971 HV_TSC_PAGE_HOST_CHANGED,
972 /* TSC page was properly set up and is currently active */
973 HV_TSC_PAGE_SET,
974 /* TSC page is currently being updated and therefore is inactive */
975 HV_TSC_PAGE_UPDATING,
976 /* TSC page was set up with an inaccessible GPA */
977 HV_TSC_PAGE_BROKEN,
978 };
979
980 /* Hyper-V emulation context */
981 struct kvm_hv {
982 struct mutex hv_lock;
983 u64 hv_guest_os_id;
984 u64 hv_hypercall;
985 u64 hv_tsc_page;
986 enum hv_tsc_page_status hv_tsc_page_status;
987
988 /* Hyper-v based guest crash (NT kernel bugcheck) parameters */
989 u64 hv_crash_param[HV_X64_MSR_CRASH_PARAMS];
990 u64 hv_crash_ctl;
991
992 struct ms_hyperv_tsc_page tsc_ref;
993
994 struct idr conn_to_evt;
995
996 u64 hv_reenlightenment_control;
997 u64 hv_tsc_emulation_control;
998 u64 hv_tsc_emulation_status;
999
1000 /* How many vCPUs have VP index != vCPU index */
1001 atomic_t num_mismatched_vp_indexes;
1002
1003 /*
1004 * How many SynICs use 'AutoEOI' feature
1005 * (protected by arch.apicv_update_lock)
1006 */
1007 unsigned int synic_auto_eoi_used;
1008
1009 struct hv_partition_assist_pg *hv_pa_pg;
1010 struct kvm_hv_syndbg hv_syndbg;
1011 };
1012
1013 struct msr_bitmap_range {
1014 u32 flags;
1015 u32 nmsrs;
1016 u32 base;
1017 unsigned long *bitmap;
1018 };
1019
1020 /* Xen emulation context */
1021 struct kvm_xen {
1022 bool long_mode;
1023 u8 upcall_vector;
1024 gfn_t shinfo_gfn;
1025 };
1026
1027 enum kvm_irqchip_mode {
1028 KVM_IRQCHIP_NONE,
1029 KVM_IRQCHIP_KERNEL, /* created with KVM_CREATE_IRQCHIP */
1030 KVM_IRQCHIP_SPLIT, /* created with KVM_CAP_SPLIT_IRQCHIP */
1031 };
1032
1033 struct kvm_x86_msr_filter {
1034 u8 count;
1035 bool default_allow:1;
1036 struct msr_bitmap_range ranges[16];
1037 };
1038
1039 #define APICV_INHIBIT_REASON_DISABLE 0
1040 #define APICV_INHIBIT_REASON_HYPERV 1
1041 #define APICV_INHIBIT_REASON_NESTED 2
1042 #define APICV_INHIBIT_REASON_IRQWIN 3
1043 #define APICV_INHIBIT_REASON_PIT_REINJ 4
1044 #define APICV_INHIBIT_REASON_X2APIC 5
1045
1046 struct kvm_arch {
1047 unsigned long n_used_mmu_pages;
1048 unsigned long n_requested_mmu_pages;
1049 unsigned long n_max_mmu_pages;
1050 unsigned int indirect_shadow_pages;
1051 u8 mmu_valid_gen;
1052 struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES];
1053 struct list_head active_mmu_pages;
1054 struct list_head zapped_obsolete_pages;
1055 struct list_head lpage_disallowed_mmu_pages;
1056 struct kvm_page_track_notifier_node mmu_sp_tracker;
1057 struct kvm_page_track_notifier_head track_notifier_head;
1058 /*
1059 * Protects marking pages unsync during page faults, as TDP MMU page
1060 * faults only take mmu_lock for read. For simplicity, the unsync
1061 * pages lock is always taken when marking pages unsync regardless of
1062 * whether mmu_lock is held for read or write.
1063 */
1064 spinlock_t mmu_unsync_pages_lock;
1065
1066 struct list_head assigned_dev_head;
1067 struct iommu_domain *iommu_domain;
1068 bool iommu_noncoherent;
1069 #define __KVM_HAVE_ARCH_NONCOHERENT_DMA
1070 atomic_t noncoherent_dma_count;
1071 #define __KVM_HAVE_ARCH_ASSIGNED_DEVICE
1072 atomic_t assigned_device_count;
1073 struct kvm_pic *vpic;
1074 struct kvm_ioapic *vioapic;
1075 struct kvm_pit *vpit;
1076 atomic_t vapics_in_nmi_mode;
1077 struct mutex apic_map_lock;
1078 struct kvm_apic_map __rcu *apic_map;
1079 atomic_t apic_map_dirty;
1080
1081 /* Protects apic_access_memslot_enabled and apicv_inhibit_reasons */
1082 struct mutex apicv_update_lock;
1083
1084 bool apic_access_memslot_enabled;
1085 unsigned long apicv_inhibit_reasons;
1086
1087 gpa_t wall_clock;
1088
1089 bool mwait_in_guest;
1090 bool hlt_in_guest;
1091 bool pause_in_guest;
1092 bool cstate_in_guest;
1093
1094 unsigned long irq_sources_bitmap;
1095 s64 kvmclock_offset;
1096 raw_spinlock_t tsc_write_lock;
1097 u64 last_tsc_nsec;
1098 u64 last_tsc_write;
1099 u32 last_tsc_khz;
1100 u64 cur_tsc_nsec;
1101 u64 cur_tsc_write;
1102 u64 cur_tsc_offset;
1103 u64 cur_tsc_generation;
1104 int nr_vcpus_matched_tsc;
1105
1106 raw_spinlock_t pvclock_gtod_sync_lock;
1107 bool use_master_clock;
1108 u64 master_kernel_ns;
1109 u64 master_cycle_now;
1110 struct delayed_work kvmclock_update_work;
1111 struct delayed_work kvmclock_sync_work;
1112
1113 struct kvm_xen_hvm_config xen_hvm_config;
1114
1115 /* reads protected by irq_srcu, writes by irq_lock */
1116 struct hlist_head mask_notifier_list;
1117
1118 struct kvm_hv hyperv;
1119 struct kvm_xen xen;
1120
1121 #ifdef CONFIG_KVM_MMU_AUDIT
1122 int audit_point;
1123 #endif
1124
1125 bool backwards_tsc_observed;
1126 bool boot_vcpu_runs_old_kvmclock;
1127 u32 bsp_vcpu_id;
1128
1129 u64 disabled_quirks;
1130 int cpu_dirty_logging_count;
1131
1132 enum kvm_irqchip_mode irqchip_mode;
1133 u8 nr_reserved_ioapic_pins;
1134
1135 bool disabled_lapic_found;
1136
1137 bool x2apic_format;
1138 bool x2apic_broadcast_quirk_disabled;
1139
1140 bool guest_can_read_msr_platform_info;
1141 bool exception_payload_enabled;
1142
1143 bool bus_lock_detection_enabled;
1144 /*
1145 * If exit_on_emulation_error is set, and the in-kernel instruction
1146 * emulator fails to emulate an instruction, allow userspace
1147 * the opportunity to look at it.
1148 */
1149 bool exit_on_emulation_error;
1150
1151 /* Deflect RDMSR and WRMSR to user space when they trigger a #GP */
1152 u32 user_space_msr_mask;
1153 struct kvm_x86_msr_filter __rcu *msr_filter;
1154
1155 u32 hypercall_exit_enabled;
1156
1157 /* Guest can access the SGX PROVISIONKEY. */
1158 bool sgx_provisioning_allowed;
1159
1160 struct kvm_pmu_event_filter __rcu *pmu_event_filter;
1161 struct task_struct *nx_lpage_recovery_thread;
1162
1163 #ifdef CONFIG_X86_64
1164 /*
1165 * Whether the TDP MMU is enabled for this VM. This contains a
1166 * snapshot of the TDP MMU module parameter from when the VM was
1167 * created and remains unchanged for the life of the VM. If this is
1168 * true, TDP MMU handler functions will run for various MMU
1169 * operations.
1170 */
1171 bool tdp_mmu_enabled;
1172
1173 /*
1174 * List of struct kvm_mmu_pages being used as roots.
1175 * All struct kvm_mmu_pages in the list should have
1176 * tdp_mmu_page set.
1177 *
1178 * For reads, this list is protected by:
1179 * the MMU lock in read mode + RCU or
1180 * the MMU lock in write mode
1181 *
1182 * For writes, this list is protected by:
1183 * the MMU lock in read mode + the tdp_mmu_pages_lock or
1184 * the MMU lock in write mode
1185 *
1186 * Roots will remain in the list until their tdp_mmu_root_count
1187 * drops to zero, at which point the thread that decremented the
1188 * count to zero should removed the root from the list and clean
1189 * it up, freeing the root after an RCU grace period.
1190 */
1191 struct list_head tdp_mmu_roots;
1192
1193 /*
1194 * List of struct kvmp_mmu_pages not being used as roots.
1195 * All struct kvm_mmu_pages in the list should have
1196 * tdp_mmu_page set and a tdp_mmu_root_count of 0.
1197 */
1198 struct list_head tdp_mmu_pages;
1199
1200 /*
1201 * Protects accesses to the following fields when the MMU lock
1202 * is held in read mode:
1203 * - tdp_mmu_roots (above)
1204 * - tdp_mmu_pages (above)
1205 * - the link field of struct kvm_mmu_pages used by the TDP MMU
1206 * - lpage_disallowed_mmu_pages
1207 * - the lpage_disallowed_link field of struct kvm_mmu_pages used
1208 * by the TDP MMU
1209 * It is acceptable, but not necessary, to acquire this lock when
1210 * the thread holds the MMU lock in write mode.
1211 */
1212 spinlock_t tdp_mmu_pages_lock;
1213 #endif /* CONFIG_X86_64 */
1214
1215 /*
1216 * If set, rmaps have been allocated for all memslots and should be
1217 * allocated for any newly created or modified memslots.
1218 */
1219 bool memslots_have_rmaps;
1220
1221 #if IS_ENABLED(CONFIG_HYPERV)
1222 hpa_t hv_root_tdp;
1223 spinlock_t hv_root_tdp_lock;
1224 #endif
1225 };
1226
1227 struct kvm_vm_stat {
1228 struct kvm_vm_stat_generic generic;
1229 u64 mmu_shadow_zapped;
1230 u64 mmu_pte_write;
1231 u64 mmu_pde_zapped;
1232 u64 mmu_flooded;
1233 u64 mmu_recycled;
1234 u64 mmu_cache_miss;
1235 u64 mmu_unsync;
1236 union {
1237 struct {
1238 atomic64_t pages_4k;
1239 atomic64_t pages_2m;
1240 atomic64_t pages_1g;
1241 };
1242 atomic64_t pages[KVM_NR_PAGE_SIZES];
1243 };
1244 u64 nx_lpage_splits;
1245 u64 max_mmu_page_hash_collisions;
1246 u64 max_mmu_rmap_size;
1247 };
1248
1249 struct kvm_vcpu_stat {
1250 struct kvm_vcpu_stat_generic generic;
1251 u64 pf_fixed;
1252 u64 pf_guest;
1253 u64 tlb_flush;
1254 u64 invlpg;
1255
1256 u64 exits;
1257 u64 io_exits;
1258 u64 mmio_exits;
1259 u64 signal_exits;
1260 u64 irq_window_exits;
1261 u64 nmi_window_exits;
1262 u64 l1d_flush;
1263 u64 halt_exits;
1264 u64 request_irq_exits;
1265 u64 irq_exits;
1266 u64 host_state_reload;
1267 u64 fpu_reload;
1268 u64 insn_emulation;
1269 u64 insn_emulation_fail;
1270 u64 hypercalls;
1271 u64 irq_injections;
1272 u64 nmi_injections;
1273 u64 req_event;
1274 u64 nested_run;
1275 u64 directed_yield_attempted;
1276 u64 directed_yield_successful;
1277 u64 preemption_reported;
1278 u64 preemption_other;
1279 u64 guest_mode;
1280 };
1281
1282 struct x86_instruction_info;
1283
1284 struct msr_data {
1285 bool host_initiated;
1286 u32 index;
1287 u64 data;
1288 };
1289
1290 struct kvm_lapic_irq {
1291 u32 vector;
1292 u16 delivery_mode;
1293 u16 dest_mode;
1294 bool level;
1295 u16 trig_mode;
1296 u32 shorthand;
1297 u32 dest_id;
1298 bool msi_redir_hint;
1299 };
1300
kvm_lapic_irq_dest_mode(bool dest_mode_logical)1301 static inline u16 kvm_lapic_irq_dest_mode(bool dest_mode_logical)
1302 {
1303 return dest_mode_logical ? APIC_DEST_LOGICAL : APIC_DEST_PHYSICAL;
1304 }
1305
1306 struct kvm_x86_ops {
1307 int (*hardware_enable)(void);
1308 void (*hardware_disable)(void);
1309 void (*hardware_unsetup)(void);
1310 bool (*cpu_has_accelerated_tpr)(void);
1311 bool (*has_emulated_msr)(struct kvm *kvm, u32 index);
1312 void (*vcpu_after_set_cpuid)(struct kvm_vcpu *vcpu);
1313
1314 unsigned int vm_size;
1315 int (*vm_init)(struct kvm *kvm);
1316 void (*vm_destroy)(struct kvm *kvm);
1317
1318 /* Create, but do not attach this VCPU */
1319 int (*vcpu_create)(struct kvm_vcpu *vcpu);
1320 void (*vcpu_free)(struct kvm_vcpu *vcpu);
1321 void (*vcpu_reset)(struct kvm_vcpu *vcpu, bool init_event);
1322
1323 void (*prepare_guest_switch)(struct kvm_vcpu *vcpu);
1324 void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu);
1325 void (*vcpu_put)(struct kvm_vcpu *vcpu);
1326
1327 void (*update_exception_bitmap)(struct kvm_vcpu *vcpu);
1328 int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr);
1329 int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr);
1330 u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg);
1331 void (*get_segment)(struct kvm_vcpu *vcpu,
1332 struct kvm_segment *var, int seg);
1333 int (*get_cpl)(struct kvm_vcpu *vcpu);
1334 void (*set_segment)(struct kvm_vcpu *vcpu,
1335 struct kvm_segment *var, int seg);
1336 void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l);
1337 bool (*is_valid_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0);
1338 void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0);
1339 bool (*is_valid_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4);
1340 void (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4);
1341 int (*set_efer)(struct kvm_vcpu *vcpu, u64 efer);
1342 void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
1343 void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
1344 void (*get_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
1345 void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
1346 void (*sync_dirty_debug_regs)(struct kvm_vcpu *vcpu);
1347 void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value);
1348 void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg);
1349 unsigned long (*get_rflags)(struct kvm_vcpu *vcpu);
1350 void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags);
1351 bool (*get_if_flag)(struct kvm_vcpu *vcpu);
1352
1353 void (*tlb_flush_all)(struct kvm_vcpu *vcpu);
1354 void (*tlb_flush_current)(struct kvm_vcpu *vcpu);
1355 int (*tlb_remote_flush)(struct kvm *kvm);
1356 int (*tlb_remote_flush_with_range)(struct kvm *kvm,
1357 struct kvm_tlb_range *range);
1358
1359 /*
1360 * Flush any TLB entries associated with the given GVA.
1361 * Does not need to flush GPA->HPA mappings.
1362 * Can potentially get non-canonical addresses through INVLPGs, which
1363 * the implementation may choose to ignore if appropriate.
1364 */
1365 void (*tlb_flush_gva)(struct kvm_vcpu *vcpu, gva_t addr);
1366
1367 /*
1368 * Flush any TLB entries created by the guest. Like tlb_flush_gva(),
1369 * does not need to flush GPA->HPA mappings.
1370 */
1371 void (*tlb_flush_guest)(struct kvm_vcpu *vcpu);
1372
1373 enum exit_fastpath_completion (*run)(struct kvm_vcpu *vcpu);
1374 int (*handle_exit)(struct kvm_vcpu *vcpu,
1375 enum exit_fastpath_completion exit_fastpath);
1376 int (*skip_emulated_instruction)(struct kvm_vcpu *vcpu);
1377 void (*update_emulated_instruction)(struct kvm_vcpu *vcpu);
1378 void (*set_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask);
1379 u32 (*get_interrupt_shadow)(struct kvm_vcpu *vcpu);
1380 void (*patch_hypercall)(struct kvm_vcpu *vcpu,
1381 unsigned char *hypercall_addr);
1382 void (*set_irq)(struct kvm_vcpu *vcpu);
1383 void (*set_nmi)(struct kvm_vcpu *vcpu);
1384 void (*queue_exception)(struct kvm_vcpu *vcpu);
1385 void (*cancel_injection)(struct kvm_vcpu *vcpu);
1386 int (*interrupt_allowed)(struct kvm_vcpu *vcpu, bool for_injection);
1387 int (*nmi_allowed)(struct kvm_vcpu *vcpu, bool for_injection);
1388 bool (*get_nmi_mask)(struct kvm_vcpu *vcpu);
1389 void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked);
1390 void (*enable_nmi_window)(struct kvm_vcpu *vcpu);
1391 void (*enable_irq_window)(struct kvm_vcpu *vcpu);
1392 void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr);
1393 bool (*check_apicv_inhibit_reasons)(ulong bit);
1394 void (*refresh_apicv_exec_ctrl)(struct kvm_vcpu *vcpu);
1395 void (*hwapic_irr_update)(struct kvm_vcpu *vcpu, int max_irr);
1396 void (*hwapic_isr_update)(struct kvm_vcpu *vcpu, int isr);
1397 bool (*guest_apic_has_interrupt)(struct kvm_vcpu *vcpu);
1398 void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap);
1399 void (*set_virtual_apic_mode)(struct kvm_vcpu *vcpu);
1400 void (*set_apic_access_page_addr)(struct kvm_vcpu *vcpu);
1401 int (*deliver_posted_interrupt)(struct kvm_vcpu *vcpu, int vector);
1402 int (*sync_pir_to_irr)(struct kvm_vcpu *vcpu);
1403 int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
1404 int (*set_identity_map_addr)(struct kvm *kvm, u64 ident_addr);
1405 u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio);
1406
1407 void (*load_mmu_pgd)(struct kvm_vcpu *vcpu, hpa_t root_hpa,
1408 int root_level);
1409
1410 bool (*has_wbinvd_exit)(void);
1411
1412 u64 (*get_l2_tsc_offset)(struct kvm_vcpu *vcpu);
1413 u64 (*get_l2_tsc_multiplier)(struct kvm_vcpu *vcpu);
1414 void (*write_tsc_offset)(struct kvm_vcpu *vcpu, u64 offset);
1415 void (*write_tsc_multiplier)(struct kvm_vcpu *vcpu, u64 multiplier);
1416
1417 /*
1418 * Retrieve somewhat arbitrary exit information. Intended to be used
1419 * only from within tracepoints to avoid VMREADs when tracing is off.
1420 */
1421 void (*get_exit_info)(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2,
1422 u32 *exit_int_info, u32 *exit_int_info_err_code);
1423
1424 int (*check_intercept)(struct kvm_vcpu *vcpu,
1425 struct x86_instruction_info *info,
1426 enum x86_intercept_stage stage,
1427 struct x86_exception *exception);
1428 void (*handle_exit_irqoff)(struct kvm_vcpu *vcpu);
1429
1430 void (*request_immediate_exit)(struct kvm_vcpu *vcpu);
1431
1432 void (*sched_in)(struct kvm_vcpu *kvm, int cpu);
1433
1434 /*
1435 * Size of the CPU's dirty log buffer, i.e. VMX's PML buffer. A zero
1436 * value indicates CPU dirty logging is unsupported or disabled.
1437 */
1438 int cpu_dirty_log_size;
1439 void (*update_cpu_dirty_logging)(struct kvm_vcpu *vcpu);
1440
1441 /* pmu operations of sub-arch */
1442 const struct kvm_pmu_ops *pmu_ops;
1443 const struct kvm_x86_nested_ops *nested_ops;
1444
1445 /*
1446 * Architecture specific hooks for vCPU blocking due to
1447 * HLT instruction.
1448 * Returns for .pre_block():
1449 * - 0 means continue to block the vCPU.
1450 * - 1 means we cannot block the vCPU since some event
1451 * happens during this period, such as, 'ON' bit in
1452 * posted-interrupts descriptor is set.
1453 */
1454 int (*pre_block)(struct kvm_vcpu *vcpu);
1455 void (*post_block)(struct kvm_vcpu *vcpu);
1456
1457 void (*vcpu_blocking)(struct kvm_vcpu *vcpu);
1458 void (*vcpu_unblocking)(struct kvm_vcpu *vcpu);
1459
1460 int (*update_pi_irte)(struct kvm *kvm, unsigned int host_irq,
1461 uint32_t guest_irq, bool set);
1462 void (*start_assignment)(struct kvm *kvm);
1463 void (*apicv_post_state_restore)(struct kvm_vcpu *vcpu);
1464 bool (*dy_apicv_has_pending_interrupt)(struct kvm_vcpu *vcpu);
1465
1466 int (*set_hv_timer)(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
1467 bool *expired);
1468 void (*cancel_hv_timer)(struct kvm_vcpu *vcpu);
1469
1470 void (*setup_mce)(struct kvm_vcpu *vcpu);
1471
1472 int (*smi_allowed)(struct kvm_vcpu *vcpu, bool for_injection);
1473 int (*enter_smm)(struct kvm_vcpu *vcpu, char *smstate);
1474 int (*leave_smm)(struct kvm_vcpu *vcpu, const char *smstate);
1475 void (*enable_smi_window)(struct kvm_vcpu *vcpu);
1476
1477 int (*mem_enc_op)(struct kvm *kvm, void __user *argp);
1478 int (*mem_enc_reg_region)(struct kvm *kvm, struct kvm_enc_region *argp);
1479 int (*mem_enc_unreg_region)(struct kvm *kvm, struct kvm_enc_region *argp);
1480 int (*vm_copy_enc_context_from)(struct kvm *kvm, unsigned int source_fd);
1481 void (*guest_memory_reclaimed)(struct kvm *kvm);
1482
1483 int (*get_msr_feature)(struct kvm_msr_entry *entry);
1484
1485 bool (*can_emulate_instruction)(struct kvm_vcpu *vcpu, void *insn, int insn_len);
1486
1487 bool (*apic_init_signal_blocked)(struct kvm_vcpu *vcpu);
1488 int (*enable_direct_tlbflush)(struct kvm_vcpu *vcpu);
1489
1490 void (*migrate_timers)(struct kvm_vcpu *vcpu);
1491 void (*msr_filter_changed)(struct kvm_vcpu *vcpu);
1492 int (*complete_emulated_msr)(struct kvm_vcpu *vcpu, int err);
1493
1494 void (*vcpu_deliver_sipi_vector)(struct kvm_vcpu *vcpu, u8 vector);
1495 };
1496
1497 struct kvm_x86_nested_ops {
1498 void (*leave_nested)(struct kvm_vcpu *vcpu);
1499 int (*check_events)(struct kvm_vcpu *vcpu);
1500 bool (*hv_timer_pending)(struct kvm_vcpu *vcpu);
1501 void (*triple_fault)(struct kvm_vcpu *vcpu);
1502 int (*get_state)(struct kvm_vcpu *vcpu,
1503 struct kvm_nested_state __user *user_kvm_nested_state,
1504 unsigned user_data_size);
1505 int (*set_state)(struct kvm_vcpu *vcpu,
1506 struct kvm_nested_state __user *user_kvm_nested_state,
1507 struct kvm_nested_state *kvm_state);
1508 bool (*get_nested_state_pages)(struct kvm_vcpu *vcpu);
1509 int (*write_log_dirty)(struct kvm_vcpu *vcpu, gpa_t l2_gpa);
1510
1511 int (*enable_evmcs)(struct kvm_vcpu *vcpu,
1512 uint16_t *vmcs_version);
1513 uint16_t (*get_evmcs_version)(struct kvm_vcpu *vcpu);
1514 };
1515
1516 struct kvm_x86_init_ops {
1517 int (*cpu_has_kvm_support)(void);
1518 int (*disabled_by_bios)(void);
1519 int (*check_processor_compatibility)(void);
1520 int (*hardware_setup)(void);
1521 unsigned int (*handle_intel_pt_intr)(void);
1522
1523 struct kvm_x86_ops *runtime_ops;
1524 };
1525
1526 struct kvm_arch_async_pf {
1527 u32 token;
1528 gfn_t gfn;
1529 unsigned long cr3;
1530 bool direct_map;
1531 };
1532
1533 extern u32 __read_mostly kvm_nr_uret_msrs;
1534 extern u64 __read_mostly host_efer;
1535 extern bool __read_mostly allow_smaller_maxphyaddr;
1536 extern bool __read_mostly enable_apicv;
1537 extern struct kvm_x86_ops kvm_x86_ops;
1538
1539 #define KVM_X86_OP(func) \
1540 DECLARE_STATIC_CALL(kvm_x86_##func, *(((struct kvm_x86_ops *)0)->func));
1541 #define KVM_X86_OP_NULL KVM_X86_OP
1542 #include <asm/kvm-x86-ops.h>
1543
kvm_ops_static_call_update(void)1544 static inline void kvm_ops_static_call_update(void)
1545 {
1546 #define KVM_X86_OP(func) \
1547 static_call_update(kvm_x86_##func, kvm_x86_ops.func);
1548 #define KVM_X86_OP_NULL KVM_X86_OP
1549 #include <asm/kvm-x86-ops.h>
1550 }
1551
1552 #define __KVM_HAVE_ARCH_VM_ALLOC
kvm_arch_alloc_vm(void)1553 static inline struct kvm *kvm_arch_alloc_vm(void)
1554 {
1555 return __vmalloc(kvm_x86_ops.vm_size, GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1556 }
1557 void kvm_arch_free_vm(struct kvm *kvm);
1558
1559 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLB
kvm_arch_flush_remote_tlb(struct kvm * kvm)1560 static inline int kvm_arch_flush_remote_tlb(struct kvm *kvm)
1561 {
1562 if (kvm_x86_ops.tlb_remote_flush &&
1563 !static_call(kvm_x86_tlb_remote_flush)(kvm))
1564 return 0;
1565 else
1566 return -ENOTSUPP;
1567 }
1568
1569 #define kvm_arch_pmi_in_guest(vcpu) \
1570 ((vcpu) && (vcpu)->arch.handling_intr_from_guest)
1571
1572 void __init kvm_mmu_x86_module_init(void);
1573 int kvm_mmu_vendor_module_init(void);
1574 void kvm_mmu_vendor_module_exit(void);
1575
1576 void kvm_mmu_destroy(struct kvm_vcpu *vcpu);
1577 int kvm_mmu_create(struct kvm_vcpu *vcpu);
1578 void kvm_mmu_init_vm(struct kvm *kvm);
1579 void kvm_mmu_uninit_vm(struct kvm *kvm);
1580
1581 void kvm_mmu_after_set_cpuid(struct kvm_vcpu *vcpu);
1582 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu);
1583 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
1584 const struct kvm_memory_slot *memslot,
1585 int start_level);
1586 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
1587 const struct kvm_memory_slot *memslot);
1588 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
1589 const struct kvm_memory_slot *memslot);
1590 void kvm_mmu_zap_all(struct kvm *kvm);
1591 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen);
1592 unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm);
1593 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long kvm_nr_mmu_pages);
1594
1595 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3);
1596
1597 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
1598 const void *val, int bytes);
1599
1600 struct kvm_irq_mask_notifier {
1601 void (*func)(struct kvm_irq_mask_notifier *kimn, bool masked);
1602 int irq;
1603 struct hlist_node link;
1604 };
1605
1606 void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq,
1607 struct kvm_irq_mask_notifier *kimn);
1608 void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq,
1609 struct kvm_irq_mask_notifier *kimn);
1610 void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin,
1611 bool mask);
1612
1613 extern bool tdp_enabled;
1614
1615 u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu);
1616
1617 /* control of guest tsc rate supported? */
1618 extern bool kvm_has_tsc_control;
1619 /* maximum supported tsc_khz for guests */
1620 extern u32 kvm_max_guest_tsc_khz;
1621 /* number of bits of the fractional part of the TSC scaling ratio */
1622 extern u8 kvm_tsc_scaling_ratio_frac_bits;
1623 /* maximum allowed value of TSC scaling ratio */
1624 extern u64 kvm_max_tsc_scaling_ratio;
1625 /* 1ull << kvm_tsc_scaling_ratio_frac_bits */
1626 extern u64 kvm_default_tsc_scaling_ratio;
1627 /* bus lock detection supported? */
1628 extern bool kvm_has_bus_lock_exit;
1629
1630 extern u64 kvm_mce_cap_supported;
1631
1632 /*
1633 * EMULTYPE_NO_DECODE - Set when re-emulating an instruction (after completing
1634 * userspace I/O) to indicate that the emulation context
1635 * should be reused as is, i.e. skip initialization of
1636 * emulation context, instruction fetch and decode.
1637 *
1638 * EMULTYPE_TRAP_UD - Set when emulating an intercepted #UD from hardware.
1639 * Indicates that only select instructions (tagged with
1640 * EmulateOnUD) should be emulated (to minimize the emulator
1641 * attack surface). See also EMULTYPE_TRAP_UD_FORCED.
1642 *
1643 * EMULTYPE_SKIP - Set when emulating solely to skip an instruction, i.e. to
1644 * decode the instruction length. For use *only* by
1645 * kvm_x86_ops.skip_emulated_instruction() implementations.
1646 *
1647 * EMULTYPE_ALLOW_RETRY_PF - Set when the emulator should resume the guest to
1648 * retry native execution under certain conditions,
1649 * Can only be set in conjunction with EMULTYPE_PF.
1650 *
1651 * EMULTYPE_TRAP_UD_FORCED - Set when emulating an intercepted #UD that was
1652 * triggered by KVM's magic "force emulation" prefix,
1653 * which is opt in via module param (off by default).
1654 * Bypasses EmulateOnUD restriction despite emulating
1655 * due to an intercepted #UD (see EMULTYPE_TRAP_UD).
1656 * Used to test the full emulator from userspace.
1657 *
1658 * EMULTYPE_VMWARE_GP - Set when emulating an intercepted #GP for VMware
1659 * backdoor emulation, which is opt in via module param.
1660 * VMware backdoor emulation handles select instructions
1661 * and reinjects the #GP for all other cases.
1662 *
1663 * EMULTYPE_PF - Set when emulating MMIO by way of an intercepted #PF, in which
1664 * case the CR2/GPA value pass on the stack is valid.
1665 */
1666 #define EMULTYPE_NO_DECODE (1 << 0)
1667 #define EMULTYPE_TRAP_UD (1 << 1)
1668 #define EMULTYPE_SKIP (1 << 2)
1669 #define EMULTYPE_ALLOW_RETRY_PF (1 << 3)
1670 #define EMULTYPE_TRAP_UD_FORCED (1 << 4)
1671 #define EMULTYPE_VMWARE_GP (1 << 5)
1672 #define EMULTYPE_PF (1 << 6)
1673
1674 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type);
1675 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
1676 void *insn, int insn_len);
1677
1678 void kvm_enable_efer_bits(u64);
1679 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer);
1680 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, bool host_initiated);
1681 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data);
1682 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data);
1683 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu);
1684 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu);
1685 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu);
1686 int kvm_emulate_invd(struct kvm_vcpu *vcpu);
1687 int kvm_emulate_mwait(struct kvm_vcpu *vcpu);
1688 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu);
1689 int kvm_emulate_monitor(struct kvm_vcpu *vcpu);
1690
1691 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in);
1692 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu);
1693 int kvm_emulate_halt(struct kvm_vcpu *vcpu);
1694 int kvm_vcpu_halt(struct kvm_vcpu *vcpu);
1695 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu);
1696 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu);
1697
1698 void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
1699 int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg);
1700 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector);
1701
1702 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
1703 int reason, bool has_error_code, u32 error_code);
1704
1705 void kvm_free_guest_fpu(struct kvm_vcpu *vcpu);
1706
1707 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0);
1708 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4);
1709 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
1710 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
1711 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1712 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8);
1713 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val);
1714 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val);
1715 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu);
1716 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw);
1717 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l);
1718 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu);
1719
1720 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr);
1721 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr);
1722
1723 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu);
1724 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
1725 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu);
1726
1727 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr);
1728 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code);
1729 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, unsigned long payload);
1730 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr);
1731 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code);
1732 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault);
1733 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
1734 struct x86_exception *fault);
1735 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
1736 gfn_t gfn, void *data, int offset, int len,
1737 u32 access);
1738 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl);
1739 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr);
1740
__kvm_irq_line_state(unsigned long * irq_state,int irq_source_id,int level)1741 static inline int __kvm_irq_line_state(unsigned long *irq_state,
1742 int irq_source_id, int level)
1743 {
1744 /* Logical OR for level trig interrupt */
1745 if (level)
1746 __set_bit(irq_source_id, irq_state);
1747 else
1748 __clear_bit(irq_source_id, irq_state);
1749
1750 return !!(*irq_state);
1751 }
1752
1753 #define KVM_MMU_ROOT_CURRENT BIT(0)
1754 #define KVM_MMU_ROOT_PREVIOUS(i) BIT(1+i)
1755 #define KVM_MMU_ROOTS_ALL (~0UL)
1756
1757 int kvm_pic_set_irq(struct kvm_pic *pic, int irq, int irq_source_id, int level);
1758 void kvm_pic_clear_all(struct kvm_pic *pic, int irq_source_id);
1759
1760 void kvm_inject_nmi(struct kvm_vcpu *vcpu);
1761
1762 void kvm_update_dr7(struct kvm_vcpu *vcpu);
1763
1764 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn);
1765 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu);
1766 void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
1767 ulong roots_to_free);
1768 void kvm_mmu_free_guest_mode_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu);
1769 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
1770 struct x86_exception *exception);
1771 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
1772 struct x86_exception *exception);
1773 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
1774 struct x86_exception *exception);
1775 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
1776 struct x86_exception *exception);
1777 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
1778 struct x86_exception *exception);
1779
1780 bool kvm_apicv_activated(struct kvm *kvm);
1781 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu);
1782 void kvm_request_apicv_update(struct kvm *kvm, bool activate,
1783 unsigned long bit);
1784
1785 void __kvm_request_apicv_update(struct kvm *kvm, bool activate,
1786 unsigned long bit);
1787
1788 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu);
1789
1790 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code,
1791 void *insn, int insn_len);
1792 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva);
1793 void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
1794 gva_t gva, hpa_t root_hpa);
1795 void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid);
1796 void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd);
1797
1798 void kvm_configure_mmu(bool enable_tdp, int tdp_forced_root_level,
1799 int tdp_max_root_level, int tdp_huge_page_level);
1800
kvm_read_ldt(void)1801 static inline u16 kvm_read_ldt(void)
1802 {
1803 u16 ldt;
1804 asm("sldt %0" : "=g"(ldt));
1805 return ldt;
1806 }
1807
kvm_load_ldt(u16 sel)1808 static inline void kvm_load_ldt(u16 sel)
1809 {
1810 asm("lldt %0" : : "rm"(sel));
1811 }
1812
1813 #ifdef CONFIG_X86_64
read_msr(unsigned long msr)1814 static inline unsigned long read_msr(unsigned long msr)
1815 {
1816 u64 value;
1817
1818 rdmsrl(msr, value);
1819 return value;
1820 }
1821 #endif
1822
kvm_inject_gp(struct kvm_vcpu * vcpu,u32 error_code)1823 static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code)
1824 {
1825 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
1826 }
1827
1828 #define TSS_IOPB_BASE_OFFSET 0x66
1829 #define TSS_BASE_SIZE 0x68
1830 #define TSS_IOPB_SIZE (65536 / 8)
1831 #define TSS_REDIRECTION_SIZE (256 / 8)
1832 #define RMODE_TSS_SIZE \
1833 (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1)
1834
1835 enum {
1836 TASK_SWITCH_CALL = 0,
1837 TASK_SWITCH_IRET = 1,
1838 TASK_SWITCH_JMP = 2,
1839 TASK_SWITCH_GATE = 3,
1840 };
1841
1842 #define HF_GIF_MASK (1 << 0)
1843 #define HF_NMI_MASK (1 << 3)
1844 #define HF_IRET_MASK (1 << 4)
1845 #define HF_GUEST_MASK (1 << 5) /* VCPU is in guest-mode */
1846 #define HF_SMM_MASK (1 << 6)
1847 #define HF_SMM_INSIDE_NMI_MASK (1 << 7)
1848
1849 #define __KVM_VCPU_MULTIPLE_ADDRESS_SPACE
1850 #define KVM_ADDRESS_SPACE_NUM 2
1851
1852 #define kvm_arch_vcpu_memslots_id(vcpu) ((vcpu)->arch.hflags & HF_SMM_MASK ? 1 : 0)
1853 #define kvm_memslots_for_spte_role(kvm, role) __kvm_memslots(kvm, (role).smm)
1854
1855 #define KVM_ARCH_WANT_MMU_NOTIFIER
1856
1857 int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v);
1858 int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu);
1859 int kvm_cpu_has_extint(struct kvm_vcpu *v);
1860 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu);
1861 int kvm_cpu_get_interrupt(struct kvm_vcpu *v);
1862 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event);
1863 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu);
1864
1865 int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low,
1866 unsigned long ipi_bitmap_high, u32 min,
1867 unsigned long icr, int op_64_bit);
1868
1869 int kvm_add_user_return_msr(u32 msr);
1870 int kvm_find_user_return_msr(u32 msr);
1871 int kvm_set_user_return_msr(unsigned index, u64 val, u64 mask);
1872
kvm_is_supported_user_return_msr(u32 msr)1873 static inline bool kvm_is_supported_user_return_msr(u32 msr)
1874 {
1875 return kvm_find_user_return_msr(msr) >= 0;
1876 }
1877
1878 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc, u64 ratio);
1879 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc);
1880 u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier);
1881 u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier);
1882
1883 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu);
1884 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip);
1885
1886 void kvm_make_mclock_inprogress_request(struct kvm *kvm);
1887 void kvm_make_scan_ioapic_request(struct kvm *kvm);
1888 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
1889 unsigned long *vcpu_bitmap);
1890
1891 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
1892 struct kvm_async_pf *work);
1893 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
1894 struct kvm_async_pf *work);
1895 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu,
1896 struct kvm_async_pf *work);
1897 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu);
1898 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu);
1899 extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn);
1900
1901 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu);
1902 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err);
1903 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu);
1904
1905 void __user *__x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa,
1906 u32 size);
1907 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu);
1908 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu);
1909
1910 bool kvm_intr_is_single_vcpu(struct kvm *kvm, struct kvm_lapic_irq *irq,
1911 struct kvm_vcpu **dest_vcpu);
1912
1913 void kvm_set_msi_irq(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
1914 struct kvm_lapic_irq *irq);
1915
kvm_irq_is_postable(struct kvm_lapic_irq * irq)1916 static inline bool kvm_irq_is_postable(struct kvm_lapic_irq *irq)
1917 {
1918 /* We can only post Fixed and LowPrio IRQs */
1919 return (irq->delivery_mode == APIC_DM_FIXED ||
1920 irq->delivery_mode == APIC_DM_LOWEST);
1921 }
1922
kvm_arch_vcpu_blocking(struct kvm_vcpu * vcpu)1923 static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu)
1924 {
1925 static_call_cond(kvm_x86_vcpu_blocking)(vcpu);
1926 }
1927
kvm_arch_vcpu_unblocking(struct kvm_vcpu * vcpu)1928 static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu)
1929 {
1930 static_call_cond(kvm_x86_vcpu_unblocking)(vcpu);
1931 }
1932
kvm_arch_vcpu_block_finish(struct kvm_vcpu * vcpu)1933 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
1934
kvm_cpu_get_apicid(int mps_cpu)1935 static inline int kvm_cpu_get_apicid(int mps_cpu)
1936 {
1937 #ifdef CONFIG_X86_LOCAL_APIC
1938 return default_cpu_present_to_apicid(mps_cpu);
1939 #else
1940 WARN_ON_ONCE(1);
1941 return BAD_APICID;
1942 #endif
1943 }
1944
1945 #define put_smstate(type, buf, offset, val) \
1946 *(type *)((buf) + (offset) - 0x7e00) = val
1947
1948 #define GET_SMSTATE(type, buf, offset) \
1949 (*(type *)((buf) + (offset) - 0x7e00))
1950
1951 int kvm_cpu_dirty_log_size(void);
1952
1953 int alloc_all_memslots_rmaps(struct kvm *kvm);
1954
1955 #endif /* _ASM_X86_KVM_HOST_H */
1956