1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * MHI PCI driver - MHI over PCI controller driver
4 *
5 * This module is a generic driver for registering MHI-over-PCI devices,
6 * such as PCIe QCOM modems.
7 *
8 * Copyright (C) 2020 Linaro Ltd <loic.poulain@linaro.org>
9 */
10
11 #include <linux/aer.h>
12 #include <linux/delay.h>
13 #include <linux/device.h>
14 #include <linux/mhi.h>
15 #include <linux/module.h>
16 #include <linux/pci.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/timer.h>
19 #include <linux/workqueue.h>
20
21 #define MHI_PCI_DEFAULT_BAR_NUM 0
22
23 #define MHI_POST_RESET_DELAY_MS 2000
24
25 #define HEALTH_CHECK_PERIOD (HZ * 2)
26
27 /**
28 * struct mhi_pci_dev_info - MHI PCI device specific information
29 * @config: MHI controller configuration
30 * @name: name of the PCI module
31 * @fw: firmware path (if any)
32 * @edl: emergency download mode firmware path (if any)
33 * @bar_num: PCI base address register to use for MHI MMIO register space
34 * @dma_data_width: DMA transfer word size (32 or 64 bits)
35 * @mru_default: default MRU size for MBIM network packets
36 * @sideband_wake: Devices using dedicated sideband GPIO for wakeup instead
37 * of inband wake support (such as sdx24)
38 */
39 struct mhi_pci_dev_info {
40 const struct mhi_controller_config *config;
41 const char *name;
42 const char *fw;
43 const char *edl;
44 unsigned int bar_num;
45 unsigned int dma_data_width;
46 unsigned int mru_default;
47 bool sideband_wake;
48 };
49
50 #define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name, el_count, ev_ring) \
51 { \
52 .num = ch_num, \
53 .name = ch_name, \
54 .num_elements = el_count, \
55 .event_ring = ev_ring, \
56 .dir = DMA_TO_DEVICE, \
57 .ee_mask = BIT(MHI_EE_AMSS), \
58 .pollcfg = 0, \
59 .doorbell = MHI_DB_BRST_DISABLE, \
60 .lpm_notify = false, \
61 .offload_channel = false, \
62 .doorbell_mode_switch = false, \
63 } \
64
65 #define MHI_CHANNEL_CONFIG_DL(ch_num, ch_name, el_count, ev_ring) \
66 { \
67 .num = ch_num, \
68 .name = ch_name, \
69 .num_elements = el_count, \
70 .event_ring = ev_ring, \
71 .dir = DMA_FROM_DEVICE, \
72 .ee_mask = BIT(MHI_EE_AMSS), \
73 .pollcfg = 0, \
74 .doorbell = MHI_DB_BRST_DISABLE, \
75 .lpm_notify = false, \
76 .offload_channel = false, \
77 .doorbell_mode_switch = false, \
78 }
79
80 #define MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(ch_num, ch_name, el_count, ev_ring) \
81 { \
82 .num = ch_num, \
83 .name = ch_name, \
84 .num_elements = el_count, \
85 .event_ring = ev_ring, \
86 .dir = DMA_FROM_DEVICE, \
87 .ee_mask = BIT(MHI_EE_AMSS), \
88 .pollcfg = 0, \
89 .doorbell = MHI_DB_BRST_DISABLE, \
90 .lpm_notify = false, \
91 .offload_channel = false, \
92 .doorbell_mode_switch = false, \
93 .auto_queue = true, \
94 }
95
96 #define MHI_EVENT_CONFIG_CTRL(ev_ring, el_count) \
97 { \
98 .num_elements = el_count, \
99 .irq_moderation_ms = 0, \
100 .irq = (ev_ring) + 1, \
101 .priority = 1, \
102 .mode = MHI_DB_BRST_DISABLE, \
103 .data_type = MHI_ER_CTRL, \
104 .hardware_event = false, \
105 .client_managed = false, \
106 .offload_channel = false, \
107 }
108
109 #define MHI_CHANNEL_CONFIG_HW_UL(ch_num, ch_name, el_count, ev_ring) \
110 { \
111 .num = ch_num, \
112 .name = ch_name, \
113 .num_elements = el_count, \
114 .event_ring = ev_ring, \
115 .dir = DMA_TO_DEVICE, \
116 .ee_mask = BIT(MHI_EE_AMSS), \
117 .pollcfg = 0, \
118 .doorbell = MHI_DB_BRST_ENABLE, \
119 .lpm_notify = false, \
120 .offload_channel = false, \
121 .doorbell_mode_switch = true, \
122 } \
123
124 #define MHI_CHANNEL_CONFIG_HW_DL(ch_num, ch_name, el_count, ev_ring) \
125 { \
126 .num = ch_num, \
127 .name = ch_name, \
128 .num_elements = el_count, \
129 .event_ring = ev_ring, \
130 .dir = DMA_FROM_DEVICE, \
131 .ee_mask = BIT(MHI_EE_AMSS), \
132 .pollcfg = 0, \
133 .doorbell = MHI_DB_BRST_ENABLE, \
134 .lpm_notify = false, \
135 .offload_channel = false, \
136 .doorbell_mode_switch = true, \
137 }
138
139 #define MHI_CHANNEL_CONFIG_UL_SBL(ch_num, ch_name, el_count, ev_ring) \
140 { \
141 .num = ch_num, \
142 .name = ch_name, \
143 .num_elements = el_count, \
144 .event_ring = ev_ring, \
145 .dir = DMA_TO_DEVICE, \
146 .ee_mask = BIT(MHI_EE_SBL), \
147 .pollcfg = 0, \
148 .doorbell = MHI_DB_BRST_DISABLE, \
149 .lpm_notify = false, \
150 .offload_channel = false, \
151 .doorbell_mode_switch = false, \
152 } \
153
154 #define MHI_CHANNEL_CONFIG_DL_SBL(ch_num, ch_name, el_count, ev_ring) \
155 { \
156 .num = ch_num, \
157 .name = ch_name, \
158 .num_elements = el_count, \
159 .event_ring = ev_ring, \
160 .dir = DMA_FROM_DEVICE, \
161 .ee_mask = BIT(MHI_EE_SBL), \
162 .pollcfg = 0, \
163 .doorbell = MHI_DB_BRST_DISABLE, \
164 .lpm_notify = false, \
165 .offload_channel = false, \
166 .doorbell_mode_switch = false, \
167 }
168
169 #define MHI_CHANNEL_CONFIG_UL_FP(ch_num, ch_name, el_count, ev_ring) \
170 { \
171 .num = ch_num, \
172 .name = ch_name, \
173 .num_elements = el_count, \
174 .event_ring = ev_ring, \
175 .dir = DMA_TO_DEVICE, \
176 .ee_mask = BIT(MHI_EE_FP), \
177 .pollcfg = 0, \
178 .doorbell = MHI_DB_BRST_DISABLE, \
179 .lpm_notify = false, \
180 .offload_channel = false, \
181 .doorbell_mode_switch = false, \
182 } \
183
184 #define MHI_CHANNEL_CONFIG_DL_FP(ch_num, ch_name, el_count, ev_ring) \
185 { \
186 .num = ch_num, \
187 .name = ch_name, \
188 .num_elements = el_count, \
189 .event_ring = ev_ring, \
190 .dir = DMA_FROM_DEVICE, \
191 .ee_mask = BIT(MHI_EE_FP), \
192 .pollcfg = 0, \
193 .doorbell = MHI_DB_BRST_DISABLE, \
194 .lpm_notify = false, \
195 .offload_channel = false, \
196 .doorbell_mode_switch = false, \
197 }
198
199 #define MHI_EVENT_CONFIG_DATA(ev_ring, el_count) \
200 { \
201 .num_elements = el_count, \
202 .irq_moderation_ms = 5, \
203 .irq = (ev_ring) + 1, \
204 .priority = 1, \
205 .mode = MHI_DB_BRST_DISABLE, \
206 .data_type = MHI_ER_DATA, \
207 .hardware_event = false, \
208 .client_managed = false, \
209 .offload_channel = false, \
210 }
211
212 #define MHI_EVENT_CONFIG_HW_DATA(ev_ring, el_count, ch_num) \
213 { \
214 .num_elements = el_count, \
215 .irq_moderation_ms = 1, \
216 .irq = (ev_ring) + 1, \
217 .priority = 1, \
218 .mode = MHI_DB_BRST_DISABLE, \
219 .data_type = MHI_ER_DATA, \
220 .hardware_event = true, \
221 .client_managed = false, \
222 .offload_channel = false, \
223 .channel = ch_num, \
224 }
225
226 static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = {
227 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 16, 1),
228 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 16, 1),
229 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 4, 0),
230 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 4, 0),
231 MHI_CHANNEL_CONFIG_UL(14, "QMI", 4, 0),
232 MHI_CHANNEL_CONFIG_DL(15, "QMI", 4, 0),
233 MHI_CHANNEL_CONFIG_UL(20, "IPCR", 8, 0),
234 MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(21, "IPCR", 8, 0),
235 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0),
236 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0),
237 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 2),
238 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 3),
239 };
240
241 static struct mhi_event_config modem_qcom_v1_mhi_events[] = {
242 /* first ring is control+data ring */
243 MHI_EVENT_CONFIG_CTRL(0, 64),
244 /* DIAG dedicated event ring */
245 MHI_EVENT_CONFIG_DATA(1, 128),
246 /* Hardware channels request dedicated hardware event rings */
247 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
248 MHI_EVENT_CONFIG_HW_DATA(3, 2048, 101)
249 };
250
251 static const struct mhi_controller_config modem_qcom_v1_mhiv_config = {
252 .max_channels = 128,
253 .timeout_ms = 8000,
254 .num_channels = ARRAY_SIZE(modem_qcom_v1_mhi_channels),
255 .ch_cfg = modem_qcom_v1_mhi_channels,
256 .num_events = ARRAY_SIZE(modem_qcom_v1_mhi_events),
257 .event_cfg = modem_qcom_v1_mhi_events,
258 };
259
260 static const struct mhi_pci_dev_info mhi_qcom_sdx65_info = {
261 .name = "qcom-sdx65m",
262 .fw = "qcom/sdx65m/xbl.elf",
263 .edl = "qcom/sdx65m/edl.mbn",
264 .config = &modem_qcom_v1_mhiv_config,
265 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
266 .dma_data_width = 32,
267 .sideband_wake = false,
268 };
269
270 static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = {
271 .name = "qcom-sdx55m",
272 .fw = "qcom/sdx55m/sbl1.mbn",
273 .edl = "qcom/sdx55m/edl.mbn",
274 .config = &modem_qcom_v1_mhiv_config,
275 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
276 .dma_data_width = 32,
277 .mru_default = 32768,
278 .sideband_wake = false,
279 };
280
281 static const struct mhi_pci_dev_info mhi_qcom_sdx24_info = {
282 .name = "qcom-sdx24",
283 .edl = "qcom/prog_firehose_sdx24.mbn",
284 .config = &modem_qcom_v1_mhiv_config,
285 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
286 .dma_data_width = 32,
287 .sideband_wake = true,
288 };
289
290 static const struct mhi_channel_config mhi_quectel_em1xx_channels[] = {
291 MHI_CHANNEL_CONFIG_UL(0, "NMEA", 32, 0),
292 MHI_CHANNEL_CONFIG_DL(1, "NMEA", 32, 0),
293 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0),
294 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0),
295 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1),
296 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1),
297 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0),
298 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0),
299 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0),
300 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0),
301 /* The EDL firmware is a flash-programmer exposing firehose protocol */
302 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0),
303 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0),
304 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2),
305 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3),
306 };
307
308 static struct mhi_event_config mhi_quectel_em1xx_events[] = {
309 MHI_EVENT_CONFIG_CTRL(0, 128),
310 MHI_EVENT_CONFIG_DATA(1, 128),
311 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
312 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101)
313 };
314
315 static const struct mhi_controller_config modem_quectel_em1xx_config = {
316 .max_channels = 128,
317 .timeout_ms = 20000,
318 .num_channels = ARRAY_SIZE(mhi_quectel_em1xx_channels),
319 .ch_cfg = mhi_quectel_em1xx_channels,
320 .num_events = ARRAY_SIZE(mhi_quectel_em1xx_events),
321 .event_cfg = mhi_quectel_em1xx_events,
322 };
323
324 static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = {
325 .name = "quectel-em1xx",
326 .edl = "qcom/prog_firehose_sdx24.mbn",
327 .config = &modem_quectel_em1xx_config,
328 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
329 .dma_data_width = 32,
330 .mru_default = 32768,
331 .sideband_wake = true,
332 };
333
334 static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = {
335 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 0),
336 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 0),
337 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1),
338 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1),
339 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0),
340 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0),
341 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0),
342 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0),
343 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2),
344 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3),
345 };
346
347 static struct mhi_event_config mhi_foxconn_sdx55_events[] = {
348 MHI_EVENT_CONFIG_CTRL(0, 128),
349 MHI_EVENT_CONFIG_DATA(1, 128),
350 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
351 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101)
352 };
353
354 static const struct mhi_controller_config modem_foxconn_sdx55_config = {
355 .max_channels = 128,
356 .timeout_ms = 20000,
357 .num_channels = ARRAY_SIZE(mhi_foxconn_sdx55_channels),
358 .ch_cfg = mhi_foxconn_sdx55_channels,
359 .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events),
360 .event_cfg = mhi_foxconn_sdx55_events,
361 };
362
363 static const struct mhi_pci_dev_info mhi_foxconn_sdx55_info = {
364 .name = "foxconn-sdx55",
365 .fw = "qcom/sdx55m/sbl1.mbn",
366 .edl = "qcom/sdx55m/edl.mbn",
367 .config = &modem_foxconn_sdx55_config,
368 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
369 .dma_data_width = 32,
370 .mru_default = 32768,
371 .sideband_wake = false,
372 };
373
374 static const struct mhi_channel_config mhi_mv31_channels[] = {
375 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 64, 0),
376 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 64, 0),
377 /* MBIM Control Channel */
378 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 64, 0),
379 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 64, 0),
380 /* MBIM Data Channel */
381 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 512, 2),
382 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 512, 3),
383 };
384
385 static struct mhi_event_config mhi_mv31_events[] = {
386 MHI_EVENT_CONFIG_CTRL(0, 256),
387 MHI_EVENT_CONFIG_DATA(1, 256),
388 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
389 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101),
390 };
391
392 static const struct mhi_controller_config modem_mv31_config = {
393 .max_channels = 128,
394 .timeout_ms = 20000,
395 .num_channels = ARRAY_SIZE(mhi_mv31_channels),
396 .ch_cfg = mhi_mv31_channels,
397 .num_events = ARRAY_SIZE(mhi_mv31_events),
398 .event_cfg = mhi_mv31_events,
399 };
400
401 static const struct mhi_pci_dev_info mhi_mv31_info = {
402 .name = "cinterion-mv31",
403 .config = &modem_mv31_config,
404 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
405 .dma_data_width = 32,
406 .mru_default = 32768,
407 };
408
409 static const struct mhi_channel_config mhi_telit_fn980_hw_v1_channels[] = {
410 MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0),
411 MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0),
412 MHI_CHANNEL_CONFIG_UL(20, "IPCR", 16, 0),
413 MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(21, "IPCR", 16, 0),
414 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 1),
415 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 2),
416 };
417
418 static struct mhi_event_config mhi_telit_fn980_hw_v1_events[] = {
419 MHI_EVENT_CONFIG_CTRL(0, 128),
420 MHI_EVENT_CONFIG_HW_DATA(1, 1024, 100),
421 MHI_EVENT_CONFIG_HW_DATA(2, 2048, 101)
422 };
423
424 static struct mhi_controller_config modem_telit_fn980_hw_v1_config = {
425 .max_channels = 128,
426 .timeout_ms = 20000,
427 .num_channels = ARRAY_SIZE(mhi_telit_fn980_hw_v1_channels),
428 .ch_cfg = mhi_telit_fn980_hw_v1_channels,
429 .num_events = ARRAY_SIZE(mhi_telit_fn980_hw_v1_events),
430 .event_cfg = mhi_telit_fn980_hw_v1_events,
431 };
432
433 static const struct mhi_pci_dev_info mhi_telit_fn980_hw_v1_info = {
434 .name = "telit-fn980-hwv1",
435 .fw = "qcom/sdx55m/sbl1.mbn",
436 .edl = "qcom/sdx55m/edl.mbn",
437 .config = &modem_telit_fn980_hw_v1_config,
438 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
439 .dma_data_width = 32,
440 .mru_default = 32768,
441 .sideband_wake = false,
442 };
443
444 static const struct mhi_channel_config mhi_telit_fn990_channels[] = {
445 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0),
446 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0),
447 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 64, 1),
448 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 64, 1),
449 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0),
450 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0),
451 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0),
452 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0),
453 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2),
454 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3),
455 };
456
457 static struct mhi_event_config mhi_telit_fn990_events[] = {
458 MHI_EVENT_CONFIG_CTRL(0, 128),
459 MHI_EVENT_CONFIG_DATA(1, 128),
460 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
461 MHI_EVENT_CONFIG_HW_DATA(3, 2048, 101)
462 };
463
464 static const struct mhi_controller_config modem_telit_fn990_config = {
465 .max_channels = 128,
466 .timeout_ms = 20000,
467 .num_channels = ARRAY_SIZE(mhi_telit_fn990_channels),
468 .ch_cfg = mhi_telit_fn990_channels,
469 .num_events = ARRAY_SIZE(mhi_telit_fn990_events),
470 .event_cfg = mhi_telit_fn990_events,
471 };
472
473 static const struct mhi_pci_dev_info mhi_telit_fn990_info = {
474 .name = "telit-fn990",
475 .config = &modem_telit_fn990_config,
476 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
477 .dma_data_width = 32,
478 .sideband_wake = false,
479 .mru_default = 32768,
480 };
481
482 static const struct pci_device_id mhi_pci_id_table[] = {
483 /* Telit FN980 hardware revision v1 */
484 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, 0x1C5D, 0x2000),
485 .driver_data = (kernel_ulong_t) &mhi_telit_fn980_hw_v1_info },
486 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306),
487 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info },
488 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0304),
489 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx24_info },
490 /* Telit FN990 */
491 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, 0x1c5d, 0x2010),
492 .driver_data = (kernel_ulong_t) &mhi_telit_fn990_info },
493 { PCI_DEVICE(0x1eac, 0x1001), /* EM120R-GL (sdx24) */
494 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
495 { PCI_DEVICE(0x1eac, 0x1002), /* EM160R-GL (sdx24) */
496 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
497 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0308),
498 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx65_info },
499 /* T99W175 (sdx55), Both for eSIM and Non-eSIM */
500 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0ab),
501 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
502 /* DW5930e (sdx55), With eSIM, It's also T99W175 */
503 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b0),
504 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
505 /* DW5930e (sdx55), Non-eSIM, It's also T99W175 */
506 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b1),
507 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
508 /* MV31-W (Cinterion) */
509 { PCI_DEVICE(0x1269, 0x00b3),
510 .driver_data = (kernel_ulong_t) &mhi_mv31_info },
511 { }
512 };
513 MODULE_DEVICE_TABLE(pci, mhi_pci_id_table);
514
515 enum mhi_pci_device_status {
516 MHI_PCI_DEV_STARTED,
517 MHI_PCI_DEV_SUSPENDED,
518 };
519
520 struct mhi_pci_device {
521 struct mhi_controller mhi_cntrl;
522 struct pci_saved_state *pci_state;
523 struct work_struct recovery_work;
524 struct timer_list health_check_timer;
525 unsigned long status;
526 };
527
mhi_pci_read_reg(struct mhi_controller * mhi_cntrl,void __iomem * addr,u32 * out)528 static int mhi_pci_read_reg(struct mhi_controller *mhi_cntrl,
529 void __iomem *addr, u32 *out)
530 {
531 *out = readl(addr);
532 return 0;
533 }
534
mhi_pci_write_reg(struct mhi_controller * mhi_cntrl,void __iomem * addr,u32 val)535 static void mhi_pci_write_reg(struct mhi_controller *mhi_cntrl,
536 void __iomem *addr, u32 val)
537 {
538 writel(val, addr);
539 }
540
mhi_pci_status_cb(struct mhi_controller * mhi_cntrl,enum mhi_callback cb)541 static void mhi_pci_status_cb(struct mhi_controller *mhi_cntrl,
542 enum mhi_callback cb)
543 {
544 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
545
546 /* Nothing to do for now */
547 switch (cb) {
548 case MHI_CB_FATAL_ERROR:
549 case MHI_CB_SYS_ERROR:
550 dev_warn(&pdev->dev, "firmware crashed (%u)\n", cb);
551 pm_runtime_forbid(&pdev->dev);
552 break;
553 case MHI_CB_EE_MISSION_MODE:
554 pm_runtime_allow(&pdev->dev);
555 break;
556 default:
557 break;
558 }
559 }
560
mhi_pci_wake_get_nop(struct mhi_controller * mhi_cntrl,bool force)561 static void mhi_pci_wake_get_nop(struct mhi_controller *mhi_cntrl, bool force)
562 {
563 /* no-op */
564 }
565
mhi_pci_wake_put_nop(struct mhi_controller * mhi_cntrl,bool override)566 static void mhi_pci_wake_put_nop(struct mhi_controller *mhi_cntrl, bool override)
567 {
568 /* no-op */
569 }
570
mhi_pci_wake_toggle_nop(struct mhi_controller * mhi_cntrl)571 static void mhi_pci_wake_toggle_nop(struct mhi_controller *mhi_cntrl)
572 {
573 /* no-op */
574 }
575
mhi_pci_is_alive(struct mhi_controller * mhi_cntrl)576 static bool mhi_pci_is_alive(struct mhi_controller *mhi_cntrl)
577 {
578 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
579 u16 vendor = 0;
580
581 if (pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor))
582 return false;
583
584 if (vendor == (u16) ~0 || vendor == 0)
585 return false;
586
587 return true;
588 }
589
mhi_pci_claim(struct mhi_controller * mhi_cntrl,unsigned int bar_num,u64 dma_mask)590 static int mhi_pci_claim(struct mhi_controller *mhi_cntrl,
591 unsigned int bar_num, u64 dma_mask)
592 {
593 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
594 int err;
595
596 err = pci_assign_resource(pdev, bar_num);
597 if (err)
598 return err;
599
600 err = pcim_enable_device(pdev);
601 if (err) {
602 dev_err(&pdev->dev, "failed to enable pci device: %d\n", err);
603 return err;
604 }
605
606 err = pcim_iomap_regions(pdev, 1 << bar_num, pci_name(pdev));
607 if (err) {
608 dev_err(&pdev->dev, "failed to map pci region: %d\n", err);
609 return err;
610 }
611 mhi_cntrl->regs = pcim_iomap_table(pdev)[bar_num];
612 mhi_cntrl->reg_len = pci_resource_len(pdev, bar_num);
613
614 err = pci_set_dma_mask(pdev, dma_mask);
615 if (err) {
616 dev_err(&pdev->dev, "Cannot set proper DMA mask\n");
617 return err;
618 }
619
620 err = pci_set_consistent_dma_mask(pdev, dma_mask);
621 if (err) {
622 dev_err(&pdev->dev, "set consistent dma mask failed\n");
623 return err;
624 }
625
626 pci_set_master(pdev);
627
628 return 0;
629 }
630
mhi_pci_get_irqs(struct mhi_controller * mhi_cntrl,const struct mhi_controller_config * mhi_cntrl_config)631 static int mhi_pci_get_irqs(struct mhi_controller *mhi_cntrl,
632 const struct mhi_controller_config *mhi_cntrl_config)
633 {
634 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
635 int nr_vectors, i;
636 int *irq;
637
638 /*
639 * Alloc one MSI vector for BHI + one vector per event ring, ideally...
640 * No explicit pci_free_irq_vectors required, done by pcim_release.
641 */
642 mhi_cntrl->nr_irqs = 1 + mhi_cntrl_config->num_events;
643
644 nr_vectors = pci_alloc_irq_vectors(pdev, 1, mhi_cntrl->nr_irqs, PCI_IRQ_MSI);
645 if (nr_vectors < 0) {
646 dev_err(&pdev->dev, "Error allocating MSI vectors %d\n",
647 nr_vectors);
648 return nr_vectors;
649 }
650
651 if (nr_vectors < mhi_cntrl->nr_irqs) {
652 dev_warn(&pdev->dev, "using shared MSI\n");
653
654 /* Patch msi vectors, use only one (shared) */
655 for (i = 0; i < mhi_cntrl_config->num_events; i++)
656 mhi_cntrl_config->event_cfg[i].irq = 0;
657 mhi_cntrl->nr_irqs = 1;
658 }
659
660 irq = devm_kcalloc(&pdev->dev, mhi_cntrl->nr_irqs, sizeof(int), GFP_KERNEL);
661 if (!irq)
662 return -ENOMEM;
663
664 for (i = 0; i < mhi_cntrl->nr_irqs; i++) {
665 int vector = i >= nr_vectors ? (nr_vectors - 1) : i;
666
667 irq[i] = pci_irq_vector(pdev, vector);
668 }
669
670 mhi_cntrl->irq = irq;
671
672 return 0;
673 }
674
mhi_pci_runtime_get(struct mhi_controller * mhi_cntrl)675 static int mhi_pci_runtime_get(struct mhi_controller *mhi_cntrl)
676 {
677 /* The runtime_get() MHI callback means:
678 * Do whatever is requested to leave M3.
679 */
680 return pm_runtime_get(mhi_cntrl->cntrl_dev);
681 }
682
mhi_pci_runtime_put(struct mhi_controller * mhi_cntrl)683 static void mhi_pci_runtime_put(struct mhi_controller *mhi_cntrl)
684 {
685 /* The runtime_put() MHI callback means:
686 * Device can be moved in M3 state.
687 */
688 pm_runtime_mark_last_busy(mhi_cntrl->cntrl_dev);
689 pm_runtime_put(mhi_cntrl->cntrl_dev);
690 }
691
mhi_pci_recovery_work(struct work_struct * work)692 static void mhi_pci_recovery_work(struct work_struct *work)
693 {
694 struct mhi_pci_device *mhi_pdev = container_of(work, struct mhi_pci_device,
695 recovery_work);
696 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
697 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
698 int err;
699
700 dev_warn(&pdev->dev, "device recovery started\n");
701
702 del_timer(&mhi_pdev->health_check_timer);
703 pm_runtime_forbid(&pdev->dev);
704
705 /* Clean up MHI state */
706 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
707 mhi_power_down(mhi_cntrl, false);
708 mhi_unprepare_after_power_down(mhi_cntrl);
709 }
710
711 pci_set_power_state(pdev, PCI_D0);
712 pci_load_saved_state(pdev, mhi_pdev->pci_state);
713 pci_restore_state(pdev);
714
715 if (!mhi_pci_is_alive(mhi_cntrl))
716 goto err_try_reset;
717
718 err = mhi_prepare_for_power_up(mhi_cntrl);
719 if (err)
720 goto err_try_reset;
721
722 err = mhi_sync_power_up(mhi_cntrl);
723 if (err)
724 goto err_unprepare;
725
726 dev_dbg(&pdev->dev, "Recovery completed\n");
727
728 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status);
729 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
730 return;
731
732 err_unprepare:
733 mhi_unprepare_after_power_down(mhi_cntrl);
734 err_try_reset:
735 if (pci_reset_function(pdev))
736 dev_err(&pdev->dev, "Recovery failed\n");
737 }
738
health_check(struct timer_list * t)739 static void health_check(struct timer_list *t)
740 {
741 struct mhi_pci_device *mhi_pdev = from_timer(mhi_pdev, t, health_check_timer);
742 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
743
744 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) ||
745 test_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status))
746 return;
747
748 if (!mhi_pci_is_alive(mhi_cntrl)) {
749 dev_err(mhi_cntrl->cntrl_dev, "Device died\n");
750 queue_work(system_long_wq, &mhi_pdev->recovery_work);
751 return;
752 }
753
754 /* reschedule in two seconds */
755 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
756 }
757
mhi_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)758 static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
759 {
760 const struct mhi_pci_dev_info *info = (struct mhi_pci_dev_info *) id->driver_data;
761 const struct mhi_controller_config *mhi_cntrl_config;
762 struct mhi_pci_device *mhi_pdev;
763 struct mhi_controller *mhi_cntrl;
764 int err;
765
766 dev_dbg(&pdev->dev, "MHI PCI device found: %s\n", info->name);
767
768 /* mhi_pdev.mhi_cntrl must be zero-initialized */
769 mhi_pdev = devm_kzalloc(&pdev->dev, sizeof(*mhi_pdev), GFP_KERNEL);
770 if (!mhi_pdev)
771 return -ENOMEM;
772
773 INIT_WORK(&mhi_pdev->recovery_work, mhi_pci_recovery_work);
774 timer_setup(&mhi_pdev->health_check_timer, health_check, 0);
775
776 mhi_cntrl_config = info->config;
777 mhi_cntrl = &mhi_pdev->mhi_cntrl;
778
779 mhi_cntrl->cntrl_dev = &pdev->dev;
780 mhi_cntrl->iova_start = 0;
781 mhi_cntrl->iova_stop = (dma_addr_t)DMA_BIT_MASK(info->dma_data_width);
782 mhi_cntrl->fw_image = info->fw;
783 mhi_cntrl->edl_image = info->edl;
784
785 mhi_cntrl->read_reg = mhi_pci_read_reg;
786 mhi_cntrl->write_reg = mhi_pci_write_reg;
787 mhi_cntrl->status_cb = mhi_pci_status_cb;
788 mhi_cntrl->runtime_get = mhi_pci_runtime_get;
789 mhi_cntrl->runtime_put = mhi_pci_runtime_put;
790 mhi_cntrl->mru = info->mru_default;
791
792 if (info->sideband_wake) {
793 mhi_cntrl->wake_get = mhi_pci_wake_get_nop;
794 mhi_cntrl->wake_put = mhi_pci_wake_put_nop;
795 mhi_cntrl->wake_toggle = mhi_pci_wake_toggle_nop;
796 }
797
798 err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(info->dma_data_width));
799 if (err)
800 return err;
801
802 err = mhi_pci_get_irqs(mhi_cntrl, mhi_cntrl_config);
803 if (err)
804 return err;
805
806 pci_set_drvdata(pdev, mhi_pdev);
807
808 /* Have stored pci confspace at hand for restore in sudden PCI error.
809 * cache the state locally and discard the PCI core one.
810 */
811 pci_save_state(pdev);
812 mhi_pdev->pci_state = pci_store_saved_state(pdev);
813 pci_load_saved_state(pdev, NULL);
814
815 pci_enable_pcie_error_reporting(pdev);
816
817 err = mhi_register_controller(mhi_cntrl, mhi_cntrl_config);
818 if (err)
819 goto err_disable_reporting;
820
821 /* MHI bus does not power up the controller by default */
822 err = mhi_prepare_for_power_up(mhi_cntrl);
823 if (err) {
824 dev_err(&pdev->dev, "failed to prepare MHI controller\n");
825 goto err_unregister;
826 }
827
828 err = mhi_sync_power_up(mhi_cntrl);
829 if (err) {
830 dev_err(&pdev->dev, "failed to power up MHI controller\n");
831 goto err_unprepare;
832 }
833
834 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status);
835
836 /* start health check */
837 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
838
839 /* Only allow runtime-suspend if PME capable (for wakeup) */
840 if (pci_pme_capable(pdev, PCI_D3hot)) {
841 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
842 pm_runtime_use_autosuspend(&pdev->dev);
843 pm_runtime_mark_last_busy(&pdev->dev);
844 pm_runtime_put_noidle(&pdev->dev);
845 }
846
847 return 0;
848
849 err_unprepare:
850 mhi_unprepare_after_power_down(mhi_cntrl);
851 err_unregister:
852 mhi_unregister_controller(mhi_cntrl);
853 err_disable_reporting:
854 pci_disable_pcie_error_reporting(pdev);
855
856 return err;
857 }
858
mhi_pci_remove(struct pci_dev * pdev)859 static void mhi_pci_remove(struct pci_dev *pdev)
860 {
861 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
862 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
863
864 del_timer_sync(&mhi_pdev->health_check_timer);
865 cancel_work_sync(&mhi_pdev->recovery_work);
866
867 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
868 mhi_power_down(mhi_cntrl, true);
869 mhi_unprepare_after_power_down(mhi_cntrl);
870 }
871
872 /* balancing probe put_noidle */
873 if (pci_pme_capable(pdev, PCI_D3hot))
874 pm_runtime_get_noresume(&pdev->dev);
875
876 mhi_unregister_controller(mhi_cntrl);
877 pci_disable_pcie_error_reporting(pdev);
878 }
879
mhi_pci_shutdown(struct pci_dev * pdev)880 static void mhi_pci_shutdown(struct pci_dev *pdev)
881 {
882 mhi_pci_remove(pdev);
883 pci_set_power_state(pdev, PCI_D3hot);
884 }
885
mhi_pci_reset_prepare(struct pci_dev * pdev)886 static void mhi_pci_reset_prepare(struct pci_dev *pdev)
887 {
888 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
889 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
890
891 dev_info(&pdev->dev, "reset\n");
892
893 del_timer(&mhi_pdev->health_check_timer);
894
895 /* Clean up MHI state */
896 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
897 mhi_power_down(mhi_cntrl, false);
898 mhi_unprepare_after_power_down(mhi_cntrl);
899 }
900
901 /* cause internal device reset */
902 mhi_soc_reset(mhi_cntrl);
903
904 /* Be sure device reset has been executed */
905 msleep(MHI_POST_RESET_DELAY_MS);
906 }
907
mhi_pci_reset_done(struct pci_dev * pdev)908 static void mhi_pci_reset_done(struct pci_dev *pdev)
909 {
910 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
911 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
912 int err;
913
914 /* Restore initial known working PCI state */
915 pci_load_saved_state(pdev, mhi_pdev->pci_state);
916 pci_restore_state(pdev);
917
918 /* Is device status available ? */
919 if (!mhi_pci_is_alive(mhi_cntrl)) {
920 dev_err(&pdev->dev, "reset failed\n");
921 return;
922 }
923
924 err = mhi_prepare_for_power_up(mhi_cntrl);
925 if (err) {
926 dev_err(&pdev->dev, "failed to prepare MHI controller\n");
927 return;
928 }
929
930 err = mhi_sync_power_up(mhi_cntrl);
931 if (err) {
932 dev_err(&pdev->dev, "failed to power up MHI controller\n");
933 mhi_unprepare_after_power_down(mhi_cntrl);
934 return;
935 }
936
937 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status);
938 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
939 }
940
mhi_pci_error_detected(struct pci_dev * pdev,pci_channel_state_t state)941 static pci_ers_result_t mhi_pci_error_detected(struct pci_dev *pdev,
942 pci_channel_state_t state)
943 {
944 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
945 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
946
947 dev_err(&pdev->dev, "PCI error detected, state = %u\n", state);
948
949 if (state == pci_channel_io_perm_failure)
950 return PCI_ERS_RESULT_DISCONNECT;
951
952 /* Clean up MHI state */
953 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
954 mhi_power_down(mhi_cntrl, false);
955 mhi_unprepare_after_power_down(mhi_cntrl);
956 } else {
957 /* Nothing to do */
958 return PCI_ERS_RESULT_RECOVERED;
959 }
960
961 pci_disable_device(pdev);
962
963 return PCI_ERS_RESULT_NEED_RESET;
964 }
965
mhi_pci_slot_reset(struct pci_dev * pdev)966 static pci_ers_result_t mhi_pci_slot_reset(struct pci_dev *pdev)
967 {
968 if (pci_enable_device(pdev)) {
969 dev_err(&pdev->dev, "Cannot re-enable PCI device after reset.\n");
970 return PCI_ERS_RESULT_DISCONNECT;
971 }
972
973 return PCI_ERS_RESULT_RECOVERED;
974 }
975
mhi_pci_io_resume(struct pci_dev * pdev)976 static void mhi_pci_io_resume(struct pci_dev *pdev)
977 {
978 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
979
980 dev_err(&pdev->dev, "PCI slot reset done\n");
981
982 queue_work(system_long_wq, &mhi_pdev->recovery_work);
983 }
984
985 static const struct pci_error_handlers mhi_pci_err_handler = {
986 .error_detected = mhi_pci_error_detected,
987 .slot_reset = mhi_pci_slot_reset,
988 .resume = mhi_pci_io_resume,
989 .reset_prepare = mhi_pci_reset_prepare,
990 .reset_done = mhi_pci_reset_done,
991 };
992
mhi_pci_runtime_suspend(struct device * dev)993 static int __maybe_unused mhi_pci_runtime_suspend(struct device *dev)
994 {
995 struct pci_dev *pdev = to_pci_dev(dev);
996 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev);
997 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
998 int err;
999
1000 if (test_and_set_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status))
1001 return 0;
1002
1003 del_timer(&mhi_pdev->health_check_timer);
1004 cancel_work_sync(&mhi_pdev->recovery_work);
1005
1006 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) ||
1007 mhi_cntrl->ee != MHI_EE_AMSS)
1008 goto pci_suspend; /* Nothing to do at MHI level */
1009
1010 /* Transition to M3 state */
1011 err = mhi_pm_suspend(mhi_cntrl);
1012 if (err) {
1013 dev_err(&pdev->dev, "failed to suspend device: %d\n", err);
1014 clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status);
1015 return -EBUSY;
1016 }
1017
1018 pci_suspend:
1019 pci_disable_device(pdev);
1020 pci_wake_from_d3(pdev, true);
1021
1022 return 0;
1023 }
1024
mhi_pci_runtime_resume(struct device * dev)1025 static int __maybe_unused mhi_pci_runtime_resume(struct device *dev)
1026 {
1027 struct pci_dev *pdev = to_pci_dev(dev);
1028 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev);
1029 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
1030 int err;
1031
1032 if (!test_and_clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status))
1033 return 0;
1034
1035 err = pci_enable_device(pdev);
1036 if (err)
1037 goto err_recovery;
1038
1039 pci_set_master(pdev);
1040 pci_wake_from_d3(pdev, false);
1041
1042 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) ||
1043 mhi_cntrl->ee != MHI_EE_AMSS)
1044 return 0; /* Nothing to do at MHI level */
1045
1046 /* Exit M3, transition to M0 state */
1047 err = mhi_pm_resume(mhi_cntrl);
1048 if (err) {
1049 dev_err(&pdev->dev, "failed to resume device: %d\n", err);
1050 goto err_recovery;
1051 }
1052
1053 /* Resume health check */
1054 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
1055
1056 /* It can be a remote wakeup (no mhi runtime_get), update access time */
1057 pm_runtime_mark_last_busy(dev);
1058
1059 return 0;
1060
1061 err_recovery:
1062 /* Do not fail to not mess up our PCI device state, the device likely
1063 * lost power (d3cold) and we simply need to reset it from the recovery
1064 * procedure, trigger the recovery asynchronously to prevent system
1065 * suspend exit delaying.
1066 */
1067 queue_work(system_long_wq, &mhi_pdev->recovery_work);
1068 pm_runtime_mark_last_busy(dev);
1069
1070 return 0;
1071 }
1072
mhi_pci_suspend(struct device * dev)1073 static int __maybe_unused mhi_pci_suspend(struct device *dev)
1074 {
1075 pm_runtime_disable(dev);
1076 return mhi_pci_runtime_suspend(dev);
1077 }
1078
mhi_pci_resume(struct device * dev)1079 static int __maybe_unused mhi_pci_resume(struct device *dev)
1080 {
1081 int ret;
1082
1083 /* Depending the platform, device may have lost power (d3cold), we need
1084 * to resume it now to check its state and recover when necessary.
1085 */
1086 ret = mhi_pci_runtime_resume(dev);
1087 pm_runtime_enable(dev);
1088
1089 return ret;
1090 }
1091
mhi_pci_freeze(struct device * dev)1092 static int __maybe_unused mhi_pci_freeze(struct device *dev)
1093 {
1094 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev);
1095 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
1096
1097 /* We want to stop all operations, hibernation does not guarantee that
1098 * device will be in the same state as before freezing, especially if
1099 * the intermediate restore kernel reinitializes MHI device with new
1100 * context.
1101 */
1102 flush_work(&mhi_pdev->recovery_work);
1103 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
1104 mhi_power_down(mhi_cntrl, true);
1105 mhi_unprepare_after_power_down(mhi_cntrl);
1106 }
1107
1108 return 0;
1109 }
1110
mhi_pci_restore(struct device * dev)1111 static int __maybe_unused mhi_pci_restore(struct device *dev)
1112 {
1113 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev);
1114
1115 /* Reinitialize the device */
1116 queue_work(system_long_wq, &mhi_pdev->recovery_work);
1117
1118 return 0;
1119 }
1120
1121 static const struct dev_pm_ops mhi_pci_pm_ops = {
1122 SET_RUNTIME_PM_OPS(mhi_pci_runtime_suspend, mhi_pci_runtime_resume, NULL)
1123 #ifdef CONFIG_PM_SLEEP
1124 .suspend = mhi_pci_suspend,
1125 .resume = mhi_pci_resume,
1126 .freeze = mhi_pci_freeze,
1127 .thaw = mhi_pci_restore,
1128 .poweroff = mhi_pci_freeze,
1129 .restore = mhi_pci_restore,
1130 #endif
1131 };
1132
1133 static struct pci_driver mhi_pci_driver = {
1134 .name = "mhi-pci-generic",
1135 .id_table = mhi_pci_id_table,
1136 .probe = mhi_pci_probe,
1137 .remove = mhi_pci_remove,
1138 .shutdown = mhi_pci_shutdown,
1139 .err_handler = &mhi_pci_err_handler,
1140 .driver.pm = &mhi_pci_pm_ops
1141 };
1142 module_pci_driver(mhi_pci_driver);
1143
1144 MODULE_AUTHOR("Loic Poulain <loic.poulain@linaro.org>");
1145 MODULE_DESCRIPTION("Modem Host Interface (MHI) PCI controller driver");
1146 MODULE_LICENSE("GPL");
1147