1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include <linux/firmware.h>
27 #include <linux/pci.h>
28 #include <linux/i2c.h>
29 #include "amdgpu.h"
30 #include "amdgpu_smu.h"
31 #include "atomfirmware.h"
32 #include "amdgpu_atomfirmware.h"
33 #include "amdgpu_atombios.h"
34 #include "smu_v11_0.h"
35 #include "smu11_driver_if_sienna_cichlid.h"
36 #include "soc15_common.h"
37 #include "atom.h"
38 #include "sienna_cichlid_ppt.h"
39 #include "smu_v11_0_7_pptable.h"
40 #include "smu_v11_0_7_ppsmc.h"
41 #include "nbio/nbio_2_3_offset.h"
42 #include "nbio/nbio_2_3_sh_mask.h"
43 #include "thm/thm_11_0_2_offset.h"
44 #include "thm/thm_11_0_2_sh_mask.h"
45 #include "mp/mp_11_0_offset.h"
46 #include "mp/mp_11_0_sh_mask.h"
47
48 #include "asic_reg/mp/mp_11_0_sh_mask.h"
49 #include "smu_cmn.h"
50
51 /*
52 * DO NOT use these for err/warn/info/debug messages.
53 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
54 * They are more MGPU friendly.
55 */
56 #undef pr_err
57 #undef pr_warn
58 #undef pr_info
59 #undef pr_debug
60
61 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
62
63 #define FEATURE_MASK(feature) (1ULL << feature)
64 #define SMC_DPM_FEATURE ( \
65 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
66 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
68 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
69 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
70 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
71 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | \
72 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
73
74 #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
75
76 #define GET_PPTABLE_MEMBER(field, member) do {\
77 if (smu->adev->asic_type == CHIP_BEIGE_GOBY)\
78 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field));\
79 else\
80 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\
81 } while(0)
82
get_table_size(struct smu_context * smu)83 static int get_table_size(struct smu_context *smu)
84 {
85 if (smu->adev->asic_type == CHIP_BEIGE_GOBY)
86 return sizeof(PPTable_beige_goby_t);
87 else
88 return sizeof(PPTable_t);
89 }
90
91 static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
92 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
93 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
94 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
95 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
96 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
97 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
98 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
99 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
100 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
101 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
102 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
103 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),
104 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),
105 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
106 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
107 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
108 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
109 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
110 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
111 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
112 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
113 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
114 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
115 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
116 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1),
117 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
118 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
119 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
120 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
121 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
122 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
123 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0),
124 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0),
125 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0),
126 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
127 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
128 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
129 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0),
130 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0),
131 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
132 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
133 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
134 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
135 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
136 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
137 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
138 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
139 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
140 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
141 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0),
142 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
143 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
144 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
145 MSG_MAP(SetGpoFeaturePMask, PPSMC_MSG_SetGpoFeaturePMask, 0),
146 MSG_MAP(DisallowGpo, PPSMC_MSG_DisallowGpo, 0),
147 MSG_MAP(Enable2ndUSB20Port, PPSMC_MSG_Enable2ndUSB20Port, 0),
148 };
149
150 static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
151 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
152 CLK_MAP(SCLK, PPCLK_GFXCLK),
153 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
154 CLK_MAP(FCLK, PPCLK_FCLK),
155 CLK_MAP(UCLK, PPCLK_UCLK),
156 CLK_MAP(MCLK, PPCLK_UCLK),
157 CLK_MAP(DCLK, PPCLK_DCLK_0),
158 CLK_MAP(DCLK1, PPCLK_DCLK_1),
159 CLK_MAP(VCLK, PPCLK_VCLK_0),
160 CLK_MAP(VCLK1, PPCLK_VCLK_1),
161 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
162 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
163 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
164 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
165 };
166
167 static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
168 FEA_MAP(DPM_PREFETCHER),
169 FEA_MAP(DPM_GFXCLK),
170 FEA_MAP(DPM_GFX_GPO),
171 FEA_MAP(DPM_UCLK),
172 FEA_MAP(DPM_FCLK),
173 FEA_MAP(DPM_SOCCLK),
174 FEA_MAP(DPM_MP0CLK),
175 FEA_MAP(DPM_LINK),
176 FEA_MAP(DPM_DCEFCLK),
177 FEA_MAP(DPM_XGMI),
178 FEA_MAP(MEM_VDDCI_SCALING),
179 FEA_MAP(MEM_MVDD_SCALING),
180 FEA_MAP(DS_GFXCLK),
181 FEA_MAP(DS_SOCCLK),
182 FEA_MAP(DS_FCLK),
183 FEA_MAP(DS_LCLK),
184 FEA_MAP(DS_DCEFCLK),
185 FEA_MAP(DS_UCLK),
186 FEA_MAP(GFX_ULV),
187 FEA_MAP(FW_DSTATE),
188 FEA_MAP(GFXOFF),
189 FEA_MAP(BACO),
190 FEA_MAP(MM_DPM_PG),
191 FEA_MAP(RSMU_SMN_CG),
192 FEA_MAP(PPT),
193 FEA_MAP(TDC),
194 FEA_MAP(APCC_PLUS),
195 FEA_MAP(GTHR),
196 FEA_MAP(ACDC),
197 FEA_MAP(VR0HOT),
198 FEA_MAP(VR1HOT),
199 FEA_MAP(FW_CTF),
200 FEA_MAP(FAN_CONTROL),
201 FEA_MAP(THERMAL),
202 FEA_MAP(GFX_DCS),
203 FEA_MAP(RM),
204 FEA_MAP(LED_DISPLAY),
205 FEA_MAP(GFX_SS),
206 FEA_MAP(OUT_OF_BAND_MONITOR),
207 FEA_MAP(TEMP_DEPENDENT_VMIN),
208 FEA_MAP(MMHUB_PG),
209 FEA_MAP(ATHUB_PG),
210 FEA_MAP(APCC_DFLL),
211 };
212
213 static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
214 TAB_MAP(PPTABLE),
215 TAB_MAP(WATERMARKS),
216 TAB_MAP(AVFS_PSM_DEBUG),
217 TAB_MAP(AVFS_FUSE_OVERRIDE),
218 TAB_MAP(PMSTATUSLOG),
219 TAB_MAP(SMU_METRICS),
220 TAB_MAP(DRIVER_SMU_CONFIG),
221 TAB_MAP(ACTIVITY_MONITOR_COEFF),
222 TAB_MAP(OVERDRIVE),
223 TAB_MAP(I2C_COMMANDS),
224 TAB_MAP(PACE),
225 };
226
227 static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
228 PWR_MAP(AC),
229 PWR_MAP(DC),
230 };
231
232 static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
233 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
234 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
235 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
236 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
237 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
238 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
239 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
240 };
241
242 static const uint8_t sienna_cichlid_throttler_map[] = {
243 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
244 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
245 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
246 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
247 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
248 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
249 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
250 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
251 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
252 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
253 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
254 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
255 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
256 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
257 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
258 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
259 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT),
260 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT),
261 };
262
263 static int
sienna_cichlid_get_allowed_feature_mask(struct smu_context * smu,uint32_t * feature_mask,uint32_t num)264 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
265 uint32_t *feature_mask, uint32_t num)
266 {
267 struct amdgpu_device *adev = smu->adev;
268
269 if (num > 2)
270 return -EINVAL;
271
272 memset(feature_mask, 0, sizeof(uint32_t) * num);
273
274 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
275 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
276 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
277 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
278 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
279 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
280 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
281 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
282 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
283 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
284 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
285 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
286 | FEATURE_MASK(FEATURE_PPT_BIT)
287 | FEATURE_MASK(FEATURE_TDC_BIT)
288 | FEATURE_MASK(FEATURE_BACO_BIT)
289 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
290 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
291 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
292 | FEATURE_MASK(FEATURE_THERMAL_BIT)
293 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
294
295 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
296 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
297 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
298 }
299
300 if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
301 (adev->asic_type > CHIP_SIENNA_CICHLID) &&
302 !(adev->flags & AMD_IS_APU))
303 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
304
305 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
306 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
307 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
308 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
309
310 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
311 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
312
313 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
314 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
315
316 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
317 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
318
319 if (adev->pm.pp_feature & PP_ULV_MASK)
320 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
321
322 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
323 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
324
325 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
326 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
327
328 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
329 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
330
331 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
332 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
333
334 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
335 smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
336 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
337
338 if (smu->dc_controlled_by_gpio)
339 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
340
341 if (amdgpu_device_should_use_aspm(adev))
342 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
343
344 return 0;
345 }
346
sienna_cichlid_check_bxco_support(struct smu_context * smu)347 static void sienna_cichlid_check_bxco_support(struct smu_context *smu)
348 {
349 struct smu_table_context *table_context = &smu->smu_table;
350 struct smu_11_0_7_powerplay_table *powerplay_table =
351 table_context->power_play_table;
352 struct smu_baco_context *smu_baco = &smu->smu_baco;
353 struct amdgpu_device *adev = smu->adev;
354 uint32_t val;
355
356 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO) {
357 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
358 smu_baco->platform_support =
359 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
360 false;
361
362 /*
363 * Disable BACO entry/exit completely on below SKUs to
364 * avoid hardware intermittent failures.
365 */
366 if (((adev->pdev->device == 0x73A1) &&
367 (adev->pdev->revision == 0x00)) ||
368 ((adev->pdev->device == 0x73BF) &&
369 (adev->pdev->revision == 0xCF)) ||
370 ((adev->pdev->device == 0x7422) &&
371 (adev->pdev->revision == 0x00)) ||
372 ((adev->pdev->device == 0x73A3) &&
373 (adev->pdev->revision == 0x00)) ||
374 ((adev->pdev->device == 0x73E3) &&
375 (adev->pdev->revision == 0x00)))
376 smu_baco->platform_support = false;
377
378 }
379 }
380
sienna_cichlid_check_powerplay_table(struct smu_context * smu)381 static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
382 {
383 struct smu_table_context *table_context = &smu->smu_table;
384 struct smu_11_0_7_powerplay_table *powerplay_table =
385 table_context->power_play_table;
386
387 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC)
388 smu->dc_controlled_by_gpio = true;
389
390 sienna_cichlid_check_bxco_support(smu);
391
392 table_context->thermal_controller_type =
393 powerplay_table->thermal_controller_type;
394
395 /*
396 * Instead of having its own buffer space and get overdrive_table copied,
397 * smu->od_settings just points to the actual overdrive_table
398 */
399 smu->od_settings = &powerplay_table->overdrive_table;
400
401 return 0;
402 }
403
sienna_cichlid_append_powerplay_table(struct smu_context * smu)404 static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
405 {
406 struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
407 int index, ret;
408 I2cControllerConfig_t *table_member;
409
410 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
411 smc_dpm_info);
412
413 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
414 (uint8_t **)&smc_dpm_table);
415 if (ret)
416 return ret;
417 GET_PPTABLE_MEMBER(I2cControllers, &table_member);
418 memcpy(table_member, smc_dpm_table->I2cControllers,
419 sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
420
421 return 0;
422 }
423
sienna_cichlid_store_powerplay_table(struct smu_context * smu)424 static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
425 {
426 struct smu_table_context *table_context = &smu->smu_table;
427 struct smu_11_0_7_powerplay_table *powerplay_table =
428 table_context->power_play_table;
429 int table_size;
430
431 table_size = get_table_size(smu);
432 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
433 table_size);
434
435 return 0;
436 }
437
sienna_cichlid_patch_pptable_quirk(struct smu_context * smu)438 static int sienna_cichlid_patch_pptable_quirk(struct smu_context *smu)
439 {
440 struct amdgpu_device *adev = smu->adev;
441 uint32_t *board_reserved;
442 uint16_t *freq_table_gfx;
443 uint32_t i;
444
445 /* Fix some OEM SKU specific stability issues */
446 GET_PPTABLE_MEMBER(BoardReserved, &board_reserved);
447 if ((adev->pdev->device == 0x73DF) &&
448 (adev->pdev->revision == 0XC3) &&
449 (adev->pdev->subsystem_device == 0x16C2) &&
450 (adev->pdev->subsystem_vendor == 0x1043))
451 board_reserved[0] = 1387;
452
453 GET_PPTABLE_MEMBER(FreqTableGfx, &freq_table_gfx);
454 if ((adev->pdev->device == 0x73DF) &&
455 (adev->pdev->revision == 0XC3) &&
456 ((adev->pdev->subsystem_device == 0x16C2) ||
457 (adev->pdev->subsystem_device == 0x133C)) &&
458 (adev->pdev->subsystem_vendor == 0x1043)) {
459 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) {
460 if (freq_table_gfx[i] > 2500)
461 freq_table_gfx[i] = 2500;
462 }
463 }
464
465 return 0;
466 }
467
sienna_cichlid_setup_pptable(struct smu_context * smu)468 static int sienna_cichlid_setup_pptable(struct smu_context *smu)
469 {
470 int ret = 0;
471
472 ret = smu_v11_0_setup_pptable(smu);
473 if (ret)
474 return ret;
475
476 ret = sienna_cichlid_store_powerplay_table(smu);
477 if (ret)
478 return ret;
479
480 ret = sienna_cichlid_append_powerplay_table(smu);
481 if (ret)
482 return ret;
483
484 ret = sienna_cichlid_check_powerplay_table(smu);
485 if (ret)
486 return ret;
487
488 return sienna_cichlid_patch_pptable_quirk(smu);
489 }
490
sienna_cichlid_tables_init(struct smu_context * smu)491 static int sienna_cichlid_tables_init(struct smu_context *smu)
492 {
493 struct smu_table_context *smu_table = &smu->smu_table;
494 struct smu_table *tables = smu_table->tables;
495 int table_size;
496
497 table_size = get_table_size(smu);
498 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size,
499 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
500 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
501 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
502 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
503 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
504 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
505 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
506 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
507 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
508 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
509 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
510 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
511 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
512 AMDGPU_GEM_DOMAIN_VRAM);
513
514 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
515 if (!smu_table->metrics_table)
516 goto err0_out;
517 smu_table->metrics_time = 0;
518
519 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
520 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
521 if (!smu_table->gpu_metrics_table)
522 goto err1_out;
523
524 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
525 if (!smu_table->watermarks_table)
526 goto err2_out;
527
528 return 0;
529
530 err2_out:
531 kfree(smu_table->gpu_metrics_table);
532 err1_out:
533 kfree(smu_table->metrics_table);
534 err0_out:
535 return -ENOMEM;
536 }
537
sienna_cichlid_get_throttler_status_locked(struct smu_context * smu)538 static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *smu)
539 {
540 struct smu_table_context *smu_table= &smu->smu_table;
541 SmuMetricsExternal_t *metrics_ext =
542 (SmuMetricsExternal_t *)(smu_table->metrics_table);
543 uint32_t throttler_status = 0;
544 int i;
545
546 if ((smu->adev->asic_type == CHIP_SIENNA_CICHLID) &&
547 (smu->smc_fw_version >= 0x3A4300)) {
548 for (i = 0; i < THROTTLER_COUNT; i++)
549 throttler_status |=
550 (metrics_ext->SmuMetrics_V2.ThrottlingPercentage[i] ? 1U << i : 0);
551 } else {
552 throttler_status = metrics_ext->SmuMetrics.ThrottlerStatus;
553 }
554
555 return throttler_status;
556 }
557
sienna_cichlid_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)558 static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
559 MetricsMember_t member,
560 uint32_t *value)
561 {
562 struct smu_table_context *smu_table= &smu->smu_table;
563 SmuMetrics_t *metrics =
564 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
565 SmuMetrics_V2_t *metrics_v2 =
566 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2);
567 bool use_metrics_v2 = ((smu->adev->asic_type == CHIP_SIENNA_CICHLID) &&
568 (smu->smc_fw_version >= 0x3A4300)) ? true : false;
569 uint16_t average_gfx_activity;
570 int ret = 0;
571
572 mutex_lock(&smu->metrics_lock);
573
574 ret = smu_cmn_get_metrics_table_locked(smu,
575 NULL,
576 false);
577 if (ret) {
578 mutex_unlock(&smu->metrics_lock);
579 return ret;
580 }
581
582 switch (member) {
583 case METRICS_CURR_GFXCLK:
584 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] :
585 metrics->CurrClock[PPCLK_GFXCLK];
586 break;
587 case METRICS_CURR_SOCCLK:
588 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] :
589 metrics->CurrClock[PPCLK_SOCCLK];
590 break;
591 case METRICS_CURR_UCLK:
592 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] :
593 metrics->CurrClock[PPCLK_UCLK];
594 break;
595 case METRICS_CURR_VCLK:
596 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] :
597 metrics->CurrClock[PPCLK_VCLK_0];
598 break;
599 case METRICS_CURR_VCLK1:
600 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] :
601 metrics->CurrClock[PPCLK_VCLK_1];
602 break;
603 case METRICS_CURR_DCLK:
604 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] :
605 metrics->CurrClock[PPCLK_DCLK_0];
606 break;
607 case METRICS_CURR_DCLK1:
608 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] :
609 metrics->CurrClock[PPCLK_DCLK_1];
610 break;
611 case METRICS_CURR_DCEFCLK:
612 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCEFCLK] :
613 metrics->CurrClock[PPCLK_DCEFCLK];
614 break;
615 case METRICS_CURR_FCLK:
616 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_FCLK] :
617 metrics->CurrClock[PPCLK_FCLK];
618 break;
619 case METRICS_AVERAGE_GFXCLK:
620 average_gfx_activity = use_metrics_v2 ? metrics_v2->AverageGfxActivity :
621 metrics->AverageGfxActivity;
622 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
623 *value = use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
624 metrics->AverageGfxclkFrequencyPostDs;
625 else
626 *value = use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
627 metrics->AverageGfxclkFrequencyPreDs;
628 break;
629 case METRICS_AVERAGE_FCLK:
630 *value = use_metrics_v2 ? metrics_v2->AverageFclkFrequencyPostDs :
631 metrics->AverageFclkFrequencyPostDs;
632 break;
633 case METRICS_AVERAGE_UCLK:
634 *value = use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
635 metrics->AverageUclkFrequencyPostDs;
636 break;
637 case METRICS_AVERAGE_GFXACTIVITY:
638 *value = use_metrics_v2 ? metrics_v2->AverageGfxActivity :
639 metrics->AverageGfxActivity;
640 break;
641 case METRICS_AVERAGE_MEMACTIVITY:
642 *value = use_metrics_v2 ? metrics_v2->AverageUclkActivity :
643 metrics->AverageUclkActivity;
644 break;
645 case METRICS_AVERAGE_SOCKETPOWER:
646 *value = use_metrics_v2 ? metrics_v2->AverageSocketPower << 8 :
647 metrics->AverageSocketPower << 8;
648 break;
649 case METRICS_TEMPERATURE_EDGE:
650 *value = (use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge) *
651 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
652 break;
653 case METRICS_TEMPERATURE_HOTSPOT:
654 *value = (use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot) *
655 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
656 break;
657 case METRICS_TEMPERATURE_MEM:
658 *value = (use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem) *
659 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
660 break;
661 case METRICS_TEMPERATURE_VRGFX:
662 *value = (use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx) *
663 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
664 break;
665 case METRICS_TEMPERATURE_VRSOC:
666 *value = (use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc) *
667 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
668 break;
669 case METRICS_THROTTLER_STATUS:
670 *value = sienna_cichlid_get_throttler_status_locked(smu);
671 break;
672 case METRICS_CURR_FANSPEED:
673 *value = use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
674 break;
675 default:
676 *value = UINT_MAX;
677 break;
678 }
679
680 mutex_unlock(&smu->metrics_lock);
681
682 return ret;
683
684 }
685
sienna_cichlid_allocate_dpm_context(struct smu_context * smu)686 static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
687 {
688 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
689
690 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
691 GFP_KERNEL);
692 if (!smu_dpm->dpm_context)
693 return -ENOMEM;
694
695 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
696
697 return 0;
698 }
699
sienna_cichlid_init_smc_tables(struct smu_context * smu)700 static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
701 {
702 int ret = 0;
703
704 ret = sienna_cichlid_tables_init(smu);
705 if (ret)
706 return ret;
707
708 ret = sienna_cichlid_allocate_dpm_context(smu);
709 if (ret)
710 return ret;
711
712 return smu_v11_0_init_smc_tables(smu);
713 }
714
sienna_cichlid_set_default_dpm_table(struct smu_context * smu)715 static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
716 {
717 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
718 struct smu_11_0_dpm_table *dpm_table;
719 struct amdgpu_device *adev = smu->adev;
720 int ret = 0;
721 DpmDescriptor_t *table_member;
722
723 /* socclk dpm table setup */
724 dpm_table = &dpm_context->dpm_tables.soc_table;
725 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
726 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
727 ret = smu_v11_0_set_single_dpm_table(smu,
728 SMU_SOCCLK,
729 dpm_table);
730 if (ret)
731 return ret;
732 dpm_table->is_fine_grained =
733 !table_member[PPCLK_SOCCLK].SnapToDiscrete;
734 } else {
735 dpm_table->count = 1;
736 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
737 dpm_table->dpm_levels[0].enabled = true;
738 dpm_table->min = dpm_table->dpm_levels[0].value;
739 dpm_table->max = dpm_table->dpm_levels[0].value;
740 }
741
742 /* gfxclk dpm table setup */
743 dpm_table = &dpm_context->dpm_tables.gfx_table;
744 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
745 ret = smu_v11_0_set_single_dpm_table(smu,
746 SMU_GFXCLK,
747 dpm_table);
748 if (ret)
749 return ret;
750 dpm_table->is_fine_grained =
751 !table_member[PPCLK_GFXCLK].SnapToDiscrete;
752 } else {
753 dpm_table->count = 1;
754 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
755 dpm_table->dpm_levels[0].enabled = true;
756 dpm_table->min = dpm_table->dpm_levels[0].value;
757 dpm_table->max = dpm_table->dpm_levels[0].value;
758 }
759
760 /* uclk dpm table setup */
761 dpm_table = &dpm_context->dpm_tables.uclk_table;
762 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
763 ret = smu_v11_0_set_single_dpm_table(smu,
764 SMU_UCLK,
765 dpm_table);
766 if (ret)
767 return ret;
768 dpm_table->is_fine_grained =
769 !table_member[PPCLK_UCLK].SnapToDiscrete;
770 } else {
771 dpm_table->count = 1;
772 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
773 dpm_table->dpm_levels[0].enabled = true;
774 dpm_table->min = dpm_table->dpm_levels[0].value;
775 dpm_table->max = dpm_table->dpm_levels[0].value;
776 }
777
778 /* fclk dpm table setup */
779 dpm_table = &dpm_context->dpm_tables.fclk_table;
780 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
781 ret = smu_v11_0_set_single_dpm_table(smu,
782 SMU_FCLK,
783 dpm_table);
784 if (ret)
785 return ret;
786 dpm_table->is_fine_grained =
787 !table_member[PPCLK_FCLK].SnapToDiscrete;
788 } else {
789 dpm_table->count = 1;
790 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
791 dpm_table->dpm_levels[0].enabled = true;
792 dpm_table->min = dpm_table->dpm_levels[0].value;
793 dpm_table->max = dpm_table->dpm_levels[0].value;
794 }
795
796 /* vclk0 dpm table setup */
797 dpm_table = &dpm_context->dpm_tables.vclk_table;
798 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
799 ret = smu_v11_0_set_single_dpm_table(smu,
800 SMU_VCLK,
801 dpm_table);
802 if (ret)
803 return ret;
804 dpm_table->is_fine_grained =
805 !table_member[PPCLK_VCLK_0].SnapToDiscrete;
806 } else {
807 dpm_table->count = 1;
808 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
809 dpm_table->dpm_levels[0].enabled = true;
810 dpm_table->min = dpm_table->dpm_levels[0].value;
811 dpm_table->max = dpm_table->dpm_levels[0].value;
812 }
813
814 /* vclk1 dpm table setup */
815 if (adev->vcn.num_vcn_inst > 1) {
816 dpm_table = &dpm_context->dpm_tables.vclk1_table;
817 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
818 ret = smu_v11_0_set_single_dpm_table(smu,
819 SMU_VCLK1,
820 dpm_table);
821 if (ret)
822 return ret;
823 dpm_table->is_fine_grained =
824 !table_member[PPCLK_VCLK_1].SnapToDiscrete;
825 } else {
826 dpm_table->count = 1;
827 dpm_table->dpm_levels[0].value =
828 smu->smu_table.boot_values.vclk / 100;
829 dpm_table->dpm_levels[0].enabled = true;
830 dpm_table->min = dpm_table->dpm_levels[0].value;
831 dpm_table->max = dpm_table->dpm_levels[0].value;
832 }
833 }
834
835 /* dclk0 dpm table setup */
836 dpm_table = &dpm_context->dpm_tables.dclk_table;
837 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
838 ret = smu_v11_0_set_single_dpm_table(smu,
839 SMU_DCLK,
840 dpm_table);
841 if (ret)
842 return ret;
843 dpm_table->is_fine_grained =
844 !table_member[PPCLK_DCLK_0].SnapToDiscrete;
845 } else {
846 dpm_table->count = 1;
847 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
848 dpm_table->dpm_levels[0].enabled = true;
849 dpm_table->min = dpm_table->dpm_levels[0].value;
850 dpm_table->max = dpm_table->dpm_levels[0].value;
851 }
852
853 /* dclk1 dpm table setup */
854 if (adev->vcn.num_vcn_inst > 1) {
855 dpm_table = &dpm_context->dpm_tables.dclk1_table;
856 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
857 ret = smu_v11_0_set_single_dpm_table(smu,
858 SMU_DCLK1,
859 dpm_table);
860 if (ret)
861 return ret;
862 dpm_table->is_fine_grained =
863 !table_member[PPCLK_DCLK_1].SnapToDiscrete;
864 } else {
865 dpm_table->count = 1;
866 dpm_table->dpm_levels[0].value =
867 smu->smu_table.boot_values.dclk / 100;
868 dpm_table->dpm_levels[0].enabled = true;
869 dpm_table->min = dpm_table->dpm_levels[0].value;
870 dpm_table->max = dpm_table->dpm_levels[0].value;
871 }
872 }
873
874 /* dcefclk dpm table setup */
875 dpm_table = &dpm_context->dpm_tables.dcef_table;
876 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
877 ret = smu_v11_0_set_single_dpm_table(smu,
878 SMU_DCEFCLK,
879 dpm_table);
880 if (ret)
881 return ret;
882 dpm_table->is_fine_grained =
883 !table_member[PPCLK_DCEFCLK].SnapToDiscrete;
884 } else {
885 dpm_table->count = 1;
886 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
887 dpm_table->dpm_levels[0].enabled = true;
888 dpm_table->min = dpm_table->dpm_levels[0].value;
889 dpm_table->max = dpm_table->dpm_levels[0].value;
890 }
891
892 /* pixelclk dpm table setup */
893 dpm_table = &dpm_context->dpm_tables.pixel_table;
894 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
895 ret = smu_v11_0_set_single_dpm_table(smu,
896 SMU_PIXCLK,
897 dpm_table);
898 if (ret)
899 return ret;
900 dpm_table->is_fine_grained =
901 !table_member[PPCLK_PIXCLK].SnapToDiscrete;
902 } else {
903 dpm_table->count = 1;
904 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
905 dpm_table->dpm_levels[0].enabled = true;
906 dpm_table->min = dpm_table->dpm_levels[0].value;
907 dpm_table->max = dpm_table->dpm_levels[0].value;
908 }
909
910 /* displayclk dpm table setup */
911 dpm_table = &dpm_context->dpm_tables.display_table;
912 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
913 ret = smu_v11_0_set_single_dpm_table(smu,
914 SMU_DISPCLK,
915 dpm_table);
916 if (ret)
917 return ret;
918 dpm_table->is_fine_grained =
919 !table_member[PPCLK_DISPCLK].SnapToDiscrete;
920 } else {
921 dpm_table->count = 1;
922 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
923 dpm_table->dpm_levels[0].enabled = true;
924 dpm_table->min = dpm_table->dpm_levels[0].value;
925 dpm_table->max = dpm_table->dpm_levels[0].value;
926 }
927
928 /* phyclk dpm table setup */
929 dpm_table = &dpm_context->dpm_tables.phy_table;
930 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
931 ret = smu_v11_0_set_single_dpm_table(smu,
932 SMU_PHYCLK,
933 dpm_table);
934 if (ret)
935 return ret;
936 dpm_table->is_fine_grained =
937 !table_member[PPCLK_PHYCLK].SnapToDiscrete;
938 } else {
939 dpm_table->count = 1;
940 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
941 dpm_table->dpm_levels[0].enabled = true;
942 dpm_table->min = dpm_table->dpm_levels[0].value;
943 dpm_table->max = dpm_table->dpm_levels[0].value;
944 }
945
946 return 0;
947 }
948
sienna_cichlid_dpm_set_vcn_enable(struct smu_context * smu,bool enable)949 static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
950 {
951 struct amdgpu_device *adev = smu->adev;
952 int ret = 0;
953
954 if (enable) {
955 /* vcn dpm on is a prerequisite for vcn power gate messages */
956 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
957 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
958 if (ret)
959 return ret;
960 if (adev->vcn.num_vcn_inst > 1) {
961 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,
962 0x10000, NULL);
963 if (ret)
964 return ret;
965 }
966 }
967 } else {
968 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
969 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
970 if (ret)
971 return ret;
972 if (adev->vcn.num_vcn_inst > 1) {
973 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,
974 0x10000, NULL);
975 if (ret)
976 return ret;
977 }
978 }
979 }
980
981 return ret;
982 }
983
sienna_cichlid_dpm_set_jpeg_enable(struct smu_context * smu,bool enable)984 static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
985 {
986 int ret = 0;
987
988 if (enable) {
989 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
990 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
991 if (ret)
992 return ret;
993 }
994 } else {
995 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
996 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
997 if (ret)
998 return ret;
999 }
1000 }
1001
1002 return ret;
1003 }
1004
sienna_cichlid_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1005 static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
1006 enum smu_clk_type clk_type,
1007 uint32_t *value)
1008 {
1009 MetricsMember_t member_type;
1010 int clk_id = 0;
1011
1012 clk_id = smu_cmn_to_asic_specific_index(smu,
1013 CMN2ASIC_MAPPING_CLK,
1014 clk_type);
1015 if (clk_id < 0)
1016 return clk_id;
1017
1018 switch (clk_id) {
1019 case PPCLK_GFXCLK:
1020 member_type = METRICS_CURR_GFXCLK;
1021 break;
1022 case PPCLK_UCLK:
1023 member_type = METRICS_CURR_UCLK;
1024 break;
1025 case PPCLK_SOCCLK:
1026 member_type = METRICS_CURR_SOCCLK;
1027 break;
1028 case PPCLK_FCLK:
1029 member_type = METRICS_CURR_FCLK;
1030 break;
1031 case PPCLK_VCLK_0:
1032 member_type = METRICS_CURR_VCLK;
1033 break;
1034 case PPCLK_VCLK_1:
1035 member_type = METRICS_CURR_VCLK1;
1036 break;
1037 case PPCLK_DCLK_0:
1038 member_type = METRICS_CURR_DCLK;
1039 break;
1040 case PPCLK_DCLK_1:
1041 member_type = METRICS_CURR_DCLK1;
1042 break;
1043 case PPCLK_DCEFCLK:
1044 member_type = METRICS_CURR_DCEFCLK;
1045 break;
1046 default:
1047 return -EINVAL;
1048 }
1049
1050 return sienna_cichlid_get_smu_metrics_data(smu,
1051 member_type,
1052 value);
1053
1054 }
1055
sienna_cichlid_is_support_fine_grained_dpm(struct smu_context * smu,enum smu_clk_type clk_type)1056 static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
1057 {
1058 DpmDescriptor_t *dpm_desc = NULL;
1059 DpmDescriptor_t *table_member;
1060 uint32_t clk_index = 0;
1061
1062 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
1063 clk_index = smu_cmn_to_asic_specific_index(smu,
1064 CMN2ASIC_MAPPING_CLK,
1065 clk_type);
1066 dpm_desc = &table_member[clk_index];
1067
1068 /* 0 - Fine grained DPM, 1 - Discrete DPM */
1069 return dpm_desc->SnapToDiscrete == 0;
1070 }
1071
sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table * od_table,enum SMU_11_0_7_ODFEATURE_CAP cap)1072 static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table,
1073 enum SMU_11_0_7_ODFEATURE_CAP cap)
1074 {
1075 return od_table->cap[cap];
1076 }
1077
sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table * od_table,enum SMU_11_0_7_ODSETTING_ID setting,uint32_t * min,uint32_t * max)1078 static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table,
1079 enum SMU_11_0_7_ODSETTING_ID setting,
1080 uint32_t *min, uint32_t *max)
1081 {
1082 if (min)
1083 *min = od_table->min[setting];
1084 if (max)
1085 *max = od_table->max[setting];
1086 }
1087
sienna_cichlid_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)1088 static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
1089 enum smu_clk_type clk_type, char *buf)
1090 {
1091 struct amdgpu_device *adev = smu->adev;
1092 struct smu_table_context *table_context = &smu->smu_table;
1093 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1094 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1095 uint16_t *table_member;
1096
1097 struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings;
1098 OverDriveTable_t *od_table =
1099 (OverDriveTable_t *)table_context->overdrive_table;
1100 int i, size = 0, ret = 0;
1101 uint32_t cur_value = 0, value = 0, count = 0;
1102 uint32_t freq_values[3] = {0};
1103 uint32_t mark_index = 0;
1104 uint32_t gen_speed, lane_width;
1105 uint32_t min_value, max_value;
1106 uint32_t smu_version;
1107
1108 smu_cmn_get_sysfs_buf(&buf, &size);
1109
1110 switch (clk_type) {
1111 case SMU_GFXCLK:
1112 case SMU_SCLK:
1113 case SMU_SOCCLK:
1114 case SMU_MCLK:
1115 case SMU_UCLK:
1116 case SMU_FCLK:
1117 case SMU_VCLK:
1118 case SMU_VCLK1:
1119 case SMU_DCLK:
1120 case SMU_DCLK1:
1121 case SMU_DCEFCLK:
1122 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
1123 if (ret)
1124 goto print_clk_out;
1125
1126 /* no need to disable gfxoff when retrieving the current gfxclk */
1127 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1128 amdgpu_gfx_off_ctrl(adev, false);
1129
1130 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
1131 if (ret)
1132 goto print_clk_out;
1133
1134 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1135 for (i = 0; i < count; i++) {
1136 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
1137 if (ret)
1138 goto print_clk_out;
1139
1140 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
1141 cur_value == value ? "*" : "");
1142 }
1143 } else {
1144 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
1145 if (ret)
1146 goto print_clk_out;
1147 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
1148 if (ret)
1149 goto print_clk_out;
1150
1151 freq_values[1] = cur_value;
1152 mark_index = cur_value == freq_values[0] ? 0 :
1153 cur_value == freq_values[2] ? 2 : 1;
1154
1155 count = 3;
1156 if (mark_index != 1) {
1157 count = 2;
1158 freq_values[1] = freq_values[2];
1159 }
1160
1161 for (i = 0; i < count; i++) {
1162 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],
1163 cur_value == freq_values[i] ? "*" : "");
1164 }
1165
1166 }
1167 break;
1168 case SMU_PCIE:
1169 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1170 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
1171 GET_PPTABLE_MEMBER(LclkFreq, &table_member);
1172 for (i = 0; i < NUM_LINK_LEVELS; i++)
1173 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1174 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1175 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1176 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1177 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1178 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1179 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1180 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1181 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1182 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1183 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
1184 table_member[i],
1185 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1186 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1187 "*" : "");
1188 break;
1189 case SMU_OD_SCLK:
1190 if (!smu->od_enabled || !od_table || !od_settings)
1191 break;
1192
1193 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS))
1194 break;
1195
1196 size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1197 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
1198 break;
1199
1200 case SMU_OD_MCLK:
1201 if (!smu->od_enabled || !od_table || !od_settings)
1202 break;
1203
1204 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS))
1205 break;
1206
1207 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1208 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax);
1209 break;
1210
1211 case SMU_OD_VDDGFX_OFFSET:
1212 if (!smu->od_enabled || !od_table || !od_settings)
1213 break;
1214
1215 /*
1216 * OD GFX Voltage Offset functionality is supported only by 58.41.0
1217 * and onwards SMU firmwares.
1218 */
1219 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1220 if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
1221 (smu_version < 0x003a2900))
1222 break;
1223
1224 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
1225 size += sysfs_emit_at(buf, size, "%dmV\n", od_table->VddGfxOffset);
1226 break;
1227
1228 case SMU_OD_RANGE:
1229 if (!smu->od_enabled || !od_table || !od_settings)
1230 break;
1231
1232 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1233
1234 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
1235 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN,
1236 &min_value, NULL);
1237 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMAX,
1238 NULL, &max_value);
1239 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
1240 min_value, max_value);
1241 }
1242
1243 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
1244 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMIN,
1245 &min_value, NULL);
1246 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMAX,
1247 NULL, &max_value);
1248 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
1249 min_value, max_value);
1250 }
1251 break;
1252
1253 default:
1254 break;
1255 }
1256
1257 print_clk_out:
1258 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1259 amdgpu_gfx_off_ctrl(adev, true);
1260
1261 return size;
1262 }
1263
sienna_cichlid_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)1264 static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
1265 enum smu_clk_type clk_type, uint32_t mask)
1266 {
1267 struct amdgpu_device *adev = smu->adev;
1268 int ret = 0, size = 0;
1269 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1270
1271 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1272 soft_max_level = mask ? (fls(mask) - 1) : 0;
1273
1274 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1275 amdgpu_gfx_off_ctrl(adev, false);
1276
1277 switch (clk_type) {
1278 case SMU_GFXCLK:
1279 case SMU_SCLK:
1280 case SMU_SOCCLK:
1281 case SMU_MCLK:
1282 case SMU_UCLK:
1283 case SMU_FCLK:
1284 /* There is only 2 levels for fine grained DPM */
1285 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1286 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1287 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1288 }
1289
1290 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1291 if (ret)
1292 goto forec_level_out;
1293
1294 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1295 if (ret)
1296 goto forec_level_out;
1297
1298 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1299 if (ret)
1300 goto forec_level_out;
1301 break;
1302 case SMU_DCEFCLK:
1303 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
1304 break;
1305 default:
1306 break;
1307 }
1308
1309 forec_level_out:
1310 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1311 amdgpu_gfx_off_ctrl(adev, true);
1312
1313 return size;
1314 }
1315
sienna_cichlid_populate_umd_state_clk(struct smu_context * smu)1316 static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1317 {
1318 struct smu_11_0_dpm_context *dpm_context =
1319 smu->smu_dpm.dpm_context;
1320 struct smu_11_0_dpm_table *gfx_table =
1321 &dpm_context->dpm_tables.gfx_table;
1322 struct smu_11_0_dpm_table *mem_table =
1323 &dpm_context->dpm_tables.uclk_table;
1324 struct smu_11_0_dpm_table *soc_table =
1325 &dpm_context->dpm_tables.soc_table;
1326 struct smu_umd_pstate_table *pstate_table =
1327 &smu->pstate_table;
1328 struct amdgpu_device *adev = smu->adev;
1329
1330 pstate_table->gfxclk_pstate.min = gfx_table->min;
1331 pstate_table->gfxclk_pstate.peak = gfx_table->max;
1332
1333 pstate_table->uclk_pstate.min = mem_table->min;
1334 pstate_table->uclk_pstate.peak = mem_table->max;
1335
1336 pstate_table->socclk_pstate.min = soc_table->min;
1337 pstate_table->socclk_pstate.peak = soc_table->max;
1338
1339 switch (adev->asic_type) {
1340 case CHIP_SIENNA_CICHLID:
1341 case CHIP_NAVY_FLOUNDER:
1342 pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
1343 pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
1344 pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;
1345 break;
1346 case CHIP_DIMGREY_CAVEFISH:
1347 pstate_table->gfxclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK;
1348 pstate_table->uclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK;
1349 pstate_table->socclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK;
1350 break;
1351 case CHIP_BEIGE_GOBY:
1352 pstate_table->gfxclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK;
1353 pstate_table->uclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK;
1354 pstate_table->socclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK;
1355 break;
1356 default:
1357 break;
1358 }
1359
1360 return 0;
1361 }
1362
sienna_cichlid_pre_display_config_changed(struct smu_context * smu)1363 static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1364 {
1365 int ret = 0;
1366 uint32_t max_freq = 0;
1367
1368 /* Sienna_Cichlid do not support to change display num currently */
1369 return 0;
1370 #if 0
1371 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1372 if (ret)
1373 return ret;
1374 #endif
1375
1376 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1377 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
1378 if (ret)
1379 return ret;
1380 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1381 if (ret)
1382 return ret;
1383 }
1384
1385 return ret;
1386 }
1387
sienna_cichlid_display_config_changed(struct smu_context * smu)1388 static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1389 {
1390 int ret = 0;
1391
1392 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1393 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1394 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1395 #if 0
1396 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1397 smu->display_config->num_display,
1398 NULL);
1399 #endif
1400 if (ret)
1401 return ret;
1402 }
1403
1404 return ret;
1405 }
1406
sienna_cichlid_is_dpm_running(struct smu_context * smu)1407 static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1408 {
1409 int ret = 0;
1410 uint32_t feature_mask[2];
1411 uint64_t feature_enabled;
1412
1413 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1414 if (ret)
1415 return false;
1416
1417 feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1418
1419 return !!(feature_enabled & SMC_DPM_FEATURE);
1420 }
1421
sienna_cichlid_get_fan_speed_rpm(struct smu_context * smu,uint32_t * speed)1422 static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
1423 uint32_t *speed)
1424 {
1425 if (!speed)
1426 return -EINVAL;
1427
1428 /*
1429 * For Sienna_Cichlid and later, the fan speed(rpm) reported
1430 * by pmfw is always trustable(even when the fan control feature
1431 * disabled or 0 RPM kicked in).
1432 */
1433 return sienna_cichlid_get_smu_metrics_data(smu,
1434 METRICS_CURR_FANSPEED,
1435 speed);
1436 }
1437
sienna_cichlid_get_fan_parameters(struct smu_context * smu)1438 static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
1439 {
1440 uint16_t *table_member;
1441
1442 GET_PPTABLE_MEMBER(FanMaximumRpm, &table_member);
1443 smu->fan_max_rpm = *table_member;
1444
1445 return 0;
1446 }
1447
sienna_cichlid_get_power_profile_mode(struct smu_context * smu,char * buf)1448 static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1449 {
1450 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1451 DpmActivityMonitorCoeffInt_t *activity_monitor =
1452 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1453 uint32_t i, size = 0;
1454 int16_t workload_type = 0;
1455 static const char *profile_name[] = {
1456 "BOOTUP_DEFAULT",
1457 "3D_FULL_SCREEN",
1458 "POWER_SAVING",
1459 "VIDEO",
1460 "VR",
1461 "COMPUTE",
1462 "CUSTOM"};
1463 static const char *title[] = {
1464 "PROFILE_INDEX(NAME)",
1465 "CLOCK_TYPE(NAME)",
1466 "FPS",
1467 "MinFreqType",
1468 "MinActiveFreqType",
1469 "MinActiveFreq",
1470 "BoosterFreqType",
1471 "BoosterFreq",
1472 "PD_Data_limit_c",
1473 "PD_Data_error_coeff",
1474 "PD_Data_error_rate_coeff"};
1475 int result = 0;
1476
1477 if (!buf)
1478 return -EINVAL;
1479
1480 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1481 title[0], title[1], title[2], title[3], title[4], title[5],
1482 title[6], title[7], title[8], title[9], title[10]);
1483
1484 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1485 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1486 workload_type = smu_cmn_to_asic_specific_index(smu,
1487 CMN2ASIC_MAPPING_WORKLOAD,
1488 i);
1489 if (workload_type < 0)
1490 return -EINVAL;
1491
1492 result = smu_cmn_update_table(smu,
1493 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1494 (void *)(&activity_monitor_external), false);
1495 if (result) {
1496 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1497 return result;
1498 }
1499
1500 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
1501 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1502
1503 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1504 " ",
1505 0,
1506 "GFXCLK",
1507 activity_monitor->Gfx_FPS,
1508 activity_monitor->Gfx_MinFreqStep,
1509 activity_monitor->Gfx_MinActiveFreqType,
1510 activity_monitor->Gfx_MinActiveFreq,
1511 activity_monitor->Gfx_BoosterFreqType,
1512 activity_monitor->Gfx_BoosterFreq,
1513 activity_monitor->Gfx_PD_Data_limit_c,
1514 activity_monitor->Gfx_PD_Data_error_coeff,
1515 activity_monitor->Gfx_PD_Data_error_rate_coeff);
1516
1517 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1518 " ",
1519 1,
1520 "SOCCLK",
1521 activity_monitor->Fclk_FPS,
1522 activity_monitor->Fclk_MinFreqStep,
1523 activity_monitor->Fclk_MinActiveFreqType,
1524 activity_monitor->Fclk_MinActiveFreq,
1525 activity_monitor->Fclk_BoosterFreqType,
1526 activity_monitor->Fclk_BoosterFreq,
1527 activity_monitor->Fclk_PD_Data_limit_c,
1528 activity_monitor->Fclk_PD_Data_error_coeff,
1529 activity_monitor->Fclk_PD_Data_error_rate_coeff);
1530
1531 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1532 " ",
1533 2,
1534 "MEMLK",
1535 activity_monitor->Mem_FPS,
1536 activity_monitor->Mem_MinFreqStep,
1537 activity_monitor->Mem_MinActiveFreqType,
1538 activity_monitor->Mem_MinActiveFreq,
1539 activity_monitor->Mem_BoosterFreqType,
1540 activity_monitor->Mem_BoosterFreq,
1541 activity_monitor->Mem_PD_Data_limit_c,
1542 activity_monitor->Mem_PD_Data_error_coeff,
1543 activity_monitor->Mem_PD_Data_error_rate_coeff);
1544 }
1545
1546 return size;
1547 }
1548
sienna_cichlid_set_power_profile_mode(struct smu_context * smu,long * input,uint32_t size)1549 static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1550 {
1551
1552 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1553 DpmActivityMonitorCoeffInt_t *activity_monitor =
1554 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1555 int workload_type, ret = 0;
1556
1557 smu->power_profile_mode = input[size];
1558
1559 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1560 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1561 return -EINVAL;
1562 }
1563
1564 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1565
1566 ret = smu_cmn_update_table(smu,
1567 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1568 (void *)(&activity_monitor_external), false);
1569 if (ret) {
1570 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1571 return ret;
1572 }
1573
1574 switch (input[0]) {
1575 case 0: /* Gfxclk */
1576 activity_monitor->Gfx_FPS = input[1];
1577 activity_monitor->Gfx_MinFreqStep = input[2];
1578 activity_monitor->Gfx_MinActiveFreqType = input[3];
1579 activity_monitor->Gfx_MinActiveFreq = input[4];
1580 activity_monitor->Gfx_BoosterFreqType = input[5];
1581 activity_monitor->Gfx_BoosterFreq = input[6];
1582 activity_monitor->Gfx_PD_Data_limit_c = input[7];
1583 activity_monitor->Gfx_PD_Data_error_coeff = input[8];
1584 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[9];
1585 break;
1586 case 1: /* Socclk */
1587 activity_monitor->Fclk_FPS = input[1];
1588 activity_monitor->Fclk_MinFreqStep = input[2];
1589 activity_monitor->Fclk_MinActiveFreqType = input[3];
1590 activity_monitor->Fclk_MinActiveFreq = input[4];
1591 activity_monitor->Fclk_BoosterFreqType = input[5];
1592 activity_monitor->Fclk_BoosterFreq = input[6];
1593 activity_monitor->Fclk_PD_Data_limit_c = input[7];
1594 activity_monitor->Fclk_PD_Data_error_coeff = input[8];
1595 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[9];
1596 break;
1597 case 2: /* Memlk */
1598 activity_monitor->Mem_FPS = input[1];
1599 activity_monitor->Mem_MinFreqStep = input[2];
1600 activity_monitor->Mem_MinActiveFreqType = input[3];
1601 activity_monitor->Mem_MinActiveFreq = input[4];
1602 activity_monitor->Mem_BoosterFreqType = input[5];
1603 activity_monitor->Mem_BoosterFreq = input[6];
1604 activity_monitor->Mem_PD_Data_limit_c = input[7];
1605 activity_monitor->Mem_PD_Data_error_coeff = input[8];
1606 activity_monitor->Mem_PD_Data_error_rate_coeff = input[9];
1607 break;
1608 }
1609
1610 ret = smu_cmn_update_table(smu,
1611 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1612 (void *)(&activity_monitor_external), true);
1613 if (ret) {
1614 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1615 return ret;
1616 }
1617 }
1618
1619 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1620 workload_type = smu_cmn_to_asic_specific_index(smu,
1621 CMN2ASIC_MAPPING_WORKLOAD,
1622 smu->power_profile_mode);
1623 if (workload_type < 0)
1624 return -EINVAL;
1625 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1626 1 << workload_type, NULL);
1627
1628 return ret;
1629 }
1630
sienna_cichlid_notify_smc_display_config(struct smu_context * smu)1631 static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1632 {
1633 struct smu_clocks min_clocks = {0};
1634 struct pp_display_clock_request clock_req;
1635 int ret = 0;
1636
1637 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1638 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1639 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1640
1641 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1642 clock_req.clock_type = amd_pp_dcef_clock;
1643 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1644
1645 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1646 if (!ret) {
1647 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1648 ret = smu_cmn_send_smc_msg_with_param(smu,
1649 SMU_MSG_SetMinDeepSleepDcefclk,
1650 min_clocks.dcef_clock_in_sr/100,
1651 NULL);
1652 if (ret) {
1653 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
1654 return ret;
1655 }
1656 }
1657 } else {
1658 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
1659 }
1660 }
1661
1662 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1663 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1664 if (ret) {
1665 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
1666 return ret;
1667 }
1668 }
1669
1670 return 0;
1671 }
1672
sienna_cichlid_set_watermarks_table(struct smu_context * smu,struct pp_smu_wm_range_sets * clock_ranges)1673 static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1674 struct pp_smu_wm_range_sets *clock_ranges)
1675 {
1676 Watermarks_t *table = smu->smu_table.watermarks_table;
1677 int ret = 0;
1678 int i;
1679
1680 if (clock_ranges) {
1681 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1682 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1683 return -EINVAL;
1684
1685 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1686 table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1687 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1688 table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1689 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1690 table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1691 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1692 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1693 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1694
1695 table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1696 clock_ranges->reader_wm_sets[i].wm_inst;
1697 }
1698
1699 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1700 table->WatermarkRow[WM_SOCCLK][i].MinClock =
1701 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1702 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1703 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1704 table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1705 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1706 table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1707 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1708
1709 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1710 clock_ranges->writer_wm_sets[i].wm_inst;
1711 }
1712
1713 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1714 }
1715
1716 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1717 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1718 ret = smu_cmn_write_watermarks_table(smu);
1719 if (ret) {
1720 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1721 return ret;
1722 }
1723 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1724 }
1725
1726 return 0;
1727 }
1728
sienna_cichlid_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)1729 static int sienna_cichlid_read_sensor(struct smu_context *smu,
1730 enum amd_pp_sensors sensor,
1731 void *data, uint32_t *size)
1732 {
1733 int ret = 0;
1734 uint16_t *temp;
1735
1736 if(!data || !size)
1737 return -EINVAL;
1738
1739 mutex_lock(&smu->sensor_lock);
1740 switch (sensor) {
1741 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1742 GET_PPTABLE_MEMBER(FanMaximumRpm, &temp);
1743 *(uint16_t *)data = *temp;
1744 *size = 4;
1745 break;
1746 case AMDGPU_PP_SENSOR_MEM_LOAD:
1747 ret = sienna_cichlid_get_smu_metrics_data(smu,
1748 METRICS_AVERAGE_MEMACTIVITY,
1749 (uint32_t *)data);
1750 *size = 4;
1751 break;
1752 case AMDGPU_PP_SENSOR_GPU_LOAD:
1753 ret = sienna_cichlid_get_smu_metrics_data(smu,
1754 METRICS_AVERAGE_GFXACTIVITY,
1755 (uint32_t *)data);
1756 *size = 4;
1757 break;
1758 case AMDGPU_PP_SENSOR_GPU_POWER:
1759 ret = sienna_cichlid_get_smu_metrics_data(smu,
1760 METRICS_AVERAGE_SOCKETPOWER,
1761 (uint32_t *)data);
1762 *size = 4;
1763 break;
1764 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1765 ret = sienna_cichlid_get_smu_metrics_data(smu,
1766 METRICS_TEMPERATURE_HOTSPOT,
1767 (uint32_t *)data);
1768 *size = 4;
1769 break;
1770 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1771 ret = sienna_cichlid_get_smu_metrics_data(smu,
1772 METRICS_TEMPERATURE_EDGE,
1773 (uint32_t *)data);
1774 *size = 4;
1775 break;
1776 case AMDGPU_PP_SENSOR_MEM_TEMP:
1777 ret = sienna_cichlid_get_smu_metrics_data(smu,
1778 METRICS_TEMPERATURE_MEM,
1779 (uint32_t *)data);
1780 *size = 4;
1781 break;
1782 case AMDGPU_PP_SENSOR_GFX_MCLK:
1783 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1784 *(uint32_t *)data *= 100;
1785 *size = 4;
1786 break;
1787 case AMDGPU_PP_SENSOR_GFX_SCLK:
1788 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1789 *(uint32_t *)data *= 100;
1790 *size = 4;
1791 break;
1792 case AMDGPU_PP_SENSOR_VDDGFX:
1793 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1794 *size = 4;
1795 break;
1796 default:
1797 ret = -EOPNOTSUPP;
1798 break;
1799 }
1800 mutex_unlock(&smu->sensor_lock);
1801
1802 return ret;
1803 }
1804
sienna_cichlid_get_uclk_dpm_states(struct smu_context * smu,uint32_t * clocks_in_khz,uint32_t * num_states)1805 static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1806 {
1807 uint32_t num_discrete_levels = 0;
1808 uint16_t *dpm_levels = NULL;
1809 uint16_t i = 0;
1810 struct smu_table_context *table_context = &smu->smu_table;
1811 DpmDescriptor_t *table_member1;
1812 uint16_t *table_member2;
1813
1814 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1815 return -EINVAL;
1816
1817 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member1);
1818 num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels;
1819 GET_PPTABLE_MEMBER(FreqTableUclk, &table_member2);
1820 dpm_levels = table_member2;
1821
1822 if (num_discrete_levels == 0 || dpm_levels == NULL)
1823 return -EINVAL;
1824
1825 *num_states = num_discrete_levels;
1826 for (i = 0; i < num_discrete_levels; i++) {
1827 /* convert to khz */
1828 *clocks_in_khz = (*dpm_levels) * 1000;
1829 clocks_in_khz++;
1830 dpm_levels++;
1831 }
1832
1833 return 0;
1834 }
1835
sienna_cichlid_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)1836 static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
1837 struct smu_temperature_range *range)
1838 {
1839 struct smu_table_context *table_context = &smu->smu_table;
1840 struct smu_11_0_7_powerplay_table *powerplay_table =
1841 table_context->power_play_table;
1842 uint16_t *table_member;
1843 uint16_t temp_edge, temp_hotspot, temp_mem;
1844
1845 if (!range)
1846 return -EINVAL;
1847
1848 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1849
1850 GET_PPTABLE_MEMBER(TemperatureLimit, &table_member);
1851 temp_edge = table_member[TEMP_EDGE];
1852 temp_hotspot = table_member[TEMP_HOTSPOT];
1853 temp_mem = table_member[TEMP_MEM];
1854
1855 range->max = temp_edge * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1856 range->edge_emergency_max = (temp_edge + CTF_OFFSET_EDGE) *
1857 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1858 range->hotspot_crit_max = temp_hotspot * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1859 range->hotspot_emergency_max = (temp_hotspot + CTF_OFFSET_HOTSPOT) *
1860 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1861 range->mem_crit_max = temp_mem * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1862 range->mem_emergency_max = (temp_mem + CTF_OFFSET_MEM)*
1863 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1864
1865 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1866
1867 return 0;
1868 }
1869
sienna_cichlid_display_disable_memory_clock_switch(struct smu_context * smu,bool disable_memory_clock_switch)1870 static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
1871 bool disable_memory_clock_switch)
1872 {
1873 int ret = 0;
1874 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1875 (struct smu_11_0_max_sustainable_clocks *)
1876 smu->smu_table.max_sustainable_clocks;
1877 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1878 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1879
1880 if(smu->disable_uclk_switch == disable_memory_clock_switch)
1881 return 0;
1882
1883 if(disable_memory_clock_switch)
1884 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
1885 else
1886 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
1887
1888 if(!ret)
1889 smu->disable_uclk_switch = disable_memory_clock_switch;
1890
1891 return ret;
1892 }
1893
sienna_cichlid_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit)1894 static int sienna_cichlid_get_power_limit(struct smu_context *smu,
1895 uint32_t *current_power_limit,
1896 uint32_t *default_power_limit,
1897 uint32_t *max_power_limit)
1898 {
1899 struct smu_11_0_7_powerplay_table *powerplay_table =
1900 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
1901 uint32_t power_limit, od_percent;
1902 uint16_t *table_member;
1903
1904 GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member);
1905
1906 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1907 power_limit =
1908 table_member[PPT_THROTTLER_PPT0];
1909 }
1910
1911 if (current_power_limit)
1912 *current_power_limit = power_limit;
1913 if (default_power_limit)
1914 *default_power_limit = power_limit;
1915
1916 if (max_power_limit) {
1917 if (smu->od_enabled) {
1918 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
1919
1920 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1921
1922 power_limit *= (100 + od_percent);
1923 power_limit /= 100;
1924 }
1925 *max_power_limit = power_limit;
1926 }
1927
1928 return 0;
1929 }
1930
sienna_cichlid_get_override_pcie_settings(struct smu_context * smu,uint32_t * gen_speed_override,uint32_t * lane_width_override)1931 static void sienna_cichlid_get_override_pcie_settings(struct smu_context *smu,
1932 uint32_t *gen_speed_override,
1933 uint32_t *lane_width_override)
1934 {
1935 struct amdgpu_device *adev = smu->adev;
1936
1937 *gen_speed_override = 0xff;
1938 *lane_width_override = 0xff;
1939
1940 switch (adev->pdev->device) {
1941 case 0x73A0:
1942 case 0x73A1:
1943 case 0x73A2:
1944 case 0x73A3:
1945 case 0x73AB:
1946 case 0x73AE:
1947 /* Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 */
1948 *lane_width_override = 6;
1949 break;
1950 case 0x73E0:
1951 case 0x73E1:
1952 case 0x73E3:
1953 *lane_width_override = 4;
1954 break;
1955 case 0x7420:
1956 case 0x7421:
1957 case 0x7422:
1958 case 0x7423:
1959 case 0x7424:
1960 *lane_width_override = 3;
1961 break;
1962 default:
1963 break;
1964 }
1965 }
1966
1967 #define MAX(a, b) ((a) > (b) ? (a) : (b))
1968
sienna_cichlid_update_pcie_parameters(struct smu_context * smu,uint32_t pcie_gen_cap,uint32_t pcie_width_cap)1969 static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
1970 uint32_t pcie_gen_cap,
1971 uint32_t pcie_width_cap)
1972 {
1973 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1974 struct smu_11_0_pcie_table *pcie_table = &dpm_context->dpm_tables.pcie_table;
1975 uint32_t gen_speed_override, lane_width_override;
1976 uint8_t *table_member1, *table_member2;
1977 uint32_t min_gen_speed, max_gen_speed;
1978 uint32_t min_lane_width, max_lane_width;
1979 uint32_t smu_pcie_arg;
1980 int ret, i;
1981
1982 GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1);
1983 GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2);
1984
1985 sienna_cichlid_get_override_pcie_settings(smu,
1986 &gen_speed_override,
1987 &lane_width_override);
1988
1989 /* PCIE gen speed override */
1990 if (gen_speed_override != 0xff) {
1991 min_gen_speed = MIN(pcie_gen_cap, gen_speed_override);
1992 max_gen_speed = MIN(pcie_gen_cap, gen_speed_override);
1993 } else {
1994 min_gen_speed = MAX(0, table_member1[0]);
1995 max_gen_speed = MIN(pcie_gen_cap, table_member1[1]);
1996 min_gen_speed = min_gen_speed > max_gen_speed ?
1997 max_gen_speed : min_gen_speed;
1998 }
1999 pcie_table->pcie_gen[0] = min_gen_speed;
2000 pcie_table->pcie_gen[1] = max_gen_speed;
2001
2002 /* PCIE lane width override */
2003 if (lane_width_override != 0xff) {
2004 min_lane_width = MIN(pcie_width_cap, lane_width_override);
2005 max_lane_width = MIN(pcie_width_cap, lane_width_override);
2006 } else {
2007 min_lane_width = MAX(1, table_member2[0]);
2008 max_lane_width = MIN(pcie_width_cap, table_member2[1]);
2009 min_lane_width = min_lane_width > max_lane_width ?
2010 max_lane_width : min_lane_width;
2011 }
2012 pcie_table->pcie_lane[0] = min_lane_width;
2013 pcie_table->pcie_lane[1] = max_lane_width;
2014
2015 for (i = 0; i < NUM_LINK_LEVELS; i++) {
2016 smu_pcie_arg = (i << 16 |
2017 pcie_table->pcie_gen[i] << 8 |
2018 pcie_table->pcie_lane[i]);
2019
2020 ret = smu_cmn_send_smc_msg_with_param(smu,
2021 SMU_MSG_OverridePcieParameters,
2022 smu_pcie_arg,
2023 NULL);
2024 if (ret)
2025 return ret;
2026 }
2027
2028 return 0;
2029 }
2030
sienna_cichlid_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)2031 static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
2032 enum smu_clk_type clk_type,
2033 uint32_t *min, uint32_t *max)
2034 {
2035 struct amdgpu_device *adev = smu->adev;
2036 int ret;
2037
2038 if (clk_type == SMU_GFXCLK)
2039 amdgpu_gfx_off_ctrl(adev, false);
2040 ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
2041 if (clk_type == SMU_GFXCLK)
2042 amdgpu_gfx_off_ctrl(adev, true);
2043
2044 return ret;
2045 }
2046
sienna_cichlid_dump_od_table(struct smu_context * smu,OverDriveTable_t * od_table)2047 static void sienna_cichlid_dump_od_table(struct smu_context *smu,
2048 OverDriveTable_t *od_table)
2049 {
2050 struct amdgpu_device *adev = smu->adev;
2051 uint32_t smu_version;
2052
2053 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin,
2054 od_table->GfxclkFmax);
2055 dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin,
2056 od_table->UclkFmax);
2057
2058 smu_cmn_get_smc_version(smu, NULL, &smu_version);
2059 if (!((adev->asic_type == CHIP_SIENNA_CICHLID) &&
2060 (smu_version < 0x003a2900)))
2061 dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset);
2062 }
2063
sienna_cichlid_set_default_od_settings(struct smu_context * smu)2064 static int sienna_cichlid_set_default_od_settings(struct smu_context *smu)
2065 {
2066 OverDriveTable_t *od_table =
2067 (OverDriveTable_t *)smu->smu_table.overdrive_table;
2068 OverDriveTable_t *boot_od_table =
2069 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
2070 OverDriveTable_t *user_od_table =
2071 (OverDriveTable_t *)smu->smu_table.user_overdrive_table;
2072 OverDriveTable_t user_od_table_bak;
2073 int ret = 0;
2074
2075 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE,
2076 0, (void *)boot_od_table, false);
2077 if (ret) {
2078 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
2079 return ret;
2080 }
2081
2082 sienna_cichlid_dump_od_table(smu, boot_od_table);
2083
2084 memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t));
2085
2086 /*
2087 * For S3/S4/Runpm resume, we need to setup those overdrive tables again,
2088 * but we have to preserve user defined values in "user_od_table".
2089 */
2090 if (!smu->adev->in_suspend) {
2091 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
2092 smu->user_dpm_profile.user_od = false;
2093 } else if (smu->user_dpm_profile.user_od) {
2094 memcpy(&user_od_table_bak, user_od_table, sizeof(OverDriveTable_t));
2095 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
2096 user_od_table->GfxclkFmin = user_od_table_bak.GfxclkFmin;
2097 user_od_table->GfxclkFmax = user_od_table_bak.GfxclkFmax;
2098 user_od_table->UclkFmin = user_od_table_bak.UclkFmin;
2099 user_od_table->UclkFmax = user_od_table_bak.UclkFmax;
2100 user_od_table->VddGfxOffset = user_od_table_bak.VddGfxOffset;
2101 }
2102
2103 return 0;
2104 }
2105
sienna_cichlid_od_setting_check_range(struct smu_context * smu,struct smu_11_0_7_overdrive_table * od_table,enum SMU_11_0_7_ODSETTING_ID setting,uint32_t value)2106 static int sienna_cichlid_od_setting_check_range(struct smu_context *smu,
2107 struct smu_11_0_7_overdrive_table *od_table,
2108 enum SMU_11_0_7_ODSETTING_ID setting,
2109 uint32_t value)
2110 {
2111 if (value < od_table->min[setting]) {
2112 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n",
2113 setting, value, od_table->min[setting]);
2114 return -EINVAL;
2115 }
2116 if (value > od_table->max[setting]) {
2117 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n",
2118 setting, value, od_table->max[setting]);
2119 return -EINVAL;
2120 }
2121
2122 return 0;
2123 }
2124
sienna_cichlid_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)2125 static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
2126 enum PP_OD_DPM_TABLE_COMMAND type,
2127 long input[], uint32_t size)
2128 {
2129 struct smu_table_context *table_context = &smu->smu_table;
2130 OverDriveTable_t *od_table =
2131 (OverDriveTable_t *)table_context->overdrive_table;
2132 struct smu_11_0_7_overdrive_table *od_settings =
2133 (struct smu_11_0_7_overdrive_table *)smu->od_settings;
2134 struct amdgpu_device *adev = smu->adev;
2135 enum SMU_11_0_7_ODSETTING_ID freq_setting;
2136 uint16_t *freq_ptr;
2137 int i, ret = 0;
2138 uint32_t smu_version;
2139
2140 if (!smu->od_enabled) {
2141 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
2142 return -EINVAL;
2143 }
2144
2145 if (!smu->od_settings) {
2146 dev_err(smu->adev->dev, "OD board limits are not set!\n");
2147 return -ENOENT;
2148 }
2149
2150 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
2151 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
2152 return -EINVAL;
2153 }
2154
2155 switch (type) {
2156 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2157 if (!sienna_cichlid_is_od_feature_supported(od_settings,
2158 SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
2159 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
2160 return -ENOTSUPP;
2161 }
2162
2163 for (i = 0; i < size; i += 2) {
2164 if (i + 2 > size) {
2165 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2166 return -EINVAL;
2167 }
2168
2169 switch (input[i]) {
2170 case 0:
2171 if (input[i + 1] > od_table->GfxclkFmax) {
2172 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2173 input[i + 1], od_table->GfxclkFmax);
2174 return -EINVAL;
2175 }
2176
2177 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMIN;
2178 freq_ptr = &od_table->GfxclkFmin;
2179 break;
2180
2181 case 1:
2182 if (input[i + 1] < od_table->GfxclkFmin) {
2183 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2184 input[i + 1], od_table->GfxclkFmin);
2185 return -EINVAL;
2186 }
2187
2188 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMAX;
2189 freq_ptr = &od_table->GfxclkFmax;
2190 break;
2191
2192 default:
2193 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2194 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2195 return -EINVAL;
2196 }
2197
2198 ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2199 freq_setting, input[i + 1]);
2200 if (ret)
2201 return ret;
2202
2203 *freq_ptr = (uint16_t)input[i + 1];
2204 }
2205 break;
2206
2207 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2208 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
2209 dev_warn(smu->adev->dev, "UCLK_LIMITS not supported!\n");
2210 return -ENOTSUPP;
2211 }
2212
2213 for (i = 0; i < size; i += 2) {
2214 if (i + 2 > size) {
2215 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2216 return -EINVAL;
2217 }
2218
2219 switch (input[i]) {
2220 case 0:
2221 if (input[i + 1] > od_table->UclkFmax) {
2222 dev_info(smu->adev->dev, "UclkFmin (%ld) must be <= UclkFmax (%u)!\n",
2223 input[i + 1], od_table->UclkFmax);
2224 return -EINVAL;
2225 }
2226
2227 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMIN;
2228 freq_ptr = &od_table->UclkFmin;
2229 break;
2230
2231 case 1:
2232 if (input[i + 1] < od_table->UclkFmin) {
2233 dev_info(smu->adev->dev, "UclkFmax (%ld) must be >= UclkFmin (%u)!\n",
2234 input[i + 1], od_table->UclkFmin);
2235 return -EINVAL;
2236 }
2237
2238 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMAX;
2239 freq_ptr = &od_table->UclkFmax;
2240 break;
2241
2242 default:
2243 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
2244 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2245 return -EINVAL;
2246 }
2247
2248 ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2249 freq_setting, input[i + 1]);
2250 if (ret)
2251 return ret;
2252
2253 *freq_ptr = (uint16_t)input[i + 1];
2254 }
2255 break;
2256
2257 case PP_OD_RESTORE_DEFAULT_TABLE:
2258 memcpy(table_context->overdrive_table,
2259 table_context->boot_overdrive_table,
2260 sizeof(OverDriveTable_t));
2261 fallthrough;
2262
2263 case PP_OD_COMMIT_DPM_TABLE:
2264 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) {
2265 sienna_cichlid_dump_od_table(smu, od_table);
2266 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2267 if (ret) {
2268 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2269 return ret;
2270 }
2271 memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t));
2272 smu->user_dpm_profile.user_od = true;
2273
2274 if (!memcmp(table_context->user_overdrive_table,
2275 table_context->boot_overdrive_table,
2276 sizeof(OverDriveTable_t)))
2277 smu->user_dpm_profile.user_od = false;
2278 }
2279 break;
2280
2281 case PP_OD_EDIT_VDDGFX_OFFSET:
2282 if (size != 1) {
2283 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2284 return -EINVAL;
2285 }
2286
2287 /*
2288 * OD GFX Voltage Offset functionality is supported only by 58.41.0
2289 * and onwards SMU firmwares.
2290 */
2291 smu_cmn_get_smc_version(smu, NULL, &smu_version);
2292 if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
2293 (smu_version < 0x003a2900)) {
2294 dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported "
2295 "only by 58.41.0 and onwards SMU firmwares!\n");
2296 return -EOPNOTSUPP;
2297 }
2298
2299 od_table->VddGfxOffset = (int16_t)input[0];
2300
2301 sienna_cichlid_dump_od_table(smu, od_table);
2302 break;
2303
2304 default:
2305 return -ENOSYS;
2306 }
2307
2308 return ret;
2309 }
2310
sienna_cichlid_restore_user_od_settings(struct smu_context * smu)2311 static int sienna_cichlid_restore_user_od_settings(struct smu_context *smu)
2312 {
2313 struct smu_table_context *table_context = &smu->smu_table;
2314 OverDriveTable_t *od_table = table_context->overdrive_table;
2315 OverDriveTable_t *user_od_table = table_context->user_overdrive_table;
2316 int res;
2317
2318 res = smu_v11_0_restore_user_od_settings(smu);
2319 if (res == 0)
2320 memcpy(od_table, user_od_table, sizeof(OverDriveTable_t));
2321
2322 return res;
2323 }
2324
sienna_cichlid_run_btc(struct smu_context * smu)2325 static int sienna_cichlid_run_btc(struct smu_context *smu)
2326 {
2327 return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2328 }
2329
sienna_cichlid_baco_enter(struct smu_context * smu)2330 static int sienna_cichlid_baco_enter(struct smu_context *smu)
2331 {
2332 struct amdgpu_device *adev = smu->adev;
2333
2334 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
2335 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
2336 else
2337 return smu_v11_0_baco_enter(smu);
2338 }
2339
sienna_cichlid_baco_exit(struct smu_context * smu)2340 static int sienna_cichlid_baco_exit(struct smu_context *smu)
2341 {
2342 struct amdgpu_device *adev = smu->adev;
2343
2344 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
2345 /* Wait for PMFW handling for the Dstate change */
2346 msleep(10);
2347 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2348 } else {
2349 return smu_v11_0_baco_exit(smu);
2350 }
2351 }
2352
sienna_cichlid_is_mode1_reset_supported(struct smu_context * smu)2353 static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
2354 {
2355 struct amdgpu_device *adev = smu->adev;
2356 uint32_t val;
2357 u32 smu_version;
2358
2359 /**
2360 * SRIOV env will not support SMU mode1 reset
2361 * PM FW support mode1 reset from 58.26
2362 */
2363 smu_cmn_get_smc_version(smu, NULL, &smu_version);
2364 if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00))
2365 return false;
2366
2367 /**
2368 * mode1 reset relies on PSP, so we should check if
2369 * PSP is alive.
2370 */
2371 val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
2372 return val != 0x0;
2373 }
2374
beige_goby_dump_pptable(struct smu_context * smu)2375 static void beige_goby_dump_pptable(struct smu_context *smu)
2376 {
2377 struct smu_table_context *table_context = &smu->smu_table;
2378 PPTable_beige_goby_t *pptable = table_context->driver_pptable;
2379 int i;
2380
2381 dev_info(smu->adev->dev, "Dumped PPTable:\n");
2382
2383 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2384 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2385 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
2386
2387 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
2388 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2389 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2390 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2391 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
2392 }
2393
2394 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
2395 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2396 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
2397 }
2398
2399 for (i = 0; i < TEMP_COUNT; i++) {
2400 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
2401 }
2402
2403 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2404 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2405 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2406 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2407 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
2408
2409 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
2410 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
2411 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2412 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
2413 }
2414 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2415
2416 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2417
2418 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2419 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2420 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2421 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2422
2423 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2424
2425 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2426
2427 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2428 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2429 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2430 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2431
2432 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2433 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2434
2435 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2436 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2437 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2438 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2439 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2440 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2441 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2442 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2443
2444 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
2445 " .VoltageMode = 0x%02x\n"
2446 " .SnapToDiscrete = 0x%02x\n"
2447 " .NumDiscreteLevels = 0x%02x\n"
2448 " .padding = 0x%02x\n"
2449 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2450 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2451 " .SsFmin = 0x%04x\n"
2452 " .Padding_16 = 0x%04x\n",
2453 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
2454 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
2455 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
2456 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
2457 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
2458 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
2459 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
2460 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
2461 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
2462 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
2463 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
2464
2465 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
2466 " .VoltageMode = 0x%02x\n"
2467 " .SnapToDiscrete = 0x%02x\n"
2468 " .NumDiscreteLevels = 0x%02x\n"
2469 " .padding = 0x%02x\n"
2470 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2471 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2472 " .SsFmin = 0x%04x\n"
2473 " .Padding_16 = 0x%04x\n",
2474 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
2475 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
2476 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
2477 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
2478 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
2479 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
2480 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
2481 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
2482 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2483 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2484 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2485
2486 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
2487 " .VoltageMode = 0x%02x\n"
2488 " .SnapToDiscrete = 0x%02x\n"
2489 " .NumDiscreteLevels = 0x%02x\n"
2490 " .padding = 0x%02x\n"
2491 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2492 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2493 " .SsFmin = 0x%04x\n"
2494 " .Padding_16 = 0x%04x\n",
2495 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2496 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2497 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
2498 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
2499 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
2500 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
2501 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
2502 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
2503 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
2504 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
2505 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
2506
2507 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
2508 " .VoltageMode = 0x%02x\n"
2509 " .SnapToDiscrete = 0x%02x\n"
2510 " .NumDiscreteLevels = 0x%02x\n"
2511 " .padding = 0x%02x\n"
2512 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2513 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2514 " .SsFmin = 0x%04x\n"
2515 " .Padding_16 = 0x%04x\n",
2516 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
2517 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
2518 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
2519 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
2520 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
2521 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
2522 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
2523 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
2524 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
2525 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
2526 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
2527
2528 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
2529 " .VoltageMode = 0x%02x\n"
2530 " .SnapToDiscrete = 0x%02x\n"
2531 " .NumDiscreteLevels = 0x%02x\n"
2532 " .padding = 0x%02x\n"
2533 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2534 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2535 " .SsFmin = 0x%04x\n"
2536 " .Padding_16 = 0x%04x\n",
2537 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
2538 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
2539 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
2540 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
2541 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
2542 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
2543 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
2544 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
2545 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
2546 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
2547 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
2548
2549 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
2550 " .VoltageMode = 0x%02x\n"
2551 " .SnapToDiscrete = 0x%02x\n"
2552 " .NumDiscreteLevels = 0x%02x\n"
2553 " .padding = 0x%02x\n"
2554 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2555 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2556 " .SsFmin = 0x%04x\n"
2557 " .Padding_16 = 0x%04x\n",
2558 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
2559 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
2560 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
2561 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
2562 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
2563 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
2564 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
2565 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
2566 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
2567 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
2568 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
2569
2570 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
2571 " .VoltageMode = 0x%02x\n"
2572 " .SnapToDiscrete = 0x%02x\n"
2573 " .NumDiscreteLevels = 0x%02x\n"
2574 " .padding = 0x%02x\n"
2575 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2576 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2577 " .SsFmin = 0x%04x\n"
2578 " .Padding_16 = 0x%04x\n",
2579 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
2580 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
2581 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
2582 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
2583 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
2584 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
2585 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
2586 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
2587 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
2588 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
2589 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
2590
2591 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
2592 " .VoltageMode = 0x%02x\n"
2593 " .SnapToDiscrete = 0x%02x\n"
2594 " .NumDiscreteLevels = 0x%02x\n"
2595 " .padding = 0x%02x\n"
2596 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2597 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2598 " .SsFmin = 0x%04x\n"
2599 " .Padding_16 = 0x%04x\n",
2600 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
2601 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
2602 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
2603 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
2604 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
2605 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
2606 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
2607 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
2608 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
2609 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
2610 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
2611
2612 dev_info(smu->adev->dev, "FreqTableGfx\n");
2613 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
2614 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
2615
2616 dev_info(smu->adev->dev, "FreqTableVclk\n");
2617 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
2618 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
2619
2620 dev_info(smu->adev->dev, "FreqTableDclk\n");
2621 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
2622 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
2623
2624 dev_info(smu->adev->dev, "FreqTableSocclk\n");
2625 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
2626 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
2627
2628 dev_info(smu->adev->dev, "FreqTableUclk\n");
2629 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2630 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
2631
2632 dev_info(smu->adev->dev, "FreqTableFclk\n");
2633 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
2634 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2635
2636 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
2637 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2638 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2639 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2640 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2641 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2642 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2643 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2644 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2645
2646 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
2647 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2648 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
2649
2650 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2651 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
2652
2653 dev_info(smu->adev->dev, "Mp0clkFreq\n");
2654 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2655 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
2656
2657 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
2658 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2659 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
2660
2661 dev_info(smu->adev->dev, "MemVddciVoltage\n");
2662 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2663 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
2664
2665 dev_info(smu->adev->dev, "MemMvddVoltage\n");
2666 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2667 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2668
2669 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2670 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2671 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2672 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2673 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2674
2675 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2676
2677 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2678 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2679 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2680 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2681 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2682 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2683 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2684 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2685 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2686 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2687 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2688
2689 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2690 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2691 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2692 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2693 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2694 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2695
2696 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2697 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2698 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2699 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2700 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2701
2702 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
2703 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
2704 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
2705
2706 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2707 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2708 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2709 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
2710
2711 dev_info(smu->adev->dev, "UclkDpmPstates\n");
2712 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2713 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
2714
2715 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2716 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2717 pptable->UclkDpmSrcFreqRange.Fmin);
2718 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2719 pptable->UclkDpmSrcFreqRange.Fmax);
2720 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2721 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2722 pptable->UclkDpmTargFreqRange.Fmin);
2723 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2724 pptable->UclkDpmTargFreqRange.Fmax);
2725 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2726 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
2727
2728 dev_info(smu->adev->dev, "PcieGenSpeed\n");
2729 for (i = 0; i < NUM_LINK_LEVELS; i++)
2730 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
2731
2732 dev_info(smu->adev->dev, "PcieLaneCount\n");
2733 for (i = 0; i < NUM_LINK_LEVELS; i++)
2734 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
2735
2736 dev_info(smu->adev->dev, "LclkFreq\n");
2737 for (i = 0; i < NUM_LINK_LEVELS; i++)
2738 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
2739
2740 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2741 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
2742
2743 dev_info(smu->adev->dev, "FanGain\n");
2744 for (i = 0; i < TEMP_COUNT; i++)
2745 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2746
2747 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2748 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2749 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2750 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2751 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2752 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2753 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2754 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2755 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2756 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2757 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2758 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2759
2760 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2761 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2762 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2763 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2764
2765 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2766 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2767 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2768 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2769
2770 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2771 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2772 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2773 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2774 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2775 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2776 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2777 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2778 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2779 pptable->dBtcGbGfxPll.a,
2780 pptable->dBtcGbGfxPll.b,
2781 pptable->dBtcGbGfxPll.c);
2782 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2783 pptable->dBtcGbGfxDfll.a,
2784 pptable->dBtcGbGfxDfll.b,
2785 pptable->dBtcGbGfxDfll.c);
2786 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2787 pptable->dBtcGbSoc.a,
2788 pptable->dBtcGbSoc.b,
2789 pptable->dBtcGbSoc.c);
2790 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2791 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2792 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2793 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2794 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2795 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2796
2797 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
2798 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
2799 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
2800 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2801 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
2802 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2803 }
2804
2805 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2806 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2807 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2808 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2809 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2810 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2811 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2812 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2813
2814 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2815 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2816
2817 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2818 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2819 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2820 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2821
2822 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2823 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2824 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2825 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2826
2827 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2828 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2829
2830 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
2831 for (i = 0; i < NUM_XGMI_LEVELS; i++)
2832 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2833 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2834 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2835
2836 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2837 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2838 pptable->ReservedEquation0.a,
2839 pptable->ReservedEquation0.b,
2840 pptable->ReservedEquation0.c);
2841 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2842 pptable->ReservedEquation1.a,
2843 pptable->ReservedEquation1.b,
2844 pptable->ReservedEquation1.c);
2845 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2846 pptable->ReservedEquation2.a,
2847 pptable->ReservedEquation2.b,
2848 pptable->ReservedEquation2.c);
2849 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2850 pptable->ReservedEquation3.a,
2851 pptable->ReservedEquation3.b,
2852 pptable->ReservedEquation3.c);
2853
2854 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2855 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2856 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2857 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2858 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2859 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2860 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2861 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2862
2863 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2864 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2865 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2866 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2867 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2868 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2869
2870 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2871 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2872 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
2873 pptable->I2cControllers[i].Enabled);
2874 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
2875 pptable->I2cControllers[i].Speed);
2876 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
2877 pptable->I2cControllers[i].SlaveAddress);
2878 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
2879 pptable->I2cControllers[i].ControllerPort);
2880 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
2881 pptable->I2cControllers[i].ControllerName);
2882 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
2883 pptable->I2cControllers[i].ThermalThrotter);
2884 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
2885 pptable->I2cControllers[i].I2cProtocol);
2886 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
2887 pptable->I2cControllers[i].PaddingConfig);
2888 }
2889
2890 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
2891 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
2892 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2893 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2894
2895 dev_info(smu->adev->dev, "Board Parameters:\n");
2896 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2897 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2898 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2899 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2900 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2901 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2902 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
2903 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
2904
2905 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
2906 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
2907 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
2908
2909 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
2910 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
2911 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
2912
2913 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2914 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2915 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2916
2917 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2918 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2919 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2920
2921 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
2922
2923 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2924 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2925 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2926 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2927 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2928 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2929 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
2930 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2931 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
2932 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
2933 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
2934 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2935 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
2936 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
2937 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2938 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2939
2940 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2941 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2942 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
2943
2944 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2945 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2946 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
2947
2948 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
2949 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
2950
2951 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
2952 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
2953 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
2954
2955 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
2956 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
2957 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
2958 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
2959 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
2960
2961 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
2962 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
2963
2964 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
2965 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2966 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
2967 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
2968 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2969 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
2970 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
2971 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2972 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
2973 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
2974 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2975 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
2976
2977 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
2978 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
2979 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
2980 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
2981
2982 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
2983 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
2984 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
2985 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
2986 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
2987 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
2988 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
2989 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
2990 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
2991 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
2992 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
2993
2994 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
2995 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
2996 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
2997 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
2998 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
2999 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3000 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3001 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
3002 }
3003
sienna_cichlid_dump_pptable(struct smu_context * smu)3004 static void sienna_cichlid_dump_pptable(struct smu_context *smu)
3005 {
3006 struct smu_table_context *table_context = &smu->smu_table;
3007 PPTable_t *pptable = table_context->driver_pptable;
3008 int i;
3009
3010 if (smu->adev->asic_type == CHIP_BEIGE_GOBY) {
3011 beige_goby_dump_pptable(smu);
3012 return;
3013 }
3014
3015 dev_info(smu->adev->dev, "Dumped PPTable:\n");
3016
3017 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
3018 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
3019 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
3020
3021 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
3022 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
3023 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
3024 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
3025 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
3026 }
3027
3028 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
3029 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
3030 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
3031 }
3032
3033 for (i = 0; i < TEMP_COUNT; i++) {
3034 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
3035 }
3036
3037 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
3038 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
3039 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
3040 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
3041 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
3042
3043 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
3044 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
3045 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
3046 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
3047 }
3048 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
3049
3050 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
3051
3052 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
3053 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
3054 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
3055 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
3056
3057 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
3058 dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
3059
3060 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
3061 dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
3062 dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
3063 dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
3064
3065 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
3066 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
3067 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
3068 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
3069
3070 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
3071 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
3072
3073 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
3074 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
3075 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
3076 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
3077 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
3078 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
3079 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
3080 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
3081
3082 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
3083 " .VoltageMode = 0x%02x\n"
3084 " .SnapToDiscrete = 0x%02x\n"
3085 " .NumDiscreteLevels = 0x%02x\n"
3086 " .padding = 0x%02x\n"
3087 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3088 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3089 " .SsFmin = 0x%04x\n"
3090 " .Padding_16 = 0x%04x\n",
3091 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
3092 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
3093 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
3094 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
3095 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
3096 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
3097 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
3098 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
3099 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
3100 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
3101 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
3102
3103 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
3104 " .VoltageMode = 0x%02x\n"
3105 " .SnapToDiscrete = 0x%02x\n"
3106 " .NumDiscreteLevels = 0x%02x\n"
3107 " .padding = 0x%02x\n"
3108 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3109 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3110 " .SsFmin = 0x%04x\n"
3111 " .Padding_16 = 0x%04x\n",
3112 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
3113 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
3114 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
3115 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
3116 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
3117 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
3118 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
3119 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
3120 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
3121 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
3122 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
3123
3124 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
3125 " .VoltageMode = 0x%02x\n"
3126 " .SnapToDiscrete = 0x%02x\n"
3127 " .NumDiscreteLevels = 0x%02x\n"
3128 " .padding = 0x%02x\n"
3129 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3130 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3131 " .SsFmin = 0x%04x\n"
3132 " .Padding_16 = 0x%04x\n",
3133 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
3134 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
3135 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
3136 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
3137 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
3138 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
3139 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
3140 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
3141 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
3142 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
3143 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
3144
3145 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
3146 " .VoltageMode = 0x%02x\n"
3147 " .SnapToDiscrete = 0x%02x\n"
3148 " .NumDiscreteLevels = 0x%02x\n"
3149 " .padding = 0x%02x\n"
3150 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3151 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3152 " .SsFmin = 0x%04x\n"
3153 " .Padding_16 = 0x%04x\n",
3154 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
3155 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
3156 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
3157 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
3158 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
3159 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
3160 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
3161 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
3162 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
3163 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
3164 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
3165
3166 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
3167 " .VoltageMode = 0x%02x\n"
3168 " .SnapToDiscrete = 0x%02x\n"
3169 " .NumDiscreteLevels = 0x%02x\n"
3170 " .padding = 0x%02x\n"
3171 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3172 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3173 " .SsFmin = 0x%04x\n"
3174 " .Padding_16 = 0x%04x\n",
3175 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
3176 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
3177 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
3178 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
3179 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
3180 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
3181 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
3182 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
3183 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
3184 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
3185 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
3186
3187 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
3188 " .VoltageMode = 0x%02x\n"
3189 " .SnapToDiscrete = 0x%02x\n"
3190 " .NumDiscreteLevels = 0x%02x\n"
3191 " .padding = 0x%02x\n"
3192 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3193 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3194 " .SsFmin = 0x%04x\n"
3195 " .Padding_16 = 0x%04x\n",
3196 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
3197 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
3198 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
3199 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
3200 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
3201 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
3202 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
3203 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
3204 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
3205 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
3206 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
3207
3208 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
3209 " .VoltageMode = 0x%02x\n"
3210 " .SnapToDiscrete = 0x%02x\n"
3211 " .NumDiscreteLevels = 0x%02x\n"
3212 " .padding = 0x%02x\n"
3213 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3214 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3215 " .SsFmin = 0x%04x\n"
3216 " .Padding_16 = 0x%04x\n",
3217 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
3218 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
3219 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
3220 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
3221 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
3222 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
3223 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
3224 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
3225 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
3226 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
3227 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
3228
3229 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
3230 " .VoltageMode = 0x%02x\n"
3231 " .SnapToDiscrete = 0x%02x\n"
3232 " .NumDiscreteLevels = 0x%02x\n"
3233 " .padding = 0x%02x\n"
3234 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3235 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3236 " .SsFmin = 0x%04x\n"
3237 " .Padding_16 = 0x%04x\n",
3238 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
3239 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
3240 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
3241 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
3242 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
3243 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
3244 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
3245 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
3246 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
3247 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
3248 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
3249
3250 dev_info(smu->adev->dev, "FreqTableGfx\n");
3251 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
3252 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
3253
3254 dev_info(smu->adev->dev, "FreqTableVclk\n");
3255 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
3256 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
3257
3258 dev_info(smu->adev->dev, "FreqTableDclk\n");
3259 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
3260 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
3261
3262 dev_info(smu->adev->dev, "FreqTableSocclk\n");
3263 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
3264 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
3265
3266 dev_info(smu->adev->dev, "FreqTableUclk\n");
3267 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3268 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
3269
3270 dev_info(smu->adev->dev, "FreqTableFclk\n");
3271 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
3272 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
3273
3274 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
3275 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
3276 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
3277 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
3278 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
3279 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
3280 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
3281 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
3282 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
3283
3284 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
3285 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3286 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
3287
3288 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
3289 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
3290
3291 dev_info(smu->adev->dev, "Mp0clkFreq\n");
3292 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
3293 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
3294
3295 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
3296 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
3297 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
3298
3299 dev_info(smu->adev->dev, "MemVddciVoltage\n");
3300 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3301 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
3302
3303 dev_info(smu->adev->dev, "MemMvddVoltage\n");
3304 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3305 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
3306
3307 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
3308 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
3309 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
3310 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
3311 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
3312
3313 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
3314
3315 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
3316 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
3317 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
3318 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
3319 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
3320 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
3321 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
3322 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
3323 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
3324 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
3325 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
3326
3327 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
3328 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
3329 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
3330 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
3331 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
3332 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
3333
3334 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
3335 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
3336 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
3337 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
3338 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
3339
3340 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
3341 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
3342 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
3343
3344 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
3345 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
3346 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
3347 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
3348
3349 dev_info(smu->adev->dev, "UclkDpmPstates\n");
3350 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3351 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
3352
3353 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
3354 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
3355 pptable->UclkDpmSrcFreqRange.Fmin);
3356 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
3357 pptable->UclkDpmSrcFreqRange.Fmax);
3358 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
3359 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
3360 pptable->UclkDpmTargFreqRange.Fmin);
3361 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
3362 pptable->UclkDpmTargFreqRange.Fmax);
3363 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
3364 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
3365
3366 dev_info(smu->adev->dev, "PcieGenSpeed\n");
3367 for (i = 0; i < NUM_LINK_LEVELS; i++)
3368 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
3369
3370 dev_info(smu->adev->dev, "PcieLaneCount\n");
3371 for (i = 0; i < NUM_LINK_LEVELS; i++)
3372 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
3373
3374 dev_info(smu->adev->dev, "LclkFreq\n");
3375 for (i = 0; i < NUM_LINK_LEVELS; i++)
3376 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
3377
3378 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
3379 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
3380
3381 dev_info(smu->adev->dev, "FanGain\n");
3382 for (i = 0; i < TEMP_COUNT; i++)
3383 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
3384
3385 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
3386 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
3387 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
3388 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
3389 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
3390 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
3391 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
3392 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
3393 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
3394 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
3395 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
3396 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
3397
3398 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
3399 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
3400 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
3401 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
3402
3403 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
3404 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
3405 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
3406 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
3407
3408 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
3409 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
3410 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
3411 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
3412 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
3413 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
3414 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
3415 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
3416 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
3417 pptable->dBtcGbGfxPll.a,
3418 pptable->dBtcGbGfxPll.b,
3419 pptable->dBtcGbGfxPll.c);
3420 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
3421 pptable->dBtcGbGfxDfll.a,
3422 pptable->dBtcGbGfxDfll.b,
3423 pptable->dBtcGbGfxDfll.c);
3424 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
3425 pptable->dBtcGbSoc.a,
3426 pptable->dBtcGbSoc.b,
3427 pptable->dBtcGbSoc.c);
3428 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
3429 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
3430 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
3431 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
3432 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
3433 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
3434
3435 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
3436 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
3437 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
3438 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
3439 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
3440 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
3441 }
3442
3443 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
3444 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
3445 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
3446 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
3447 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
3448 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
3449 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
3450 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
3451
3452 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
3453 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
3454
3455 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
3456 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
3457 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
3458 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
3459
3460 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
3461 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
3462 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
3463 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
3464
3465 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
3466 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
3467
3468 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
3469 for (i = 0; i < NUM_XGMI_LEVELS; i++)
3470 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
3471 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
3472 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
3473
3474 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
3475 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
3476 pptable->ReservedEquation0.a,
3477 pptable->ReservedEquation0.b,
3478 pptable->ReservedEquation0.c);
3479 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
3480 pptable->ReservedEquation1.a,
3481 pptable->ReservedEquation1.b,
3482 pptable->ReservedEquation1.c);
3483 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
3484 pptable->ReservedEquation2.a,
3485 pptable->ReservedEquation2.b,
3486 pptable->ReservedEquation2.c);
3487 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
3488 pptable->ReservedEquation3.a,
3489 pptable->ReservedEquation3.b,
3490 pptable->ReservedEquation3.c);
3491
3492 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
3493 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
3494 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
3495 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
3496 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
3497 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
3498 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
3499 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
3500
3501 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
3502 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
3503 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
3504 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
3505 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
3506 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
3507
3508 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
3509 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
3510 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
3511 pptable->I2cControllers[i].Enabled);
3512 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
3513 pptable->I2cControllers[i].Speed);
3514 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
3515 pptable->I2cControllers[i].SlaveAddress);
3516 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
3517 pptable->I2cControllers[i].ControllerPort);
3518 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
3519 pptable->I2cControllers[i].ControllerName);
3520 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
3521 pptable->I2cControllers[i].ThermalThrotter);
3522 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
3523 pptable->I2cControllers[i].I2cProtocol);
3524 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
3525 pptable->I2cControllers[i].PaddingConfig);
3526 }
3527
3528 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
3529 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
3530 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
3531 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
3532
3533 dev_info(smu->adev->dev, "Board Parameters:\n");
3534 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
3535 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
3536 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
3537 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
3538 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
3539 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
3540 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
3541 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
3542
3543 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
3544 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
3545 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
3546
3547 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
3548 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
3549 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
3550
3551 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
3552 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
3553 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
3554
3555 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
3556 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
3557 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
3558
3559 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3560
3561 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
3562 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
3563 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
3564 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
3565 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
3566 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
3567 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
3568 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
3569 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
3570 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
3571 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
3572 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
3573 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
3574 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
3575 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
3576 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
3577
3578 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
3579 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
3580 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
3581
3582 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
3583 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
3584 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
3585
3586 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
3587 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3588
3589 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3590 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3591 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3592
3593 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3594 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3595 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3596 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3597 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3598
3599 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3600 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3601
3602 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
3603 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3604 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3605 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
3606 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3607 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3608 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
3609 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3610 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3611 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
3612 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3613 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3614
3615 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3616 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3617 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3618 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3619
3620 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3621 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3622 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3623 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3624 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3625 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3626 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3627 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3628 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3629 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3630 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
3631
3632 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3633 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3634 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3635 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3636 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3637 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3638 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3639 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
3640 }
3641
sienna_cichlid_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msg,int num_msgs)3642 static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
3643 struct i2c_msg *msg, int num_msgs)
3644 {
3645 struct amdgpu_device *adev = to_amdgpu_device(i2c_adap);
3646 struct smu_table_context *smu_table = &adev->smu.smu_table;
3647 struct smu_table *table = &smu_table->driver_table;
3648 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
3649 int i, j, r, c;
3650 u16 dir;
3651
3652 req = kzalloc(sizeof(*req), GFP_KERNEL);
3653 if (!req)
3654 return -ENOMEM;
3655
3656 req->I2CcontrollerPort = 1;
3657 req->I2CSpeed = I2C_SPEED_FAST_400K;
3658 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
3659 dir = msg[0].flags & I2C_M_RD;
3660
3661 for (c = i = 0; i < num_msgs; i++) {
3662 for (j = 0; j < msg[i].len; j++, c++) {
3663 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
3664
3665 if (!(msg[i].flags & I2C_M_RD)) {
3666 /* write */
3667 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
3668 cmd->ReadWriteData = msg[i].buf[j];
3669 }
3670
3671 if ((dir ^ msg[i].flags) & I2C_M_RD) {
3672 /* The direction changes.
3673 */
3674 dir = msg[i].flags & I2C_M_RD;
3675 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
3676 }
3677
3678 req->NumCmds++;
3679
3680 /*
3681 * Insert STOP if we are at the last byte of either last
3682 * message for the transaction or the client explicitly
3683 * requires a STOP at this particular message.
3684 */
3685 if ((j == msg[i].len - 1) &&
3686 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
3687 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
3688 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
3689 }
3690 }
3691 }
3692 mutex_lock(&adev->smu.mutex);
3693 r = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
3694 mutex_unlock(&adev->smu.mutex);
3695 if (r)
3696 goto fail;
3697
3698 for (c = i = 0; i < num_msgs; i++) {
3699 if (!(msg[i].flags & I2C_M_RD)) {
3700 c += msg[i].len;
3701 continue;
3702 }
3703 for (j = 0; j < msg[i].len; j++, c++) {
3704 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
3705
3706 msg[i].buf[j] = cmd->ReadWriteData;
3707 }
3708 }
3709 r = num_msgs;
3710 fail:
3711 kfree(req);
3712 return r;
3713 }
3714
sienna_cichlid_i2c_func(struct i2c_adapter * adap)3715 static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
3716 {
3717 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3718 }
3719
3720
3721 static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
3722 .master_xfer = sienna_cichlid_i2c_xfer,
3723 .functionality = sienna_cichlid_i2c_func,
3724 };
3725
3726 static const struct i2c_adapter_quirks sienna_cichlid_i2c_control_quirks = {
3727 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
3728 .max_read_len = MAX_SW_I2C_COMMANDS,
3729 .max_write_len = MAX_SW_I2C_COMMANDS,
3730 .max_comb_1st_msg_len = 2,
3731 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
3732 };
3733
sienna_cichlid_i2c_control_init(struct smu_context * smu,struct i2c_adapter * control)3734 static int sienna_cichlid_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
3735 {
3736 struct amdgpu_device *adev = to_amdgpu_device(control);
3737 int res;
3738
3739 control->owner = THIS_MODULE;
3740 control->class = I2C_CLASS_HWMON;
3741 control->dev.parent = &adev->pdev->dev;
3742 control->algo = &sienna_cichlid_i2c_algo;
3743 snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
3744 control->quirks = &sienna_cichlid_i2c_control_quirks;
3745
3746 res = i2c_add_adapter(control);
3747 if (res)
3748 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
3749
3750 return res;
3751 }
3752
sienna_cichlid_i2c_control_fini(struct smu_context * smu,struct i2c_adapter * control)3753 static void sienna_cichlid_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
3754 {
3755 i2c_del_adapter(control);
3756 }
3757
sienna_cichlid_get_gpu_metrics(struct smu_context * smu,void ** table)3758 static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
3759 void **table)
3760 {
3761 struct smu_table_context *smu_table = &smu->smu_table;
3762 struct gpu_metrics_v1_3 *gpu_metrics =
3763 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
3764 SmuMetricsExternal_t metrics_external;
3765 SmuMetrics_t *metrics =
3766 &(metrics_external.SmuMetrics);
3767 SmuMetrics_V2_t *metrics_v2 =
3768 &(metrics_external.SmuMetrics_V2);
3769 struct amdgpu_device *adev = smu->adev;
3770 bool use_metrics_v2 = ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
3771 (smu->smc_fw_version >= 0x3A4300)) ? true : false;
3772 uint16_t average_gfx_activity;
3773 int ret = 0;
3774
3775 mutex_lock(&smu->metrics_lock);
3776 ret = smu_cmn_get_metrics_table_locked(smu,
3777 &metrics_external,
3778 true);
3779 if (ret) {
3780 mutex_unlock(&smu->metrics_lock);
3781 return ret;
3782 }
3783
3784 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
3785
3786 gpu_metrics->temperature_edge =
3787 use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge;
3788 gpu_metrics->temperature_hotspot =
3789 use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot;
3790 gpu_metrics->temperature_mem =
3791 use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem;
3792 gpu_metrics->temperature_vrgfx =
3793 use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx;
3794 gpu_metrics->temperature_vrsoc =
3795 use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc;
3796 gpu_metrics->temperature_vrmem =
3797 use_metrics_v2 ? metrics_v2->TemperatureVrMem0 : metrics->TemperatureVrMem0;
3798
3799 gpu_metrics->average_gfx_activity =
3800 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
3801 gpu_metrics->average_umc_activity =
3802 use_metrics_v2 ? metrics_v2->AverageUclkActivity : metrics->AverageUclkActivity;
3803 gpu_metrics->average_mm_activity =
3804 use_metrics_v2 ? metrics_v2->VcnActivityPercentage : metrics->VcnActivityPercentage;
3805
3806 gpu_metrics->average_socket_power =
3807 use_metrics_v2 ? metrics_v2->AverageSocketPower : metrics->AverageSocketPower;
3808 gpu_metrics->energy_accumulator =
3809 use_metrics_v2 ? metrics_v2->EnergyAccumulator : metrics->EnergyAccumulator;
3810
3811 average_gfx_activity = use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
3812 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
3813 gpu_metrics->average_gfxclk_frequency =
3814 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs : metrics->AverageGfxclkFrequencyPostDs;
3815 else
3816 gpu_metrics->average_gfxclk_frequency =
3817 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs : metrics->AverageGfxclkFrequencyPreDs;
3818 gpu_metrics->average_uclk_frequency =
3819 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs : metrics->AverageUclkFrequencyPostDs;
3820 gpu_metrics->average_vclk0_frequency =
3821 use_metrics_v2 ? metrics_v2->AverageVclk0Frequency : metrics->AverageVclk0Frequency;
3822 gpu_metrics->average_dclk0_frequency =
3823 use_metrics_v2 ? metrics_v2->AverageDclk0Frequency : metrics->AverageDclk0Frequency;
3824 gpu_metrics->average_vclk1_frequency =
3825 use_metrics_v2 ? metrics_v2->AverageVclk1Frequency : metrics->AverageVclk1Frequency;
3826 gpu_metrics->average_dclk1_frequency =
3827 use_metrics_v2 ? metrics_v2->AverageDclk1Frequency : metrics->AverageDclk1Frequency;
3828
3829 gpu_metrics->current_gfxclk =
3830 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : metrics->CurrClock[PPCLK_GFXCLK];
3831 gpu_metrics->current_socclk =
3832 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : metrics->CurrClock[PPCLK_SOCCLK];
3833 gpu_metrics->current_uclk =
3834 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : metrics->CurrClock[PPCLK_UCLK];
3835 gpu_metrics->current_vclk0 =
3836 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : metrics->CurrClock[PPCLK_VCLK_0];
3837 gpu_metrics->current_dclk0 =
3838 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : metrics->CurrClock[PPCLK_DCLK_0];
3839 gpu_metrics->current_vclk1 =
3840 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : metrics->CurrClock[PPCLK_VCLK_1];
3841 gpu_metrics->current_dclk1 =
3842 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : metrics->CurrClock[PPCLK_DCLK_1];
3843
3844 gpu_metrics->throttle_status = sienna_cichlid_get_throttler_status_locked(smu);
3845 gpu_metrics->indep_throttle_status =
3846 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
3847 sienna_cichlid_throttler_map);
3848
3849 gpu_metrics->current_fan_speed = use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
3850
3851 if (((adev->asic_type == CHIP_SIENNA_CICHLID) && smu->smc_fw_version > 0x003A1E00) ||
3852 ((adev->asic_type == CHIP_NAVY_FLOUNDER) && smu->smc_fw_version > 0x00410400)) {
3853 gpu_metrics->pcie_link_width = use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth;
3854 gpu_metrics->pcie_link_speed = link_speed[use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate];
3855 } else {
3856 gpu_metrics->pcie_link_width =
3857 smu_v11_0_get_current_pcie_link_width(smu);
3858 gpu_metrics->pcie_link_speed =
3859 smu_v11_0_get_current_pcie_link_speed(smu);
3860 }
3861
3862 mutex_unlock(&smu->metrics_lock);
3863
3864 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
3865
3866 *table = (void *)gpu_metrics;
3867
3868 return sizeof(struct gpu_metrics_v1_3);
3869 }
3870
sienna_cichlid_enable_mgpu_fan_boost(struct smu_context * smu)3871 static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
3872 {
3873 uint16_t *mgpu_fan_boost_limit_rpm;
3874
3875 GET_PPTABLE_MEMBER(MGpuFanBoostLimitRpm, &mgpu_fan_boost_limit_rpm);
3876 /*
3877 * Skip the MGpuFanBoost setting for those ASICs
3878 * which do not support it
3879 */
3880 if (*mgpu_fan_boost_limit_rpm == 0)
3881 return 0;
3882
3883 return smu_cmn_send_smc_msg_with_param(smu,
3884 SMU_MSG_SetMGpuFanBoostLimitRpm,
3885 0,
3886 NULL);
3887 }
3888
sienna_cichlid_gpo_control(struct smu_context * smu,bool enablement)3889 static int sienna_cichlid_gpo_control(struct smu_context *smu,
3890 bool enablement)
3891 {
3892 uint32_t smu_version;
3893 int ret = 0;
3894
3895
3896 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
3897 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
3898 if (ret)
3899 return ret;
3900
3901 if (enablement) {
3902 if (smu_version < 0x003a2500) {
3903 ret = smu_cmn_send_smc_msg_with_param(smu,
3904 SMU_MSG_SetGpoFeaturePMask,
3905 GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK,
3906 NULL);
3907 } else {
3908 ret = smu_cmn_send_smc_msg_with_param(smu,
3909 SMU_MSG_DisallowGpo,
3910 0,
3911 NULL);
3912 }
3913 } else {
3914 if (smu_version < 0x003a2500) {
3915 ret = smu_cmn_send_smc_msg_with_param(smu,
3916 SMU_MSG_SetGpoFeaturePMask,
3917 0,
3918 NULL);
3919 } else {
3920 ret = smu_cmn_send_smc_msg_with_param(smu,
3921 SMU_MSG_DisallowGpo,
3922 1,
3923 NULL);
3924 }
3925 }
3926 }
3927
3928 return ret;
3929 }
3930
sienna_cichlid_notify_2nd_usb20_port(struct smu_context * smu)3931 static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu)
3932 {
3933 uint32_t smu_version;
3934 int ret = 0;
3935
3936 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
3937 if (ret)
3938 return ret;
3939
3940 /*
3941 * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45
3942 * onwards PMFWs.
3943 */
3944 if (smu_version < 0x003A2D00)
3945 return 0;
3946
3947 return smu_cmn_send_smc_msg_with_param(smu,
3948 SMU_MSG_Enable2ndUSB20Port,
3949 smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ?
3950 1 : 0,
3951 NULL);
3952 }
3953
sienna_cichlid_system_features_control(struct smu_context * smu,bool en)3954 static int sienna_cichlid_system_features_control(struct smu_context *smu,
3955 bool en)
3956 {
3957 int ret = 0;
3958
3959 if (en) {
3960 ret = sienna_cichlid_notify_2nd_usb20_port(smu);
3961 if (ret)
3962 return ret;
3963 }
3964
3965 return smu_v11_0_system_features_control(smu, en);
3966 }
3967
sienna_cichlid_set_mp1_state(struct smu_context * smu,enum pp_mp1_state mp1_state)3968 static int sienna_cichlid_set_mp1_state(struct smu_context *smu,
3969 enum pp_mp1_state mp1_state)
3970 {
3971 int ret;
3972
3973 switch (mp1_state) {
3974 case PP_MP1_STATE_UNLOAD:
3975 ret = smu_cmn_set_mp1_state(smu, mp1_state);
3976 break;
3977 default:
3978 /* Ignore others */
3979 ret = 0;
3980 }
3981
3982 return ret;
3983 }
3984
3985 static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
3986 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
3987 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
3988 .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
3989 .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
3990 .i2c_init = sienna_cichlid_i2c_control_init,
3991 .i2c_fini = sienna_cichlid_i2c_control_fini,
3992 .print_clk_levels = sienna_cichlid_print_clk_levels,
3993 .force_clk_levels = sienna_cichlid_force_clk_levels,
3994 .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
3995 .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
3996 .display_config_changed = sienna_cichlid_display_config_changed,
3997 .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
3998 .is_dpm_running = sienna_cichlid_is_dpm_running,
3999 .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm,
4000 .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
4001 .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
4002 .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
4003 .set_watermarks_table = sienna_cichlid_set_watermarks_table,
4004 .read_sensor = sienna_cichlid_read_sensor,
4005 .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
4006 .set_performance_level = smu_v11_0_set_performance_level,
4007 .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
4008 .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
4009 .get_power_limit = sienna_cichlid_get_power_limit,
4010 .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
4011 .dump_pptable = sienna_cichlid_dump_pptable,
4012 .init_microcode = smu_v11_0_init_microcode,
4013 .load_microcode = smu_v11_0_load_microcode,
4014 .fini_microcode = smu_v11_0_fini_microcode,
4015 .init_smc_tables = sienna_cichlid_init_smc_tables,
4016 .fini_smc_tables = smu_v11_0_fini_smc_tables,
4017 .init_power = smu_v11_0_init_power,
4018 .fini_power = smu_v11_0_fini_power,
4019 .check_fw_status = smu_v11_0_check_fw_status,
4020 .setup_pptable = sienna_cichlid_setup_pptable,
4021 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
4022 .check_fw_version = smu_v11_0_check_fw_version,
4023 .write_pptable = smu_cmn_write_pptable,
4024 .set_driver_table_location = smu_v11_0_set_driver_table_location,
4025 .set_tool_table_location = smu_v11_0_set_tool_table_location,
4026 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
4027 .system_features_control = sienna_cichlid_system_features_control,
4028 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
4029 .send_smc_msg = smu_cmn_send_smc_msg,
4030 .init_display_count = NULL,
4031 .set_allowed_mask = smu_v11_0_set_allowed_mask,
4032 .get_enabled_mask = smu_cmn_get_enabled_mask,
4033 .feature_is_enabled = smu_cmn_feature_is_enabled,
4034 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
4035 .notify_display_change = NULL,
4036 .set_power_limit = smu_v11_0_set_power_limit,
4037 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
4038 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
4039 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
4040 .set_min_dcef_deep_sleep = NULL,
4041 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
4042 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
4043 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
4044 .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm,
4045 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
4046 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
4047 .gfx_off_control = smu_v11_0_gfx_off_control,
4048 .register_irq_handler = smu_v11_0_register_irq_handler,
4049 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
4050 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
4051 .baco_is_support = smu_v11_0_baco_is_support,
4052 .baco_get_state = smu_v11_0_baco_get_state,
4053 .baco_set_state = smu_v11_0_baco_set_state,
4054 .baco_enter = sienna_cichlid_baco_enter,
4055 .baco_exit = sienna_cichlid_baco_exit,
4056 .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
4057 .mode1_reset = smu_v11_0_mode1_reset,
4058 .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
4059 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
4060 .set_default_od_settings = sienna_cichlid_set_default_od_settings,
4061 .od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table,
4062 .restore_user_od_settings = sienna_cichlid_restore_user_od_settings,
4063 .run_btc = sienna_cichlid_run_btc,
4064 .set_power_source = smu_v11_0_set_power_source,
4065 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
4066 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
4067 .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
4068 .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
4069 .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
4070 .deep_sleep_control = smu_v11_0_deep_sleep_control,
4071 .get_fan_parameters = sienna_cichlid_get_fan_parameters,
4072 .interrupt_work = smu_v11_0_interrupt_work,
4073 .gpo_control = sienna_cichlid_gpo_control,
4074 .set_mp1_state = sienna_cichlid_set_mp1_state,
4075 };
4076
sienna_cichlid_set_ppt_funcs(struct smu_context * smu)4077 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
4078 {
4079 smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
4080 smu->message_map = sienna_cichlid_message_map;
4081 smu->clock_map = sienna_cichlid_clk_map;
4082 smu->feature_map = sienna_cichlid_feature_mask_map;
4083 smu->table_map = sienna_cichlid_table_map;
4084 smu->pwr_src_map = sienna_cichlid_pwr_src_map;
4085 smu->workload_map = sienna_cichlid_workload_map;
4086 }
4087