1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015 MediaTek Inc.
4 */
5
6 #include <linux/clk.h>
7 #include <linux/component.h>
8 #include <linux/module.h>
9 #include <linux/of_device.h>
10 #include <linux/of_irq.h>
11 #include <linux/platform_device.h>
12 #include <linux/soc/mediatek/mtk-cmdq.h>
13
14 #include "mtk_disp_drv.h"
15 #include "mtk_drm_crtc.h"
16 #include "mtk_drm_ddp_comp.h"
17
18 #define DISP_REG_RDMA_INT_ENABLE 0x0000
19 #define DISP_REG_RDMA_INT_STATUS 0x0004
20 #define RDMA_TARGET_LINE_INT BIT(5)
21 #define RDMA_FIFO_UNDERFLOW_INT BIT(4)
22 #define RDMA_EOF_ABNORMAL_INT BIT(3)
23 #define RDMA_FRAME_END_INT BIT(2)
24 #define RDMA_FRAME_START_INT BIT(1)
25 #define RDMA_REG_UPDATE_INT BIT(0)
26 #define DISP_REG_RDMA_GLOBAL_CON 0x0010
27 #define RDMA_ENGINE_EN BIT(0)
28 #define RDMA_MODE_MEMORY BIT(1)
29 #define DISP_REG_RDMA_SIZE_CON_0 0x0014
30 #define RDMA_MATRIX_ENABLE BIT(17)
31 #define RDMA_MATRIX_INT_MTX_SEL GENMASK(23, 20)
32 #define RDMA_MATRIX_INT_MTX_BT601_to_RGB (6 << 20)
33 #define DISP_REG_RDMA_SIZE_CON_1 0x0018
34 #define DISP_REG_RDMA_TARGET_LINE 0x001c
35 #define DISP_RDMA_MEM_CON 0x0024
36 #define MEM_MODE_INPUT_FORMAT_RGB565 (0x000 << 4)
37 #define MEM_MODE_INPUT_FORMAT_RGB888 (0x001 << 4)
38 #define MEM_MODE_INPUT_FORMAT_RGBA8888 (0x002 << 4)
39 #define MEM_MODE_INPUT_FORMAT_ARGB8888 (0x003 << 4)
40 #define MEM_MODE_INPUT_FORMAT_UYVY (0x004 << 4)
41 #define MEM_MODE_INPUT_FORMAT_YUYV (0x005 << 4)
42 #define MEM_MODE_INPUT_SWAP BIT(8)
43 #define DISP_RDMA_MEM_SRC_PITCH 0x002c
44 #define DISP_RDMA_MEM_GMC_SETTING_0 0x0030
45 #define DISP_REG_RDMA_FIFO_CON 0x0040
46 #define RDMA_FIFO_UNDERFLOW_EN BIT(31)
47 #define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16)
48 #define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16)
49 #define RDMA_FIFO_SIZE(rdma) ((rdma)->data->fifo_size)
50 #define DISP_RDMA_MEM_START_ADDR 0x0f00
51
52 #define RDMA_MEM_GMC 0x40402020
53
54 struct mtk_disp_rdma_data {
55 unsigned int fifo_size;
56 };
57
58 /*
59 * struct mtk_disp_rdma - DISP_RDMA driver structure
60 * @data: local driver data
61 */
62 struct mtk_disp_rdma {
63 struct clk *clk;
64 void __iomem *regs;
65 struct cmdq_client_reg cmdq_reg;
66 const struct mtk_disp_rdma_data *data;
67 void (*vblank_cb)(void *data);
68 void *vblank_cb_data;
69 u32 fifo_size;
70 };
71
mtk_disp_rdma_irq_handler(int irq,void * dev_id)72 static irqreturn_t mtk_disp_rdma_irq_handler(int irq, void *dev_id)
73 {
74 struct mtk_disp_rdma *priv = dev_id;
75
76 /* Clear frame completion interrupt */
77 writel(0x0, priv->regs + DISP_REG_RDMA_INT_STATUS);
78
79 if (!priv->vblank_cb)
80 return IRQ_NONE;
81
82 priv->vblank_cb(priv->vblank_cb_data);
83
84 return IRQ_HANDLED;
85 }
86
rdma_update_bits(struct device * dev,unsigned int reg,unsigned int mask,unsigned int val)87 static void rdma_update_bits(struct device *dev, unsigned int reg,
88 unsigned int mask, unsigned int val)
89 {
90 struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
91 unsigned int tmp = readl(rdma->regs + reg);
92
93 tmp = (tmp & ~mask) | (val & mask);
94 writel(tmp, rdma->regs + reg);
95 }
96
mtk_rdma_register_vblank_cb(struct device * dev,void (* vblank_cb)(void *),void * vblank_cb_data)97 void mtk_rdma_register_vblank_cb(struct device *dev,
98 void (*vblank_cb)(void *),
99 void *vblank_cb_data)
100 {
101 struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
102
103 rdma->vblank_cb = vblank_cb;
104 rdma->vblank_cb_data = vblank_cb_data;
105 }
106
mtk_rdma_unregister_vblank_cb(struct device * dev)107 void mtk_rdma_unregister_vblank_cb(struct device *dev)
108 {
109 struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
110
111 rdma->vblank_cb = NULL;
112 rdma->vblank_cb_data = NULL;
113 }
114
mtk_rdma_enable_vblank(struct device * dev)115 void mtk_rdma_enable_vblank(struct device *dev)
116 {
117 rdma_update_bits(dev, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT,
118 RDMA_FRAME_END_INT);
119 }
120
mtk_rdma_disable_vblank(struct device * dev)121 void mtk_rdma_disable_vblank(struct device *dev)
122 {
123 rdma_update_bits(dev, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT, 0);
124 }
125
mtk_rdma_clk_enable(struct device * dev)126 int mtk_rdma_clk_enable(struct device *dev)
127 {
128 struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
129
130 return clk_prepare_enable(rdma->clk);
131 }
132
mtk_rdma_clk_disable(struct device * dev)133 void mtk_rdma_clk_disable(struct device *dev)
134 {
135 struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
136
137 clk_disable_unprepare(rdma->clk);
138 }
139
mtk_rdma_start(struct device * dev)140 void mtk_rdma_start(struct device *dev)
141 {
142 rdma_update_bits(dev, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN,
143 RDMA_ENGINE_EN);
144 }
145
mtk_rdma_stop(struct device * dev)146 void mtk_rdma_stop(struct device *dev)
147 {
148 rdma_update_bits(dev, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 0);
149 }
150
mtk_rdma_config(struct device * dev,unsigned int width,unsigned int height,unsigned int vrefresh,unsigned int bpc,struct cmdq_pkt * cmdq_pkt)151 void mtk_rdma_config(struct device *dev, unsigned int width,
152 unsigned int height, unsigned int vrefresh,
153 unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
154 {
155 unsigned int threshold;
156 unsigned int reg;
157 struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
158 u32 rdma_fifo_size;
159
160 mtk_ddp_write_mask(cmdq_pkt, width, &rdma->cmdq_reg, rdma->regs,
161 DISP_REG_RDMA_SIZE_CON_0, 0xfff);
162 mtk_ddp_write_mask(cmdq_pkt, height, &rdma->cmdq_reg, rdma->regs,
163 DISP_REG_RDMA_SIZE_CON_1, 0xfffff);
164
165 if (rdma->fifo_size)
166 rdma_fifo_size = rdma->fifo_size;
167 else
168 rdma_fifo_size = RDMA_FIFO_SIZE(rdma);
169
170 /*
171 * Enable FIFO underflow since DSI and DPI can't be blocked.
172 * Keep the FIFO pseudo size reset default of 8 KiB. Set the
173 * output threshold to 70% of max fifo size to make sure the
174 * threhold will not overflow
175 */
176 threshold = rdma_fifo_size * 7 / 10;
177 reg = RDMA_FIFO_UNDERFLOW_EN |
178 RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) |
179 RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
180 mtk_ddp_write(cmdq_pkt, reg, &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_FIFO_CON);
181 }
182
rdma_fmt_convert(struct mtk_disp_rdma * rdma,unsigned int fmt)183 static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma,
184 unsigned int fmt)
185 {
186 /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX"
187 * is defined in mediatek HW data sheet.
188 * The alphabet order in XXX is no relation to data
189 * arrangement in memory.
190 */
191 switch (fmt) {
192 default:
193 case DRM_FORMAT_RGB565:
194 return MEM_MODE_INPUT_FORMAT_RGB565;
195 case DRM_FORMAT_BGR565:
196 return MEM_MODE_INPUT_FORMAT_RGB565 | MEM_MODE_INPUT_SWAP;
197 case DRM_FORMAT_RGB888:
198 return MEM_MODE_INPUT_FORMAT_RGB888;
199 case DRM_FORMAT_BGR888:
200 return MEM_MODE_INPUT_FORMAT_RGB888 | MEM_MODE_INPUT_SWAP;
201 case DRM_FORMAT_RGBX8888:
202 case DRM_FORMAT_RGBA8888:
203 return MEM_MODE_INPUT_FORMAT_ARGB8888;
204 case DRM_FORMAT_BGRX8888:
205 case DRM_FORMAT_BGRA8888:
206 return MEM_MODE_INPUT_FORMAT_ARGB8888 | MEM_MODE_INPUT_SWAP;
207 case DRM_FORMAT_XRGB8888:
208 case DRM_FORMAT_ARGB8888:
209 return MEM_MODE_INPUT_FORMAT_RGBA8888;
210 case DRM_FORMAT_XBGR8888:
211 case DRM_FORMAT_ABGR8888:
212 return MEM_MODE_INPUT_FORMAT_RGBA8888 | MEM_MODE_INPUT_SWAP;
213 case DRM_FORMAT_UYVY:
214 return MEM_MODE_INPUT_FORMAT_UYVY;
215 case DRM_FORMAT_YUYV:
216 return MEM_MODE_INPUT_FORMAT_YUYV;
217 }
218 }
219
mtk_rdma_layer_nr(struct device * dev)220 unsigned int mtk_rdma_layer_nr(struct device *dev)
221 {
222 return 1;
223 }
224
mtk_rdma_layer_config(struct device * dev,unsigned int idx,struct mtk_plane_state * state,struct cmdq_pkt * cmdq_pkt)225 void mtk_rdma_layer_config(struct device *dev, unsigned int idx,
226 struct mtk_plane_state *state,
227 struct cmdq_pkt *cmdq_pkt)
228 {
229 struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
230 struct mtk_plane_pending_state *pending = &state->pending;
231 unsigned int addr = pending->addr;
232 unsigned int pitch = pending->pitch & 0xffff;
233 unsigned int fmt = pending->format;
234 unsigned int con;
235
236 con = rdma_fmt_convert(rdma, fmt);
237 mtk_ddp_write_relaxed(cmdq_pkt, con, &rdma->cmdq_reg, rdma->regs, DISP_RDMA_MEM_CON);
238
239 if (fmt == DRM_FORMAT_UYVY || fmt == DRM_FORMAT_YUYV) {
240 mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_ENABLE, &rdma->cmdq_reg, rdma->regs,
241 DISP_REG_RDMA_SIZE_CON_0,
242 RDMA_MATRIX_ENABLE);
243 mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_INT_MTX_BT601_to_RGB,
244 &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_SIZE_CON_0,
245 RDMA_MATRIX_INT_MTX_SEL);
246 } else {
247 mtk_ddp_write_mask(cmdq_pkt, 0, &rdma->cmdq_reg, rdma->regs,
248 DISP_REG_RDMA_SIZE_CON_0,
249 RDMA_MATRIX_ENABLE);
250 }
251 mtk_ddp_write_relaxed(cmdq_pkt, addr, &rdma->cmdq_reg, rdma->regs,
252 DISP_RDMA_MEM_START_ADDR);
253 mtk_ddp_write_relaxed(cmdq_pkt, pitch, &rdma->cmdq_reg, rdma->regs,
254 DISP_RDMA_MEM_SRC_PITCH);
255 mtk_ddp_write(cmdq_pkt, RDMA_MEM_GMC, &rdma->cmdq_reg, rdma->regs,
256 DISP_RDMA_MEM_GMC_SETTING_0);
257 mtk_ddp_write_mask(cmdq_pkt, RDMA_MODE_MEMORY, &rdma->cmdq_reg, rdma->regs,
258 DISP_REG_RDMA_GLOBAL_CON, RDMA_MODE_MEMORY);
259
260 }
261
mtk_disp_rdma_bind(struct device * dev,struct device * master,void * data)262 static int mtk_disp_rdma_bind(struct device *dev, struct device *master,
263 void *data)
264 {
265 return 0;
266
267 }
268
mtk_disp_rdma_unbind(struct device * dev,struct device * master,void * data)269 static void mtk_disp_rdma_unbind(struct device *dev, struct device *master,
270 void *data)
271 {
272 }
273
274 static const struct component_ops mtk_disp_rdma_component_ops = {
275 .bind = mtk_disp_rdma_bind,
276 .unbind = mtk_disp_rdma_unbind,
277 };
278
mtk_disp_rdma_probe(struct platform_device * pdev)279 static int mtk_disp_rdma_probe(struct platform_device *pdev)
280 {
281 struct device *dev = &pdev->dev;
282 struct mtk_disp_rdma *priv;
283 struct resource *res;
284 int irq;
285 int ret;
286
287 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
288 if (!priv)
289 return -ENOMEM;
290
291 irq = platform_get_irq(pdev, 0);
292 if (irq < 0)
293 return irq;
294
295 priv->clk = devm_clk_get(dev, NULL);
296 if (IS_ERR(priv->clk)) {
297 dev_err(dev, "failed to get rdma clk\n");
298 return PTR_ERR(priv->clk);
299 }
300
301 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
302 priv->regs = devm_ioremap_resource(dev, res);
303 if (IS_ERR(priv->regs)) {
304 dev_err(dev, "failed to ioremap rdma\n");
305 return PTR_ERR(priv->regs);
306 }
307 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
308 ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
309 if (ret)
310 dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
311 #endif
312
313 if (of_find_property(dev->of_node, "mediatek,rdma-fifo-size", &ret)) {
314 ret = of_property_read_u32(dev->of_node,
315 "mediatek,rdma-fifo-size",
316 &priv->fifo_size);
317 if (ret) {
318 dev_err(dev, "Failed to get rdma fifo size\n");
319 return ret;
320 }
321 }
322
323 /* Disable and clear pending interrupts */
324 writel(0x0, priv->regs + DISP_REG_RDMA_INT_ENABLE);
325 writel(0x0, priv->regs + DISP_REG_RDMA_INT_STATUS);
326
327 ret = devm_request_irq(dev, irq, mtk_disp_rdma_irq_handler,
328 IRQF_TRIGGER_NONE, dev_name(dev), priv);
329 if (ret < 0) {
330 dev_err(dev, "Failed to request irq %d: %d\n", irq, ret);
331 return ret;
332 }
333
334 priv->data = of_device_get_match_data(dev);
335
336 platform_set_drvdata(pdev, priv);
337
338 ret = component_add(dev, &mtk_disp_rdma_component_ops);
339 if (ret)
340 dev_err(dev, "Failed to add component: %d\n", ret);
341
342 return ret;
343 }
344
mtk_disp_rdma_remove(struct platform_device * pdev)345 static int mtk_disp_rdma_remove(struct platform_device *pdev)
346 {
347 component_del(&pdev->dev, &mtk_disp_rdma_component_ops);
348
349 return 0;
350 }
351
352 static const struct mtk_disp_rdma_data mt2701_rdma_driver_data = {
353 .fifo_size = SZ_4K,
354 };
355
356 static const struct mtk_disp_rdma_data mt8173_rdma_driver_data = {
357 .fifo_size = SZ_8K,
358 };
359
360 static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
361 .fifo_size = 5 * SZ_1K,
362 };
363
364 static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
365 { .compatible = "mediatek,mt2701-disp-rdma",
366 .data = &mt2701_rdma_driver_data},
367 { .compatible = "mediatek,mt8173-disp-rdma",
368 .data = &mt8173_rdma_driver_data},
369 { .compatible = "mediatek,mt8183-disp-rdma",
370 .data = &mt8183_rdma_driver_data},
371 {},
372 };
373 MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
374
375 struct platform_driver mtk_disp_rdma_driver = {
376 .probe = mtk_disp_rdma_probe,
377 .remove = mtk_disp_rdma_remove,
378 .driver = {
379 .name = "mediatek-disp-rdma",
380 .owner = THIS_MODULE,
381 .of_match_table = mtk_disp_rdma_driver_dt_match,
382 },
383 };
384