1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
4 *
5 * Interrupt architecture for the GIC:
6 *
7 * o There is one Interrupt Distributor, which receives interrupts
8 * from system devices and sends them to the Interrupt Controllers.
9 *
10 * o There is one CPU Interface per CPU, which sends interrupts sent
11 * by the Distributor, and interrupts generated locally, to the
12 * associated CPU. The base address of the CPU interface is usually
13 * aliased so that the same address points to different chips depending
14 * on the CPU it is accessed from.
15 *
16 * Note that IRQs 0-31 are special - they are local to each CPU.
17 * As such, the enable set/clear, pending set/clear and active bit
18 * registers are banked per-cpu for these sources.
19 */
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/module.h>
24 #include <linux/list.h>
25 #include <linux/smp.h>
26 #include <linux/cpu.h>
27 #include <linux/cpu_pm.h>
28 #include <linux/cpumask.h>
29 #include <linux/io.h>
30 #include <linux/of.h>
31 #include <linux/of_address.h>
32 #include <linux/of_irq.h>
33 #include <linux/acpi.h>
34 #include <linux/irqdomain.h>
35 #include <linux/interrupt.h>
36 #include <linux/percpu.h>
37 #include <linux/slab.h>
38 #include <linux/irqchip.h>
39 #include <linux/irqchip/chained_irq.h>
40 #include <linux/irqchip/arm-gic.h>
41 #include <trace/hooks/gic.h>
42
43 #include <asm/cputype.h>
44 #include <asm/irq.h>
45 #include <asm/exception.h>
46 #include <asm/smp_plat.h>
47 #include <asm/virt.h>
48
49 #include "irq-gic-common.h"
50
51 #ifdef CONFIG_ARM64
52 #include <asm/cpufeature.h>
53
gic_check_cpu_features(void)54 static void gic_check_cpu_features(void)
55 {
56 WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_SYSREG_GIC_CPUIF),
57 TAINT_CPU_OUT_OF_SPEC,
58 "GICv3 system registers enabled, broken firmware!\n");
59 }
60 #else
61 #define gic_check_cpu_features() do { } while(0)
62 #endif
63
64 union gic_base {
65 void __iomem *common_base;
66 void __percpu * __iomem *percpu_base;
67 };
68
69 struct gic_chip_data {
70 struct irq_chip chip;
71 union gic_base dist_base;
72 union gic_base cpu_base;
73 void __iomem *raw_dist_base;
74 void __iomem *raw_cpu_base;
75 u32 percpu_offset;
76 #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
77 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
78 u32 saved_spi_active[DIV_ROUND_UP(1020, 32)];
79 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
80 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
81 u32 __percpu *saved_ppi_enable;
82 u32 __percpu *saved_ppi_active;
83 u32 __percpu *saved_ppi_conf;
84 #endif
85 struct irq_domain *domain;
86 unsigned int gic_irqs;
87 };
88
89 #ifdef CONFIG_BL_SWITCHER
90
91 static DEFINE_RAW_SPINLOCK(cpu_map_lock);
92
93 #define gic_lock_irqsave(f) \
94 raw_spin_lock_irqsave(&cpu_map_lock, (f))
95 #define gic_unlock_irqrestore(f) \
96 raw_spin_unlock_irqrestore(&cpu_map_lock, (f))
97
98 #define gic_lock() raw_spin_lock(&cpu_map_lock)
99 #define gic_unlock() raw_spin_unlock(&cpu_map_lock)
100
101 #else
102
103 #define gic_lock_irqsave(f) do { (void)(f); } while(0)
104 #define gic_unlock_irqrestore(f) do { (void)(f); } while(0)
105
106 #define gic_lock() do { } while(0)
107 #define gic_unlock() do { } while(0)
108
109 #endif
110
111 static DEFINE_STATIC_KEY_FALSE(needs_rmw_access);
112
113 /*
114 * The GIC mapping of CPU interfaces does not necessarily match
115 * the logical CPU numbering. Let's use a mapping as returned
116 * by the GIC itself.
117 */
118 #define NR_GIC_CPU_IF 8
119 static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
120
121 static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
122
123 static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly;
124
125 static struct gic_kvm_info gic_v2_kvm_info __initdata;
126
127 static DEFINE_PER_CPU(u32, sgi_intid);
128
129 #ifdef CONFIG_GIC_NON_BANKED
130 static DEFINE_STATIC_KEY_FALSE(frankengic_key);
131
enable_frankengic(void)132 static void enable_frankengic(void)
133 {
134 static_branch_enable(&frankengic_key);
135 }
136
__get_base(union gic_base * base)137 static inline void __iomem *__get_base(union gic_base *base)
138 {
139 if (static_branch_unlikely(&frankengic_key))
140 return raw_cpu_read(*base->percpu_base);
141
142 return base->common_base;
143 }
144
145 #define gic_data_dist_base(d) __get_base(&(d)->dist_base)
146 #define gic_data_cpu_base(d) __get_base(&(d)->cpu_base)
147 #else
148 #define gic_data_dist_base(d) ((d)->dist_base.common_base)
149 #define gic_data_cpu_base(d) ((d)->cpu_base.common_base)
150 #define enable_frankengic() do { } while(0)
151 #endif
152
gic_dist_base(struct irq_data * d)153 static inline void __iomem *gic_dist_base(struct irq_data *d)
154 {
155 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
156 return gic_data_dist_base(gic_data);
157 }
158
gic_cpu_base(struct irq_data * d)159 static inline void __iomem *gic_cpu_base(struct irq_data *d)
160 {
161 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
162 return gic_data_cpu_base(gic_data);
163 }
164
gic_irq(struct irq_data * d)165 static inline unsigned int gic_irq(struct irq_data *d)
166 {
167 return d->hwirq;
168 }
169
cascading_gic_irq(struct irq_data * d)170 static inline bool cascading_gic_irq(struct irq_data *d)
171 {
172 void *data = irq_data_get_irq_handler_data(d);
173
174 /*
175 * If handler_data is set, this is a cascading interrupt, and
176 * it cannot possibly be forwarded.
177 */
178 return data != NULL;
179 }
180
181 /*
182 * Routines to acknowledge, disable and enable interrupts
183 */
gic_poke_irq(struct irq_data * d,u32 offset)184 static void gic_poke_irq(struct irq_data *d, u32 offset)
185 {
186 u32 mask = 1 << (gic_irq(d) % 32);
187 writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4);
188 }
189
gic_peek_irq(struct irq_data * d,u32 offset)190 static int gic_peek_irq(struct irq_data *d, u32 offset)
191 {
192 u32 mask = 1 << (gic_irq(d) % 32);
193 return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask);
194 }
195
gic_mask_irq(struct irq_data * d)196 static void gic_mask_irq(struct irq_data *d)
197 {
198 gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR);
199 }
200
gic_eoimode1_mask_irq(struct irq_data * d)201 static void gic_eoimode1_mask_irq(struct irq_data *d)
202 {
203 gic_mask_irq(d);
204 /*
205 * When masking a forwarded interrupt, make sure it is
206 * deactivated as well.
207 *
208 * This ensures that an interrupt that is getting
209 * disabled/masked will not get "stuck", because there is
210 * noone to deactivate it (guest is being terminated).
211 */
212 if (irqd_is_forwarded_to_vcpu(d))
213 gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR);
214 }
215
gic_unmask_irq(struct irq_data * d)216 static void gic_unmask_irq(struct irq_data *d)
217 {
218 gic_poke_irq(d, GIC_DIST_ENABLE_SET);
219 }
220
gic_eoi_irq(struct irq_data * d)221 static void gic_eoi_irq(struct irq_data *d)
222 {
223 u32 hwirq = gic_irq(d);
224
225 if (hwirq < 16)
226 hwirq = this_cpu_read(sgi_intid);
227
228 writel_relaxed(hwirq, gic_cpu_base(d) + GIC_CPU_EOI);
229 }
230
gic_eoimode1_eoi_irq(struct irq_data * d)231 static void gic_eoimode1_eoi_irq(struct irq_data *d)
232 {
233 u32 hwirq = gic_irq(d);
234
235 /* Do not deactivate an IRQ forwarded to a vcpu. */
236 if (irqd_is_forwarded_to_vcpu(d))
237 return;
238
239 if (hwirq < 16)
240 hwirq = this_cpu_read(sgi_intid);
241
242 writel_relaxed(hwirq, gic_cpu_base(d) + GIC_CPU_DEACTIVATE);
243 }
244
gic_irq_set_irqchip_state(struct irq_data * d,enum irqchip_irq_state which,bool val)245 static int gic_irq_set_irqchip_state(struct irq_data *d,
246 enum irqchip_irq_state which, bool val)
247 {
248 u32 reg;
249
250 switch (which) {
251 case IRQCHIP_STATE_PENDING:
252 reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR;
253 break;
254
255 case IRQCHIP_STATE_ACTIVE:
256 reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR;
257 break;
258
259 case IRQCHIP_STATE_MASKED:
260 reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET;
261 break;
262
263 default:
264 return -EINVAL;
265 }
266
267 gic_poke_irq(d, reg);
268 return 0;
269 }
270
gic_irq_get_irqchip_state(struct irq_data * d,enum irqchip_irq_state which,bool * val)271 static int gic_irq_get_irqchip_state(struct irq_data *d,
272 enum irqchip_irq_state which, bool *val)
273 {
274 switch (which) {
275 case IRQCHIP_STATE_PENDING:
276 *val = gic_peek_irq(d, GIC_DIST_PENDING_SET);
277 break;
278
279 case IRQCHIP_STATE_ACTIVE:
280 *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET);
281 break;
282
283 case IRQCHIP_STATE_MASKED:
284 *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET);
285 break;
286
287 default:
288 return -EINVAL;
289 }
290
291 return 0;
292 }
293
gic_set_type(struct irq_data * d,unsigned int type)294 static int gic_set_type(struct irq_data *d, unsigned int type)
295 {
296 void __iomem *base = gic_dist_base(d);
297 unsigned int gicirq = gic_irq(d);
298 int ret;
299
300 /* Interrupt configuration for SGIs can't be changed */
301 if (gicirq < 16)
302 return type != IRQ_TYPE_EDGE_RISING ? -EINVAL : 0;
303
304 /* SPIs have restrictions on the supported types */
305 if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
306 type != IRQ_TYPE_EDGE_RISING)
307 return -EINVAL;
308
309 ret = gic_configure_irq(gicirq, type, base + GIC_DIST_CONFIG, NULL);
310 if (ret && gicirq < 32) {
311 /* Misconfigured PPIs are usually not fatal */
312 pr_warn("GIC: PPI%d is secure or misconfigured\n", gicirq - 16);
313 ret = 0;
314 }
315
316 return ret;
317 }
318
gic_irq_set_vcpu_affinity(struct irq_data * d,void * vcpu)319 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
320 {
321 /* Only interrupts on the primary GIC can be forwarded to a vcpu. */
322 if (cascading_gic_irq(d) || gic_irq(d) < 16)
323 return -EINVAL;
324
325 if (vcpu)
326 irqd_set_forwarded_to_vcpu(d);
327 else
328 irqd_clr_forwarded_to_vcpu(d);
329 return 0;
330 }
331
gic_retrigger(struct irq_data * data)332 static int gic_retrigger(struct irq_data *data)
333 {
334 return !gic_irq_set_irqchip_state(data, IRQCHIP_STATE_PENDING, true);
335 }
336
gic_handle_irq(struct pt_regs * regs)337 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
338 {
339 u32 irqstat, irqnr;
340 struct gic_chip_data *gic = &gic_data[0];
341 void __iomem *cpu_base = gic_data_cpu_base(gic);
342
343 do {
344 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
345 irqnr = irqstat & GICC_IAR_INT_ID_MASK;
346
347 if (unlikely(irqnr >= 1020))
348 break;
349
350 if (static_branch_likely(&supports_deactivate_key))
351 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
352 isb();
353
354 /*
355 * Ensure any shared data written by the CPU sending the IPI
356 * is read after we've read the ACK register on the GIC.
357 *
358 * Pairs with the write barrier in gic_ipi_send_mask
359 */
360 if (irqnr <= 15) {
361 smp_rmb();
362
363 /*
364 * The GIC encodes the source CPU in GICC_IAR,
365 * leading to the deactivation to fail if not
366 * written back as is to GICC_EOI. Stash the INTID
367 * away for gic_eoi_irq() to write back. This only
368 * works because we don't nest SGIs...
369 */
370 this_cpu_write(sgi_intid, irqstat);
371 }
372
373 handle_domain_irq(gic->domain, irqnr, regs);
374 } while (1);
375 }
376
gic_handle_cascade_irq(struct irq_desc * desc)377 static void gic_handle_cascade_irq(struct irq_desc *desc)
378 {
379 struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc);
380 struct irq_chip *chip = irq_desc_get_chip(desc);
381 unsigned int gic_irq;
382 unsigned long status;
383 int ret;
384
385 chained_irq_enter(chip, desc);
386
387 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
388
389 gic_irq = (status & GICC_IAR_INT_ID_MASK);
390 if (gic_irq == GICC_INT_SPURIOUS)
391 goto out;
392
393 isb();
394 ret = generic_handle_domain_irq(chip_data->domain, gic_irq);
395 if (unlikely(ret))
396 handle_bad_irq(desc);
397 out:
398 chained_irq_exit(chip, desc);
399 }
400
401 static const struct irq_chip gic_chip = {
402 .irq_mask = gic_mask_irq,
403 .irq_unmask = gic_unmask_irq,
404 .irq_eoi = gic_eoi_irq,
405 .irq_set_type = gic_set_type,
406 .irq_retrigger = gic_retrigger,
407 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
408 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
409 .flags = IRQCHIP_SET_TYPE_MASKED |
410 IRQCHIP_SKIP_SET_WAKE |
411 IRQCHIP_MASK_ON_SUSPEND,
412 };
413
gic_cascade_irq(unsigned int gic_nr,unsigned int irq)414 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
415 {
416 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
417 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq,
418 &gic_data[gic_nr]);
419 }
420
gic_get_cpumask(struct gic_chip_data * gic)421 static u8 gic_get_cpumask(struct gic_chip_data *gic)
422 {
423 void __iomem *base = gic_data_dist_base(gic);
424 u32 mask, i;
425
426 for (i = mask = 0; i < 32; i += 4) {
427 mask = readl_relaxed(base + GIC_DIST_TARGET + i);
428 mask |= mask >> 16;
429 mask |= mask >> 8;
430 if (mask)
431 break;
432 }
433
434 if (!mask && num_possible_cpus() > 1)
435 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
436
437 return mask;
438 }
439
gic_check_gicv2(void __iomem * base)440 static bool gic_check_gicv2(void __iomem *base)
441 {
442 u32 val = readl_relaxed(base + GIC_CPU_IDENT);
443 return (val & 0xff0fff) == 0x02043B;
444 }
445
gic_cpu_if_up(struct gic_chip_data * gic)446 static void gic_cpu_if_up(struct gic_chip_data *gic)
447 {
448 void __iomem *cpu_base = gic_data_cpu_base(gic);
449 u32 bypass = 0;
450 u32 mode = 0;
451 int i;
452
453 if (gic == &gic_data[0] && static_branch_likely(&supports_deactivate_key))
454 mode = GIC_CPU_CTRL_EOImodeNS;
455
456 if (gic_check_gicv2(cpu_base))
457 for (i = 0; i < 4; i++)
458 writel_relaxed(0, cpu_base + GIC_CPU_ACTIVEPRIO + i * 4);
459
460 /*
461 * Preserve bypass disable bits to be written back later
462 */
463 bypass = readl(cpu_base + GIC_CPU_CTRL);
464 bypass &= GICC_DIS_BYPASS_MASK;
465
466 writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
467 }
468
469
gic_dist_init(struct gic_chip_data * gic)470 static void gic_dist_init(struct gic_chip_data *gic)
471 {
472 unsigned int i;
473 u32 cpumask;
474 unsigned int gic_irqs = gic->gic_irqs;
475 void __iomem *base = gic_data_dist_base(gic);
476
477 writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL);
478
479 /*
480 * Set all global interrupts to this CPU only.
481 */
482 cpumask = gic_get_cpumask(gic);
483 cpumask |= cpumask << 8;
484 cpumask |= cpumask << 16;
485 for (i = 32; i < gic_irqs; i += 4)
486 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
487
488 gic_dist_config(base, gic_irqs, NULL);
489
490 writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL);
491 }
492
gic_cpu_init(struct gic_chip_data * gic)493 static int gic_cpu_init(struct gic_chip_data *gic)
494 {
495 void __iomem *dist_base = gic_data_dist_base(gic);
496 void __iomem *base = gic_data_cpu_base(gic);
497 unsigned int cpu_mask, cpu = smp_processor_id();
498 int i;
499
500 /*
501 * Setting up the CPU map is only relevant for the primary GIC
502 * because any nested/secondary GICs do not directly interface
503 * with the CPU(s).
504 */
505 if (gic == &gic_data[0]) {
506 /*
507 * Get what the GIC says our CPU mask is.
508 */
509 if (WARN_ON(cpu >= NR_GIC_CPU_IF))
510 return -EINVAL;
511
512 gic_check_cpu_features();
513 cpu_mask = gic_get_cpumask(gic);
514 gic_cpu_map[cpu] = cpu_mask;
515
516 /*
517 * Clear our mask from the other map entries in case they're
518 * still undefined.
519 */
520 for (i = 0; i < NR_GIC_CPU_IF; i++)
521 if (i != cpu)
522 gic_cpu_map[i] &= ~cpu_mask;
523 }
524
525 gic_cpu_config(dist_base, 32, NULL);
526
527 writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK);
528 gic_cpu_if_up(gic);
529
530 return 0;
531 }
532
gic_cpu_if_down(unsigned int gic_nr)533 int gic_cpu_if_down(unsigned int gic_nr)
534 {
535 void __iomem *cpu_base;
536 u32 val = 0;
537
538 if (gic_nr >= CONFIG_ARM_GIC_MAX_NR)
539 return -EINVAL;
540
541 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
542 val = readl(cpu_base + GIC_CPU_CTRL);
543 val &= ~GICC_ENABLE;
544 writel_relaxed(val, cpu_base + GIC_CPU_CTRL);
545
546 return 0;
547 }
548
549 #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
550 /*
551 * Saves the GIC distributor registers during suspend or idle. Must be called
552 * with interrupts disabled but before powering down the GIC. After calling
553 * this function, no interrupts will be delivered by the GIC, and another
554 * platform-specific wakeup source must be enabled.
555 */
gic_dist_save(struct gic_chip_data * gic)556 void gic_dist_save(struct gic_chip_data *gic)
557 {
558 unsigned int gic_irqs;
559 void __iomem *dist_base;
560 int i;
561
562 if (WARN_ON(!gic))
563 return;
564
565 gic_irqs = gic->gic_irqs;
566 dist_base = gic_data_dist_base(gic);
567
568 if (!dist_base)
569 return;
570
571 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
572 gic->saved_spi_conf[i] =
573 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
574
575 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
576 gic->saved_spi_target[i] =
577 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
578
579 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
580 gic->saved_spi_enable[i] =
581 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
582
583 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
584 gic->saved_spi_active[i] =
585 readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
586 }
587
588 /*
589 * Restores the GIC distributor registers during resume or when coming out of
590 * idle. Must be called before enabling interrupts. If a level interrupt
591 * that occurred while the GIC was suspended is still present, it will be
592 * handled normally, but any edge interrupts that occurred will not be seen by
593 * the GIC and need to be handled by the platform-specific wakeup source.
594 */
gic_dist_restore(struct gic_chip_data * gic)595 void gic_dist_restore(struct gic_chip_data *gic)
596 {
597 unsigned int gic_irqs;
598 unsigned int i;
599 void __iomem *dist_base;
600
601 if (WARN_ON(!gic))
602 return;
603
604 gic_irqs = gic->gic_irqs;
605 dist_base = gic_data_dist_base(gic);
606
607 if (!dist_base)
608 return;
609
610 writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL);
611
612 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
613 writel_relaxed(gic->saved_spi_conf[i],
614 dist_base + GIC_DIST_CONFIG + i * 4);
615
616 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
617 writel_relaxed(GICD_INT_DEF_PRI_X4,
618 dist_base + GIC_DIST_PRI + i * 4);
619
620 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
621 writel_relaxed(gic->saved_spi_target[i],
622 dist_base + GIC_DIST_TARGET + i * 4);
623
624 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
625 writel_relaxed(GICD_INT_EN_CLR_X32,
626 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
627 writel_relaxed(gic->saved_spi_enable[i],
628 dist_base + GIC_DIST_ENABLE_SET + i * 4);
629 }
630
631 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
632 writel_relaxed(GICD_INT_EN_CLR_X32,
633 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
634 writel_relaxed(gic->saved_spi_active[i],
635 dist_base + GIC_DIST_ACTIVE_SET + i * 4);
636 }
637
638 writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL);
639 }
640
gic_cpu_save(struct gic_chip_data * gic)641 void gic_cpu_save(struct gic_chip_data *gic)
642 {
643 int i;
644 u32 *ptr;
645 void __iomem *dist_base;
646 void __iomem *cpu_base;
647
648 if (WARN_ON(!gic))
649 return;
650
651 dist_base = gic_data_dist_base(gic);
652 cpu_base = gic_data_cpu_base(gic);
653
654 if (!dist_base || !cpu_base)
655 return;
656
657 ptr = raw_cpu_ptr(gic->saved_ppi_enable);
658 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
659 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
660
661 ptr = raw_cpu_ptr(gic->saved_ppi_active);
662 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
663 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
664
665 ptr = raw_cpu_ptr(gic->saved_ppi_conf);
666 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
667 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
668
669 }
670
gic_cpu_restore(struct gic_chip_data * gic)671 void gic_cpu_restore(struct gic_chip_data *gic)
672 {
673 int i;
674 u32 *ptr;
675 void __iomem *dist_base;
676 void __iomem *cpu_base;
677
678 if (WARN_ON(!gic))
679 return;
680
681 dist_base = gic_data_dist_base(gic);
682 cpu_base = gic_data_cpu_base(gic);
683
684 if (!dist_base || !cpu_base)
685 return;
686
687 ptr = raw_cpu_ptr(gic->saved_ppi_enable);
688 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
689 writel_relaxed(GICD_INT_EN_CLR_X32,
690 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
691 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
692 }
693
694 ptr = raw_cpu_ptr(gic->saved_ppi_active);
695 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
696 writel_relaxed(GICD_INT_EN_CLR_X32,
697 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
698 writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4);
699 }
700
701 ptr = raw_cpu_ptr(gic->saved_ppi_conf);
702 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
703 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
704
705 for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
706 writel_relaxed(GICD_INT_DEF_PRI_X4,
707 dist_base + GIC_DIST_PRI + i * 4);
708
709 writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);
710 gic_cpu_if_up(gic);
711 }
712
gic_notifier(struct notifier_block * self,unsigned long cmd,void * v)713 static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
714 {
715 int i;
716
717 for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) {
718 switch (cmd) {
719 case CPU_PM_ENTER:
720 gic_cpu_save(&gic_data[i]);
721 break;
722 case CPU_PM_ENTER_FAILED:
723 case CPU_PM_EXIT:
724 gic_cpu_restore(&gic_data[i]);
725 break;
726 case CPU_CLUSTER_PM_ENTER:
727 gic_dist_save(&gic_data[i]);
728 break;
729 case CPU_CLUSTER_PM_ENTER_FAILED:
730 case CPU_CLUSTER_PM_EXIT:
731 gic_dist_restore(&gic_data[i]);
732 break;
733 }
734 }
735
736 return NOTIFY_OK;
737 }
738
739 static struct notifier_block gic_notifier_block = {
740 .notifier_call = gic_notifier,
741 };
742
gic_pm_init(struct gic_chip_data * gic)743 static int gic_pm_init(struct gic_chip_data *gic)
744 {
745 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
746 sizeof(u32));
747 if (WARN_ON(!gic->saved_ppi_enable))
748 return -ENOMEM;
749
750 gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
751 sizeof(u32));
752 if (WARN_ON(!gic->saved_ppi_active))
753 goto free_ppi_enable;
754
755 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
756 sizeof(u32));
757 if (WARN_ON(!gic->saved_ppi_conf))
758 goto free_ppi_active;
759
760 if (gic == &gic_data[0])
761 cpu_pm_register_notifier(&gic_notifier_block);
762
763 return 0;
764
765 free_ppi_active:
766 free_percpu(gic->saved_ppi_active);
767 free_ppi_enable:
768 free_percpu(gic->saved_ppi_enable);
769
770 return -ENOMEM;
771 }
772 #else
gic_pm_init(struct gic_chip_data * gic)773 static int gic_pm_init(struct gic_chip_data *gic)
774 {
775 return 0;
776 }
777 #endif
778
779 #ifdef CONFIG_SMP
rmw_writeb(u8 bval,void __iomem * addr)780 static void rmw_writeb(u8 bval, void __iomem *addr)
781 {
782 static DEFINE_RAW_SPINLOCK(rmw_lock);
783 unsigned long offset = (unsigned long)addr & 3UL;
784 unsigned long shift = offset * 8;
785 unsigned long flags;
786 u32 val;
787
788 raw_spin_lock_irqsave(&rmw_lock, flags);
789
790 addr -= offset;
791 val = readl_relaxed(addr);
792 val &= ~GENMASK(shift + 7, shift);
793 val |= bval << shift;
794 writel_relaxed(val, addr);
795
796 raw_spin_unlock_irqrestore(&rmw_lock, flags);
797 }
798
gic_set_affinity(struct irq_data * d,const struct cpumask * mask_val,bool force)799 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
800 bool force)
801 {
802 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + gic_irq(d);
803 unsigned int cpu;
804
805 if (!force)
806 cpu = cpumask_any_and(mask_val, cpu_online_mask);
807 else
808 cpu = cpumask_first(mask_val);
809
810 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
811 return -EINVAL;
812
813 if (static_branch_unlikely(&needs_rmw_access))
814 rmw_writeb(gic_cpu_map[cpu], reg);
815 else
816 writeb_relaxed(gic_cpu_map[cpu], reg);
817 irq_data_update_effective_affinity(d, cpumask_of(cpu));
818
819 trace_android_vh_gic_set_affinity(d, mask_val, force, gic_cpu_map, reg);
820
821 return IRQ_SET_MASK_OK_DONE;
822 }
823
gic_ipi_send_mask(struct irq_data * d,const struct cpumask * mask)824 static void gic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask)
825 {
826 int cpu;
827 unsigned long flags, map = 0;
828
829 if (unlikely(nr_cpu_ids == 1)) {
830 /* Only one CPU? let's do a self-IPI... */
831 writel_relaxed(2 << 24 | d->hwirq,
832 gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
833 return;
834 }
835
836 gic_lock_irqsave(flags);
837
838 /* Convert our logical CPU mask into a physical one. */
839 for_each_cpu(cpu, mask)
840 map |= gic_cpu_map[cpu];
841
842 /*
843 * Ensure that stores to Normal memory are visible to the
844 * other CPUs before they observe us issuing the IPI.
845 */
846 dmb(ishst);
847
848 /* this always happens on GIC0 */
849 writel_relaxed(map << 16 | d->hwirq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
850
851 gic_unlock_irqrestore(flags);
852 }
853
gic_starting_cpu(unsigned int cpu)854 static int gic_starting_cpu(unsigned int cpu)
855 {
856 gic_cpu_init(&gic_data[0]);
857 return 0;
858 }
859
gic_smp_init(void)860 static __init void gic_smp_init(void)
861 {
862 struct irq_fwspec sgi_fwspec = {
863 .fwnode = gic_data[0].domain->fwnode,
864 .param_count = 1,
865 };
866 int base_sgi;
867
868 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
869 "irqchip/arm/gic:starting",
870 gic_starting_cpu, NULL);
871
872 base_sgi = __irq_domain_alloc_irqs(gic_data[0].domain, -1, 8,
873 NUMA_NO_NODE, &sgi_fwspec,
874 false, NULL);
875 if (WARN_ON(base_sgi <= 0))
876 return;
877
878 set_smp_ipi_range(base_sgi, 8);
879 }
880 #else
881 #define gic_smp_init() do { } while(0)
882 #define gic_set_affinity NULL
883 #define gic_ipi_send_mask NULL
884 #endif
885
886 #ifdef CONFIG_BL_SWITCHER
887 /*
888 * gic_send_sgi - send a SGI directly to given CPU interface number
889 *
890 * cpu_id: the ID for the destination CPU interface
891 * irq: the IPI number to send a SGI for
892 */
gic_send_sgi(unsigned int cpu_id,unsigned int irq)893 void gic_send_sgi(unsigned int cpu_id, unsigned int irq)
894 {
895 BUG_ON(cpu_id >= NR_GIC_CPU_IF);
896 cpu_id = 1 << cpu_id;
897 /* this always happens on GIC0 */
898 writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
899 }
900
901 /*
902 * gic_get_cpu_id - get the CPU interface ID for the specified CPU
903 *
904 * @cpu: the logical CPU number to get the GIC ID for.
905 *
906 * Return the CPU interface ID for the given logical CPU number,
907 * or -1 if the CPU number is too large or the interface ID is
908 * unknown (more than one bit set).
909 */
gic_get_cpu_id(unsigned int cpu)910 int gic_get_cpu_id(unsigned int cpu)
911 {
912 unsigned int cpu_bit;
913
914 if (cpu >= NR_GIC_CPU_IF)
915 return -1;
916 cpu_bit = gic_cpu_map[cpu];
917 if (cpu_bit & (cpu_bit - 1))
918 return -1;
919 return __ffs(cpu_bit);
920 }
921
922 /*
923 * gic_migrate_target - migrate IRQs to another CPU interface
924 *
925 * @new_cpu_id: the CPU target ID to migrate IRQs to
926 *
927 * Migrate all peripheral interrupts with a target matching the current CPU
928 * to the interface corresponding to @new_cpu_id. The CPU interface mapping
929 * is also updated. Targets to other CPU interfaces are unchanged.
930 * This must be called with IRQs locally disabled.
931 */
gic_migrate_target(unsigned int new_cpu_id)932 void gic_migrate_target(unsigned int new_cpu_id)
933 {
934 unsigned int cur_cpu_id, gic_irqs, gic_nr = 0;
935 void __iomem *dist_base;
936 int i, ror_val, cpu = smp_processor_id();
937 u32 val, cur_target_mask, active_mask;
938
939 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
940
941 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
942 if (!dist_base)
943 return;
944 gic_irqs = gic_data[gic_nr].gic_irqs;
945
946 cur_cpu_id = __ffs(gic_cpu_map[cpu]);
947 cur_target_mask = 0x01010101 << cur_cpu_id;
948 ror_val = (cur_cpu_id - new_cpu_id) & 31;
949
950 gic_lock();
951
952 /* Update the target interface for this logical CPU */
953 gic_cpu_map[cpu] = 1 << new_cpu_id;
954
955 /*
956 * Find all the peripheral interrupts targeting the current
957 * CPU interface and migrate them to the new CPU interface.
958 * We skip DIST_TARGET 0 to 7 as they are read-only.
959 */
960 for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) {
961 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
962 active_mask = val & cur_target_mask;
963 if (active_mask) {
964 val &= ~active_mask;
965 val |= ror32(active_mask, ror_val);
966 writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4);
967 }
968 }
969
970 gic_unlock();
971
972 /*
973 * Now let's migrate and clear any potential SGIs that might be
974 * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET
975 * is a banked register, we can only forward the SGI using
976 * GIC_DIST_SOFTINT. The original SGI source is lost but Linux
977 * doesn't use that information anyway.
978 *
979 * For the same reason we do not adjust SGI source information
980 * for previously sent SGIs by us to other CPUs either.
981 */
982 for (i = 0; i < 16; i += 4) {
983 int j;
984 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i);
985 if (!val)
986 continue;
987 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i);
988 for (j = i; j < i + 4; j++) {
989 if (val & 0xff)
990 writel_relaxed((1 << (new_cpu_id + 16)) | j,
991 dist_base + GIC_DIST_SOFTINT);
992 val >>= 8;
993 }
994 }
995 }
996
997 /*
998 * gic_get_sgir_physaddr - get the physical address for the SGI register
999 *
1000 * Return the physical address of the SGI register to be used
1001 * by some early assembly code when the kernel is not yet available.
1002 */
1003 static unsigned long gic_dist_physaddr;
1004
gic_get_sgir_physaddr(void)1005 unsigned long gic_get_sgir_physaddr(void)
1006 {
1007 if (!gic_dist_physaddr)
1008 return 0;
1009 return gic_dist_physaddr + GIC_DIST_SOFTINT;
1010 }
1011
gic_init_physaddr(struct device_node * node)1012 static void __init gic_init_physaddr(struct device_node *node)
1013 {
1014 struct resource res;
1015 if (of_address_to_resource(node, 0, &res) == 0) {
1016 gic_dist_physaddr = res.start;
1017 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr);
1018 }
1019 }
1020
1021 #else
1022 #define gic_init_physaddr(node) do { } while (0)
1023 #endif
1024
gic_irq_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hw)1025 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
1026 irq_hw_number_t hw)
1027 {
1028 struct gic_chip_data *gic = d->host_data;
1029 struct irq_data *irqd = irq_desc_get_irq_data(irq_to_desc(irq));
1030
1031 switch (hw) {
1032 case 0 ... 31:
1033 irq_set_percpu_devid(irq);
1034 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
1035 handle_percpu_devid_irq, NULL, NULL);
1036 break;
1037 default:
1038 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
1039 handle_fasteoi_irq, NULL, NULL);
1040 irq_set_probe(irq);
1041 irqd_set_single_target(irqd);
1042 break;
1043 }
1044
1045 /* Prevents SW retriggers which mess up the ACK/EOI ordering */
1046 irqd_set_handle_enforce_irqctx(irqd);
1047 return 0;
1048 }
1049
gic_irq_domain_unmap(struct irq_domain * d,unsigned int irq)1050 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
1051 {
1052 }
1053
gic_irq_domain_translate(struct irq_domain * d,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)1054 static int gic_irq_domain_translate(struct irq_domain *d,
1055 struct irq_fwspec *fwspec,
1056 unsigned long *hwirq,
1057 unsigned int *type)
1058 {
1059 if (fwspec->param_count == 1 && fwspec->param[0] < 16) {
1060 *hwirq = fwspec->param[0];
1061 *type = IRQ_TYPE_EDGE_RISING;
1062 return 0;
1063 }
1064
1065 if (is_of_node(fwspec->fwnode)) {
1066 if (fwspec->param_count < 3)
1067 return -EINVAL;
1068
1069 switch (fwspec->param[0]) {
1070 case 0: /* SPI */
1071 *hwirq = fwspec->param[1] + 32;
1072 break;
1073 case 1: /* PPI */
1074 *hwirq = fwspec->param[1] + 16;
1075 break;
1076 default:
1077 return -EINVAL;
1078 }
1079
1080 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
1081
1082 /* Make it clear that broken DTs are... broken */
1083 WARN_ON(*type == IRQ_TYPE_NONE);
1084 return 0;
1085 }
1086
1087 if (is_fwnode_irqchip(fwspec->fwnode)) {
1088 if(fwspec->param_count != 2)
1089 return -EINVAL;
1090
1091 if (fwspec->param[0] < 16) {
1092 pr_err(FW_BUG "Illegal GSI%d translation request\n",
1093 fwspec->param[0]);
1094 return -EINVAL;
1095 }
1096
1097 *hwirq = fwspec->param[0];
1098 *type = fwspec->param[1];
1099
1100 WARN_ON(*type == IRQ_TYPE_NONE);
1101 return 0;
1102 }
1103
1104 return -EINVAL;
1105 }
1106
gic_irq_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * arg)1107 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1108 unsigned int nr_irqs, void *arg)
1109 {
1110 int i, ret;
1111 irq_hw_number_t hwirq;
1112 unsigned int type = IRQ_TYPE_NONE;
1113 struct irq_fwspec *fwspec = arg;
1114
1115 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
1116 if (ret)
1117 return ret;
1118
1119 for (i = 0; i < nr_irqs; i++) {
1120 ret = gic_irq_domain_map(domain, virq + i, hwirq + i);
1121 if (ret)
1122 return ret;
1123 }
1124
1125 return 0;
1126 }
1127
1128 static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = {
1129 .translate = gic_irq_domain_translate,
1130 .alloc = gic_irq_domain_alloc,
1131 .free = irq_domain_free_irqs_top,
1132 };
1133
1134 static const struct irq_domain_ops gic_irq_domain_ops = {
1135 .map = gic_irq_domain_map,
1136 .unmap = gic_irq_domain_unmap,
1137 };
1138
gic_init_chip(struct gic_chip_data * gic,struct device * dev,const char * name,bool use_eoimode1)1139 static void gic_init_chip(struct gic_chip_data *gic, struct device *dev,
1140 const char *name, bool use_eoimode1)
1141 {
1142 /* Initialize irq_chip */
1143 gic->chip = gic_chip;
1144 gic->chip.name = name;
1145 gic->chip.parent_device = dev;
1146
1147 if (use_eoimode1) {
1148 gic->chip.irq_mask = gic_eoimode1_mask_irq;
1149 gic->chip.irq_eoi = gic_eoimode1_eoi_irq;
1150 gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity;
1151 }
1152
1153 if (gic == &gic_data[0]) {
1154 gic->chip.irq_set_affinity = gic_set_affinity;
1155 gic->chip.ipi_send_mask = gic_ipi_send_mask;
1156 }
1157 }
1158
gic_init_bases(struct gic_chip_data * gic,struct fwnode_handle * handle)1159 static int gic_init_bases(struct gic_chip_data *gic,
1160 struct fwnode_handle *handle)
1161 {
1162 int gic_irqs, ret;
1163
1164 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
1165 /* Frankein-GIC without banked registers... */
1166 unsigned int cpu;
1167
1168 gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
1169 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
1170 if (WARN_ON(!gic->dist_base.percpu_base ||
1171 !gic->cpu_base.percpu_base)) {
1172 ret = -ENOMEM;
1173 goto error;
1174 }
1175
1176 for_each_possible_cpu(cpu) {
1177 u32 mpidr = cpu_logical_map(cpu);
1178 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
1179 unsigned long offset = gic->percpu_offset * core_id;
1180 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) =
1181 gic->raw_dist_base + offset;
1182 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) =
1183 gic->raw_cpu_base + offset;
1184 }
1185
1186 enable_frankengic();
1187 } else {
1188 /* Normal, sane GIC... */
1189 WARN(gic->percpu_offset,
1190 "GIC_NON_BANKED not enabled, ignoring %08x offset!",
1191 gic->percpu_offset);
1192 gic->dist_base.common_base = gic->raw_dist_base;
1193 gic->cpu_base.common_base = gic->raw_cpu_base;
1194 }
1195
1196 /*
1197 * Find out how many interrupts are supported.
1198 * The GIC only supports up to 1020 interrupt sources.
1199 */
1200 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
1201 gic_irqs = (gic_irqs + 1) * 32;
1202 if (gic_irqs > 1020)
1203 gic_irqs = 1020;
1204 gic->gic_irqs = gic_irqs;
1205
1206 if (handle) { /* DT/ACPI */
1207 gic->domain = irq_domain_create_linear(handle, gic_irqs,
1208 &gic_irq_domain_hierarchy_ops,
1209 gic);
1210 } else { /* Legacy support */
1211 /*
1212 * For primary GICs, skip over SGIs.
1213 * No secondary GIC support whatsoever.
1214 */
1215 int irq_base;
1216
1217 gic_irqs -= 16; /* calculate # of irqs to allocate */
1218
1219 irq_base = irq_alloc_descs(16, 16, gic_irqs,
1220 numa_node_id());
1221 if (irq_base < 0) {
1222 WARN(1, "Cannot allocate irq_descs @ IRQ16, assuming pre-allocated\n");
1223 irq_base = 16;
1224 }
1225
1226 gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base,
1227 16, &gic_irq_domain_ops, gic);
1228 }
1229
1230 if (WARN_ON(!gic->domain)) {
1231 ret = -ENODEV;
1232 goto error;
1233 }
1234
1235 gic_dist_init(gic);
1236 ret = gic_cpu_init(gic);
1237 if (ret)
1238 goto error;
1239
1240 ret = gic_pm_init(gic);
1241 if (ret)
1242 goto error;
1243
1244 return 0;
1245
1246 error:
1247 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
1248 free_percpu(gic->dist_base.percpu_base);
1249 free_percpu(gic->cpu_base.percpu_base);
1250 }
1251
1252 return ret;
1253 }
1254
__gic_init_bases(struct gic_chip_data * gic,struct fwnode_handle * handle)1255 static int __init __gic_init_bases(struct gic_chip_data *gic,
1256 struct fwnode_handle *handle)
1257 {
1258 char *name;
1259 int i, ret;
1260
1261 if (WARN_ON(!gic || gic->domain))
1262 return -EINVAL;
1263
1264 if (gic == &gic_data[0]) {
1265 /*
1266 * Initialize the CPU interface map to all CPUs.
1267 * It will be refined as each CPU probes its ID.
1268 * This is only necessary for the primary GIC.
1269 */
1270 for (i = 0; i < NR_GIC_CPU_IF; i++)
1271 gic_cpu_map[i] = 0xff;
1272
1273 set_handle_irq(gic_handle_irq);
1274 if (static_branch_likely(&supports_deactivate_key))
1275 pr_info("GIC: Using split EOI/Deactivate mode\n");
1276 }
1277
1278 if (static_branch_likely(&supports_deactivate_key) && gic == &gic_data[0]) {
1279 name = kasprintf(GFP_KERNEL, "GICv2");
1280 gic_init_chip(gic, NULL, name, true);
1281 } else {
1282 name = kasprintf(GFP_KERNEL, "GIC-%d", (int)(gic-&gic_data[0]));
1283 gic_init_chip(gic, NULL, name, false);
1284 }
1285
1286 ret = gic_init_bases(gic, handle);
1287 if (ret)
1288 kfree(name);
1289 else if (gic == &gic_data[0])
1290 gic_smp_init();
1291
1292 return ret;
1293 }
1294
gic_init(void __iomem * dist_base,void __iomem * cpu_base)1295 void __init gic_init(void __iomem *dist_base, void __iomem *cpu_base)
1296 {
1297 struct gic_chip_data *gic;
1298
1299 /*
1300 * Non-DT/ACPI systems won't run a hypervisor, so let's not
1301 * bother with these...
1302 */
1303 static_branch_disable(&supports_deactivate_key);
1304
1305 gic = &gic_data[0];
1306 gic->raw_dist_base = dist_base;
1307 gic->raw_cpu_base = cpu_base;
1308
1309 __gic_init_bases(gic, NULL);
1310 }
1311
gic_teardown(struct gic_chip_data * gic)1312 static void gic_teardown(struct gic_chip_data *gic)
1313 {
1314 if (WARN_ON(!gic))
1315 return;
1316
1317 if (gic->raw_dist_base)
1318 iounmap(gic->raw_dist_base);
1319 if (gic->raw_cpu_base)
1320 iounmap(gic->raw_cpu_base);
1321 }
1322
1323 #ifdef CONFIG_OF
1324 static int gic_cnt __initdata;
1325 static bool gicv2_force_probe;
1326
gicv2_force_probe_cfg(char * buf)1327 static int __init gicv2_force_probe_cfg(char *buf)
1328 {
1329 return strtobool(buf, &gicv2_force_probe);
1330 }
1331 early_param("irqchip.gicv2_force_probe", gicv2_force_probe_cfg);
1332
gic_check_eoimode(struct device_node * node,void __iomem ** base)1333 static bool gic_check_eoimode(struct device_node *node, void __iomem **base)
1334 {
1335 struct resource cpuif_res;
1336
1337 of_address_to_resource(node, 1, &cpuif_res);
1338
1339 if (!is_hyp_mode_available())
1340 return false;
1341 if (resource_size(&cpuif_res) < SZ_8K) {
1342 void __iomem *alt;
1343 /*
1344 * Check for a stupid firmware that only exposes the
1345 * first page of a GICv2.
1346 */
1347 if (!gic_check_gicv2(*base))
1348 return false;
1349
1350 if (!gicv2_force_probe) {
1351 pr_warn("GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set\n");
1352 return false;
1353 }
1354
1355 alt = ioremap(cpuif_res.start, SZ_8K);
1356 if (!alt)
1357 return false;
1358 if (!gic_check_gicv2(alt + SZ_4K)) {
1359 /*
1360 * The first page was that of a GICv2, and
1361 * the second was *something*. Let's trust it
1362 * to be a GICv2, and update the mapping.
1363 */
1364 pr_warn("GIC: GICv2 at %pa, but range is too small (broken DT?), assuming 8kB\n",
1365 &cpuif_res.start);
1366 iounmap(*base);
1367 *base = alt;
1368 return true;
1369 }
1370
1371 /*
1372 * We detected *two* initial GICv2 pages in a
1373 * row. Could be a GICv2 aliased over two 64kB
1374 * pages. Update the resource, map the iospace, and
1375 * pray.
1376 */
1377 iounmap(alt);
1378 alt = ioremap(cpuif_res.start, SZ_128K);
1379 if (!alt)
1380 return false;
1381 pr_warn("GIC: Aliased GICv2 at %pa, trying to find the canonical range over 128kB\n",
1382 &cpuif_res.start);
1383 cpuif_res.end = cpuif_res.start + SZ_128K -1;
1384 iounmap(*base);
1385 *base = alt;
1386 }
1387 if (resource_size(&cpuif_res) == SZ_128K) {
1388 /*
1389 * Verify that we have the first 4kB of a GICv2
1390 * aliased over the first 64kB by checking the
1391 * GICC_IIDR register on both ends.
1392 */
1393 if (!gic_check_gicv2(*base) ||
1394 !gic_check_gicv2(*base + 0xf000))
1395 return false;
1396
1397 /*
1398 * Move the base up by 60kB, so that we have a 8kB
1399 * contiguous region, which allows us to use GICC_DIR
1400 * at its normal offset. Please pass me that bucket.
1401 */
1402 *base += 0xf000;
1403 cpuif_res.start += 0xf000;
1404 pr_warn("GIC: Adjusting CPU interface base to %pa\n",
1405 &cpuif_res.start);
1406 }
1407
1408 return true;
1409 }
1410
gic_enable_rmw_access(void * data)1411 static bool gic_enable_rmw_access(void *data)
1412 {
1413 /*
1414 * The EMEV2 class of machines has a broken interconnect, and
1415 * locks up on accesses that are less than 32bit. So far, only
1416 * the affinity setting requires it.
1417 */
1418 if (of_machine_is_compatible("renesas,emev2")) {
1419 static_branch_enable(&needs_rmw_access);
1420 return true;
1421 }
1422
1423 return false;
1424 }
1425
1426 static const struct gic_quirk gic_quirks[] = {
1427 {
1428 .desc = "broken byte access",
1429 .compatible = "arm,pl390",
1430 .init = gic_enable_rmw_access,
1431 },
1432 { },
1433 };
1434
gic_of_setup(struct gic_chip_data * gic,struct device_node * node)1435 static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node)
1436 {
1437 if (!gic || !node)
1438 return -EINVAL;
1439
1440 gic->raw_dist_base = of_iomap(node, 0);
1441 if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n"))
1442 goto error;
1443
1444 gic->raw_cpu_base = of_iomap(node, 1);
1445 if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n"))
1446 goto error;
1447
1448 if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset))
1449 gic->percpu_offset = 0;
1450
1451 gic_enable_of_quirks(node, gic_quirks, gic);
1452
1453 return 0;
1454
1455 error:
1456 gic_teardown(gic);
1457
1458 return -ENOMEM;
1459 }
1460
gic_of_init_child(struct device * dev,struct gic_chip_data ** gic,int irq)1461 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
1462 {
1463 int ret;
1464
1465 if (!dev || !dev->of_node || !gic || !irq)
1466 return -EINVAL;
1467
1468 *gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL);
1469 if (!*gic)
1470 return -ENOMEM;
1471
1472 gic_init_chip(*gic, dev, dev->of_node->name, false);
1473
1474 ret = gic_of_setup(*gic, dev->of_node);
1475 if (ret)
1476 return ret;
1477
1478 ret = gic_init_bases(*gic, &dev->of_node->fwnode);
1479 if (ret) {
1480 gic_teardown(*gic);
1481 return ret;
1482 }
1483
1484 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, *gic);
1485
1486 return 0;
1487 }
1488
gic_of_setup_kvm_info(struct device_node * node)1489 static void __init gic_of_setup_kvm_info(struct device_node *node)
1490 {
1491 int ret;
1492 struct resource *vctrl_res = &gic_v2_kvm_info.vctrl;
1493 struct resource *vcpu_res = &gic_v2_kvm_info.vcpu;
1494
1495 gic_v2_kvm_info.type = GIC_V2;
1496
1497 gic_v2_kvm_info.maint_irq = irq_of_parse_and_map(node, 0);
1498 if (!gic_v2_kvm_info.maint_irq)
1499 return;
1500
1501 ret = of_address_to_resource(node, 2, vctrl_res);
1502 if (ret)
1503 return;
1504
1505 ret = of_address_to_resource(node, 3, vcpu_res);
1506 if (ret)
1507 return;
1508
1509 if (static_branch_likely(&supports_deactivate_key))
1510 vgic_set_kvm_info(&gic_v2_kvm_info);
1511 }
1512
1513 int __init
gic_of_init(struct device_node * node,struct device_node * parent)1514 gic_of_init(struct device_node *node, struct device_node *parent)
1515 {
1516 struct gic_chip_data *gic;
1517 int irq, ret;
1518
1519 if (WARN_ON(!node))
1520 return -ENODEV;
1521
1522 if (WARN_ON(gic_cnt >= CONFIG_ARM_GIC_MAX_NR))
1523 return -EINVAL;
1524
1525 gic = &gic_data[gic_cnt];
1526
1527 ret = gic_of_setup(gic, node);
1528 if (ret)
1529 return ret;
1530
1531 /*
1532 * Disable split EOI/Deactivate if either HYP is not available
1533 * or the CPU interface is too small.
1534 */
1535 if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base))
1536 static_branch_disable(&supports_deactivate_key);
1537
1538 ret = __gic_init_bases(gic, &node->fwnode);
1539 if (ret) {
1540 gic_teardown(gic);
1541 return ret;
1542 }
1543
1544 if (!gic_cnt) {
1545 gic_init_physaddr(node);
1546 gic_of_setup_kvm_info(node);
1547 }
1548
1549 if (parent) {
1550 irq = irq_of_parse_and_map(node, 0);
1551 gic_cascade_irq(gic_cnt, irq);
1552 }
1553
1554 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1555 gicv2m_init(&node->fwnode, gic_data[gic_cnt].domain);
1556
1557 gic_cnt++;
1558 return 0;
1559 }
1560 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
1561 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
1562 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
1563 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1564 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
1565 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
1566 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
1567 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
1568 IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init);
1569 #else
gic_of_init_child(struct device * dev,struct gic_chip_data ** gic,int irq)1570 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
1571 {
1572 return -ENOTSUPP;
1573 }
1574 #endif
1575
1576 #ifdef CONFIG_ACPI
1577 static struct
1578 {
1579 phys_addr_t cpu_phys_base;
1580 u32 maint_irq;
1581 int maint_irq_mode;
1582 phys_addr_t vctrl_base;
1583 phys_addr_t vcpu_base;
1584 } acpi_data __initdata;
1585
1586 static int __init
gic_acpi_parse_madt_cpu(union acpi_subtable_headers * header,const unsigned long end)1587 gic_acpi_parse_madt_cpu(union acpi_subtable_headers *header,
1588 const unsigned long end)
1589 {
1590 struct acpi_madt_generic_interrupt *processor;
1591 phys_addr_t gic_cpu_base;
1592 static int cpu_base_assigned;
1593
1594 processor = (struct acpi_madt_generic_interrupt *)header;
1595
1596 if (BAD_MADT_GICC_ENTRY(processor, end))
1597 return -EINVAL;
1598
1599 /*
1600 * There is no support for non-banked GICv1/2 register in ACPI spec.
1601 * All CPU interface addresses have to be the same.
1602 */
1603 gic_cpu_base = processor->base_address;
1604 if (cpu_base_assigned && gic_cpu_base != acpi_data.cpu_phys_base)
1605 return -EINVAL;
1606
1607 acpi_data.cpu_phys_base = gic_cpu_base;
1608 acpi_data.maint_irq = processor->vgic_interrupt;
1609 acpi_data.maint_irq_mode = (processor->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
1610 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE;
1611 acpi_data.vctrl_base = processor->gich_base_address;
1612 acpi_data.vcpu_base = processor->gicv_base_address;
1613
1614 cpu_base_assigned = 1;
1615 return 0;
1616 }
1617
1618 /* The things you have to do to just *count* something... */
acpi_dummy_func(union acpi_subtable_headers * header,const unsigned long end)1619 static int __init acpi_dummy_func(union acpi_subtable_headers *header,
1620 const unsigned long end)
1621 {
1622 return 0;
1623 }
1624
acpi_gic_redist_is_present(void)1625 static bool __init acpi_gic_redist_is_present(void)
1626 {
1627 return acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
1628 acpi_dummy_func, 0) > 0;
1629 }
1630
gic_validate_dist(struct acpi_subtable_header * header,struct acpi_probe_entry * ape)1631 static bool __init gic_validate_dist(struct acpi_subtable_header *header,
1632 struct acpi_probe_entry *ape)
1633 {
1634 struct acpi_madt_generic_distributor *dist;
1635 dist = (struct acpi_madt_generic_distributor *)header;
1636
1637 return (dist->version == ape->driver_data &&
1638 (dist->version != ACPI_MADT_GIC_VERSION_NONE ||
1639 !acpi_gic_redist_is_present()));
1640 }
1641
1642 #define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K)
1643 #define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K)
1644 #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K)
1645 #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K)
1646
gic_acpi_setup_kvm_info(void)1647 static void __init gic_acpi_setup_kvm_info(void)
1648 {
1649 int irq;
1650 struct resource *vctrl_res = &gic_v2_kvm_info.vctrl;
1651 struct resource *vcpu_res = &gic_v2_kvm_info.vcpu;
1652
1653 gic_v2_kvm_info.type = GIC_V2;
1654
1655 if (!acpi_data.vctrl_base)
1656 return;
1657
1658 vctrl_res->flags = IORESOURCE_MEM;
1659 vctrl_res->start = acpi_data.vctrl_base;
1660 vctrl_res->end = vctrl_res->start + ACPI_GICV2_VCTRL_MEM_SIZE - 1;
1661
1662 if (!acpi_data.vcpu_base)
1663 return;
1664
1665 vcpu_res->flags = IORESOURCE_MEM;
1666 vcpu_res->start = acpi_data.vcpu_base;
1667 vcpu_res->end = vcpu_res->start + ACPI_GICV2_VCPU_MEM_SIZE - 1;
1668
1669 irq = acpi_register_gsi(NULL, acpi_data.maint_irq,
1670 acpi_data.maint_irq_mode,
1671 ACPI_ACTIVE_HIGH);
1672 if (irq <= 0)
1673 return;
1674
1675 gic_v2_kvm_info.maint_irq = irq;
1676
1677 vgic_set_kvm_info(&gic_v2_kvm_info);
1678 }
1679
gic_v2_acpi_init(union acpi_subtable_headers * header,const unsigned long end)1680 static int __init gic_v2_acpi_init(union acpi_subtable_headers *header,
1681 const unsigned long end)
1682 {
1683 struct acpi_madt_generic_distributor *dist;
1684 struct fwnode_handle *domain_handle;
1685 struct gic_chip_data *gic = &gic_data[0];
1686 int count, ret;
1687
1688 /* Collect CPU base addresses */
1689 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
1690 gic_acpi_parse_madt_cpu, 0);
1691 if (count <= 0) {
1692 pr_err("No valid GICC entries exist\n");
1693 return -EINVAL;
1694 }
1695
1696 gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE);
1697 if (!gic->raw_cpu_base) {
1698 pr_err("Unable to map GICC registers\n");
1699 return -ENOMEM;
1700 }
1701
1702 dist = (struct acpi_madt_generic_distributor *)header;
1703 gic->raw_dist_base = ioremap(dist->base_address,
1704 ACPI_GICV2_DIST_MEM_SIZE);
1705 if (!gic->raw_dist_base) {
1706 pr_err("Unable to map GICD registers\n");
1707 gic_teardown(gic);
1708 return -ENOMEM;
1709 }
1710
1711 /*
1712 * Disable split EOI/Deactivate if HYP is not available. ACPI
1713 * guarantees that we'll always have a GICv2, so the CPU
1714 * interface will always be the right size.
1715 */
1716 if (!is_hyp_mode_available())
1717 static_branch_disable(&supports_deactivate_key);
1718
1719 /*
1720 * Initialize GIC instance zero (no multi-GIC support).
1721 */
1722 domain_handle = irq_domain_alloc_fwnode(&dist->base_address);
1723 if (!domain_handle) {
1724 pr_err("Unable to allocate domain handle\n");
1725 gic_teardown(gic);
1726 return -ENOMEM;
1727 }
1728
1729 ret = __gic_init_bases(gic, domain_handle);
1730 if (ret) {
1731 pr_err("Failed to initialise GIC\n");
1732 irq_domain_free_fwnode(domain_handle);
1733 gic_teardown(gic);
1734 return ret;
1735 }
1736
1737 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
1738
1739 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1740 gicv2m_init(NULL, gic_data[0].domain);
1741
1742 if (static_branch_likely(&supports_deactivate_key))
1743 gic_acpi_setup_kvm_info();
1744
1745 return 0;
1746 }
1747 IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1748 gic_validate_dist, ACPI_MADT_GIC_VERSION_V2,
1749 gic_v2_acpi_init);
1750 IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1751 gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE,
1752 gic_v2_acpi_init);
1753 #endif
1754