1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Marvell 88e6xxx Ethernet switch single-chip support
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 *
7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 *
9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
11 */
12
13 #include <linux/bitfield.h>
14 #include <linux/delay.h>
15 #include <linux/dsa/mv88e6xxx.h>
16 #include <linux/etherdevice.h>
17 #include <linux/ethtool.h>
18 #include <linux/if_bridge.h>
19 #include <linux/interrupt.h>
20 #include <linux/irq.h>
21 #include <linux/irqdomain.h>
22 #include <linux/jiffies.h>
23 #include <linux/list.h>
24 #include <linux/mdio.h>
25 #include <linux/module.h>
26 #include <linux/of_device.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_mdio.h>
29 #include <linux/platform_data/mv88e6xxx.h>
30 #include <linux/netdevice.h>
31 #include <linux/gpio/consumer.h>
32 #include <linux/phylink.h>
33 #include <net/dsa.h>
34
35 #include "chip.h"
36 #include "devlink.h"
37 #include "global1.h"
38 #include "global2.h"
39 #include "hwtstamp.h"
40 #include "phy.h"
41 #include "port.h"
42 #include "ptp.h"
43 #include "serdes.h"
44 #include "smi.h"
45
assert_reg_lock(struct mv88e6xxx_chip * chip)46 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
47 {
48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
49 dev_err(chip->dev, "Switch registers lock not held!\n");
50 dump_stack();
51 }
52 }
53
mv88e6xxx_read(struct mv88e6xxx_chip * chip,int addr,int reg,u16 * val)54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
55 {
56 int err;
57
58 assert_reg_lock(chip);
59
60 err = mv88e6xxx_smi_read(chip, addr, reg, val);
61 if (err)
62 return err;
63
64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
65 addr, reg, *val);
66
67 return 0;
68 }
69
mv88e6xxx_write(struct mv88e6xxx_chip * chip,int addr,int reg,u16 val)70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
71 {
72 int err;
73
74 assert_reg_lock(chip);
75
76 err = mv88e6xxx_smi_write(chip, addr, reg, val);
77 if (err)
78 return err;
79
80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
81 addr, reg, val);
82
83 return 0;
84 }
85
mv88e6xxx_wait_mask(struct mv88e6xxx_chip * chip,int addr,int reg,u16 mask,u16 val)86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
87 u16 mask, u16 val)
88 {
89 u16 data;
90 int err;
91 int i;
92
93 /* There's no bus specific operation to wait for a mask */
94 for (i = 0; i < 16; i++) {
95 err = mv88e6xxx_read(chip, addr, reg, &data);
96 if (err)
97 return err;
98
99 if ((data & mask) == val)
100 return 0;
101
102 usleep_range(1000, 2000);
103 }
104
105 dev_err(chip->dev, "Timeout while waiting for switch\n");
106 return -ETIMEDOUT;
107 }
108
mv88e6xxx_wait_bit(struct mv88e6xxx_chip * chip,int addr,int reg,int bit,int val)109 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
110 int bit, int val)
111 {
112 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
113 val ? BIT(bit) : 0x0000);
114 }
115
mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip * chip)116 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
117 {
118 struct mv88e6xxx_mdio_bus *mdio_bus;
119
120 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
121 list);
122 if (!mdio_bus)
123 return NULL;
124
125 return mdio_bus->bus;
126 }
127
mv88e6xxx_g1_irq_mask(struct irq_data * d)128 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
129 {
130 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
131 unsigned int n = d->hwirq;
132
133 chip->g1_irq.masked |= (1 << n);
134 }
135
mv88e6xxx_g1_irq_unmask(struct irq_data * d)136 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
137 {
138 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
139 unsigned int n = d->hwirq;
140
141 chip->g1_irq.masked &= ~(1 << n);
142 }
143
mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip * chip)144 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
145 {
146 unsigned int nhandled = 0;
147 unsigned int sub_irq;
148 unsigned int n;
149 u16 reg;
150 u16 ctl1;
151 int err;
152
153 mv88e6xxx_reg_lock(chip);
154 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
155 mv88e6xxx_reg_unlock(chip);
156
157 if (err)
158 goto out;
159
160 do {
161 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
162 if (reg & (1 << n)) {
163 sub_irq = irq_find_mapping(chip->g1_irq.domain,
164 n);
165 handle_nested_irq(sub_irq);
166 ++nhandled;
167 }
168 }
169
170 mv88e6xxx_reg_lock(chip);
171 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
172 if (err)
173 goto unlock;
174 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
175 unlock:
176 mv88e6xxx_reg_unlock(chip);
177 if (err)
178 goto out;
179 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
180 } while (reg & ctl1);
181
182 out:
183 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
184 }
185
mv88e6xxx_g1_irq_thread_fn(int irq,void * dev_id)186 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
187 {
188 struct mv88e6xxx_chip *chip = dev_id;
189
190 return mv88e6xxx_g1_irq_thread_work(chip);
191 }
192
mv88e6xxx_g1_irq_bus_lock(struct irq_data * d)193 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
194 {
195 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
196
197 mv88e6xxx_reg_lock(chip);
198 }
199
mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data * d)200 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
201 {
202 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
203 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
204 u16 reg;
205 int err;
206
207 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®);
208 if (err)
209 goto out;
210
211 reg &= ~mask;
212 reg |= (~chip->g1_irq.masked & mask);
213
214 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
215 if (err)
216 goto out;
217
218 out:
219 mv88e6xxx_reg_unlock(chip);
220 }
221
222 static const struct irq_chip mv88e6xxx_g1_irq_chip = {
223 .name = "mv88e6xxx-g1",
224 .irq_mask = mv88e6xxx_g1_irq_mask,
225 .irq_unmask = mv88e6xxx_g1_irq_unmask,
226 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
227 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
228 };
229
mv88e6xxx_g1_irq_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)230 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
231 unsigned int irq,
232 irq_hw_number_t hwirq)
233 {
234 struct mv88e6xxx_chip *chip = d->host_data;
235
236 irq_set_chip_data(irq, d->host_data);
237 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
238 irq_set_noprobe(irq);
239
240 return 0;
241 }
242
243 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
244 .map = mv88e6xxx_g1_irq_domain_map,
245 .xlate = irq_domain_xlate_twocell,
246 };
247
248 /* To be called with reg_lock held */
mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip * chip)249 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
250 {
251 int irq, virq;
252 u16 mask;
253
254 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
255 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
256 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
257
258 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
259 virq = irq_find_mapping(chip->g1_irq.domain, irq);
260 irq_dispose_mapping(virq);
261 }
262
263 irq_domain_remove(chip->g1_irq.domain);
264 }
265
mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip * chip)266 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
267 {
268 /*
269 * free_irq must be called without reg_lock taken because the irq
270 * handler takes this lock, too.
271 */
272 free_irq(chip->irq, chip);
273
274 mv88e6xxx_reg_lock(chip);
275 mv88e6xxx_g1_irq_free_common(chip);
276 mv88e6xxx_reg_unlock(chip);
277 }
278
mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip * chip)279 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
280 {
281 int err, irq, virq;
282 u16 reg, mask;
283
284 chip->g1_irq.nirqs = chip->info->g1_irqs;
285 chip->g1_irq.domain = irq_domain_add_simple(
286 NULL, chip->g1_irq.nirqs, 0,
287 &mv88e6xxx_g1_irq_domain_ops, chip);
288 if (!chip->g1_irq.domain)
289 return -ENOMEM;
290
291 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
292 irq_create_mapping(chip->g1_irq.domain, irq);
293
294 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
295 chip->g1_irq.masked = ~0;
296
297 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
298 if (err)
299 goto out_mapping;
300
301 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
302
303 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
304 if (err)
305 goto out_disable;
306
307 /* Reading the interrupt status clears (most of) them */
308 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
309 if (err)
310 goto out_disable;
311
312 return 0;
313
314 out_disable:
315 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
316 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
317
318 out_mapping:
319 for (irq = 0; irq < 16; irq++) {
320 virq = irq_find_mapping(chip->g1_irq.domain, irq);
321 irq_dispose_mapping(virq);
322 }
323
324 irq_domain_remove(chip->g1_irq.domain);
325
326 return err;
327 }
328
mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip * chip)329 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
330 {
331 static struct lock_class_key lock_key;
332 static struct lock_class_key request_key;
333 int err;
334
335 err = mv88e6xxx_g1_irq_setup_common(chip);
336 if (err)
337 return err;
338
339 /* These lock classes tells lockdep that global 1 irqs are in
340 * a different category than their parent GPIO, so it won't
341 * report false recursion.
342 */
343 irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
344
345 snprintf(chip->irq_name, sizeof(chip->irq_name),
346 "mv88e6xxx-%s", dev_name(chip->dev));
347
348 mv88e6xxx_reg_unlock(chip);
349 err = request_threaded_irq(chip->irq, NULL,
350 mv88e6xxx_g1_irq_thread_fn,
351 IRQF_ONESHOT | IRQF_SHARED,
352 chip->irq_name, chip);
353 mv88e6xxx_reg_lock(chip);
354 if (err)
355 mv88e6xxx_g1_irq_free_common(chip);
356
357 return err;
358 }
359
mv88e6xxx_irq_poll(struct kthread_work * work)360 static void mv88e6xxx_irq_poll(struct kthread_work *work)
361 {
362 struct mv88e6xxx_chip *chip = container_of(work,
363 struct mv88e6xxx_chip,
364 irq_poll_work.work);
365 mv88e6xxx_g1_irq_thread_work(chip);
366
367 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
368 msecs_to_jiffies(100));
369 }
370
mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip * chip)371 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
372 {
373 int err;
374
375 err = mv88e6xxx_g1_irq_setup_common(chip);
376 if (err)
377 return err;
378
379 kthread_init_delayed_work(&chip->irq_poll_work,
380 mv88e6xxx_irq_poll);
381
382 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
383 if (IS_ERR(chip->kworker))
384 return PTR_ERR(chip->kworker);
385
386 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
387 msecs_to_jiffies(100));
388
389 return 0;
390 }
391
mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip * chip)392 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
393 {
394 kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
395 kthread_destroy_worker(chip->kworker);
396
397 mv88e6xxx_reg_lock(chip);
398 mv88e6xxx_g1_irq_free_common(chip);
399 mv88e6xxx_reg_unlock(chip);
400 }
401
mv88e6xxx_port_config_interface(struct mv88e6xxx_chip * chip,int port,phy_interface_t interface)402 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
403 int port, phy_interface_t interface)
404 {
405 int err;
406
407 if (chip->info->ops->port_set_rgmii_delay) {
408 err = chip->info->ops->port_set_rgmii_delay(chip, port,
409 interface);
410 if (err && err != -EOPNOTSUPP)
411 return err;
412 }
413
414 if (chip->info->ops->port_set_cmode) {
415 err = chip->info->ops->port_set_cmode(chip, port,
416 interface);
417 if (err && err != -EOPNOTSUPP)
418 return err;
419 }
420
421 return 0;
422 }
423
mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip * chip,int port,int link,int speed,int duplex,int pause,phy_interface_t mode)424 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
425 int link, int speed, int duplex, int pause,
426 phy_interface_t mode)
427 {
428 int err;
429
430 if (!chip->info->ops->port_set_link)
431 return 0;
432
433 /* Port's MAC control must not be changed unless the link is down */
434 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
435 if (err)
436 return err;
437
438 if (chip->info->ops->port_set_speed_duplex) {
439 err = chip->info->ops->port_set_speed_duplex(chip, port,
440 speed, duplex);
441 if (err && err != -EOPNOTSUPP)
442 goto restore_link;
443 }
444
445 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode)
446 mode = chip->info->ops->port_max_speed_mode(port);
447
448 if (chip->info->ops->port_set_pause) {
449 err = chip->info->ops->port_set_pause(chip, port, pause);
450 if (err)
451 goto restore_link;
452 }
453
454 err = mv88e6xxx_port_config_interface(chip, port, mode);
455 restore_link:
456 if (chip->info->ops->port_set_link(chip, port, link))
457 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
458
459 return err;
460 }
461
mv88e6xxx_phy_is_internal(struct dsa_switch * ds,int port)462 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port)
463 {
464 struct mv88e6xxx_chip *chip = ds->priv;
465
466 return port < chip->info->num_internal_phys;
467 }
468
mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip * chip,int port)469 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
470 {
471 u16 reg;
472 int err;
473
474 /* The 88e6250 family does not have the PHY detect bit. Instead,
475 * report whether the port is internal.
476 */
477 if (chip->info->family == MV88E6XXX_FAMILY_6250)
478 return port < chip->info->num_internal_phys;
479
480 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
481 if (err) {
482 dev_err(chip->dev,
483 "p%d: %s: failed to read port status\n",
484 port, __func__);
485 return err;
486 }
487
488 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
489 }
490
mv88e6xxx_serdes_pcs_get_state(struct dsa_switch * ds,int port,struct phylink_link_state * state)491 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port,
492 struct phylink_link_state *state)
493 {
494 struct mv88e6xxx_chip *chip = ds->priv;
495 int lane;
496 int err;
497
498 mv88e6xxx_reg_lock(chip);
499 lane = mv88e6xxx_serdes_get_lane(chip, port);
500 if (lane >= 0 && chip->info->ops->serdes_pcs_get_state)
501 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane,
502 state);
503 else
504 err = -EOPNOTSUPP;
505 mv88e6xxx_reg_unlock(chip);
506
507 return err;
508 }
509
mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip * chip,int port,unsigned int mode,phy_interface_t interface,const unsigned long * advertise)510 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
511 unsigned int mode,
512 phy_interface_t interface,
513 const unsigned long *advertise)
514 {
515 const struct mv88e6xxx_ops *ops = chip->info->ops;
516 int lane;
517
518 if (ops->serdes_pcs_config) {
519 lane = mv88e6xxx_serdes_get_lane(chip, port);
520 if (lane >= 0)
521 return ops->serdes_pcs_config(chip, port, lane, mode,
522 interface, advertise);
523 }
524
525 return 0;
526 }
527
mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch * ds,int port)528 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port)
529 {
530 struct mv88e6xxx_chip *chip = ds->priv;
531 const struct mv88e6xxx_ops *ops;
532 int err = 0;
533 int lane;
534
535 ops = chip->info->ops;
536
537 if (ops->serdes_pcs_an_restart) {
538 mv88e6xxx_reg_lock(chip);
539 lane = mv88e6xxx_serdes_get_lane(chip, port);
540 if (lane >= 0)
541 err = ops->serdes_pcs_an_restart(chip, port, lane);
542 mv88e6xxx_reg_unlock(chip);
543
544 if (err)
545 dev_err(ds->dev, "p%d: failed to restart AN\n", port);
546 }
547 }
548
mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip * chip,int port,unsigned int mode,int speed,int duplex)549 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
550 unsigned int mode,
551 int speed, int duplex)
552 {
553 const struct mv88e6xxx_ops *ops = chip->info->ops;
554 int lane;
555
556 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) {
557 lane = mv88e6xxx_serdes_get_lane(chip, port);
558 if (lane >= 0)
559 return ops->serdes_pcs_link_up(chip, port, lane,
560 speed, duplex);
561 }
562
563 return 0;
564 }
565
mv88e6065_phylink_validate(struct mv88e6xxx_chip * chip,int port,unsigned long * mask,struct phylink_link_state * state)566 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port,
567 unsigned long *mask,
568 struct phylink_link_state *state)
569 {
570 if (!phy_interface_mode_is_8023z(state->interface)) {
571 /* 10M and 100M are only supported in non-802.3z mode */
572 phylink_set(mask, 10baseT_Half);
573 phylink_set(mask, 10baseT_Full);
574 phylink_set(mask, 100baseT_Half);
575 phylink_set(mask, 100baseT_Full);
576 }
577 }
578
mv88e6185_phylink_validate(struct mv88e6xxx_chip * chip,int port,unsigned long * mask,struct phylink_link_state * state)579 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port,
580 unsigned long *mask,
581 struct phylink_link_state *state)
582 {
583 /* FIXME: if the port is in 1000Base-X mode, then it only supports
584 * 1000M FD speeds. In this case, CMODE will indicate 5.
585 */
586 phylink_set(mask, 1000baseT_Full);
587 phylink_set(mask, 1000baseX_Full);
588
589 mv88e6065_phylink_validate(chip, port, mask, state);
590 }
591
mv88e6341_phylink_validate(struct mv88e6xxx_chip * chip,int port,unsigned long * mask,struct phylink_link_state * state)592 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port,
593 unsigned long *mask,
594 struct phylink_link_state *state)
595 {
596 if (port >= 5)
597 phylink_set(mask, 2500baseX_Full);
598
599 /* No ethtool bits for 200Mbps */
600 phylink_set(mask, 1000baseT_Full);
601 phylink_set(mask, 1000baseX_Full);
602
603 mv88e6065_phylink_validate(chip, port, mask, state);
604 }
605
mv88e6352_phylink_validate(struct mv88e6xxx_chip * chip,int port,unsigned long * mask,struct phylink_link_state * state)606 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port,
607 unsigned long *mask,
608 struct phylink_link_state *state)
609 {
610 /* No ethtool bits for 200Mbps */
611 phylink_set(mask, 1000baseT_Full);
612 phylink_set(mask, 1000baseX_Full);
613
614 mv88e6065_phylink_validate(chip, port, mask, state);
615 }
616
mv88e6390_phylink_validate(struct mv88e6xxx_chip * chip,int port,unsigned long * mask,struct phylink_link_state * state)617 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port,
618 unsigned long *mask,
619 struct phylink_link_state *state)
620 {
621 if (port >= 9) {
622 phylink_set(mask, 2500baseX_Full);
623 phylink_set(mask, 2500baseT_Full);
624 }
625
626 /* No ethtool bits for 200Mbps */
627 phylink_set(mask, 1000baseT_Full);
628 phylink_set(mask, 1000baseX_Full);
629
630 mv88e6065_phylink_validate(chip, port, mask, state);
631 }
632
mv88e6390x_phylink_validate(struct mv88e6xxx_chip * chip,int port,unsigned long * mask,struct phylink_link_state * state)633 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
634 unsigned long *mask,
635 struct phylink_link_state *state)
636 {
637 if (port >= 9) {
638 phylink_set(mask, 10000baseT_Full);
639 phylink_set(mask, 10000baseKR_Full);
640 }
641
642 mv88e6390_phylink_validate(chip, port, mask, state);
643 }
644
mv88e6393x_phylink_validate(struct mv88e6xxx_chip * chip,int port,unsigned long * mask,struct phylink_link_state * state)645 static void mv88e6393x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
646 unsigned long *mask,
647 struct phylink_link_state *state)
648 {
649 bool is_6191x =
650 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X;
651
652 if (((port == 0 || port == 9) && !is_6191x) || port == 10) {
653 phylink_set(mask, 10000baseT_Full);
654 phylink_set(mask, 10000baseKR_Full);
655 phylink_set(mask, 10000baseCR_Full);
656 phylink_set(mask, 10000baseSR_Full);
657 phylink_set(mask, 10000baseLR_Full);
658 phylink_set(mask, 10000baseLRM_Full);
659 phylink_set(mask, 10000baseER_Full);
660 phylink_set(mask, 5000baseT_Full);
661 phylink_set(mask, 2500baseX_Full);
662 phylink_set(mask, 2500baseT_Full);
663 }
664
665 phylink_set(mask, 1000baseT_Full);
666 phylink_set(mask, 1000baseX_Full);
667
668 mv88e6065_phylink_validate(chip, port, mask, state);
669 }
670
mv88e6xxx_validate(struct dsa_switch * ds,int port,unsigned long * supported,struct phylink_link_state * state)671 static void mv88e6xxx_validate(struct dsa_switch *ds, int port,
672 unsigned long *supported,
673 struct phylink_link_state *state)
674 {
675 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
676 struct mv88e6xxx_chip *chip = ds->priv;
677
678 /* Allow all the expected bits */
679 phylink_set(mask, Autoneg);
680 phylink_set(mask, Pause);
681 phylink_set_port_modes(mask);
682
683 if (chip->info->ops->phylink_validate)
684 chip->info->ops->phylink_validate(chip, port, mask, state);
685
686 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
687 bitmap_and(state->advertising, state->advertising, mask,
688 __ETHTOOL_LINK_MODE_MASK_NBITS);
689
690 /* We can only operate at 2500BaseX or 1000BaseX. If requested
691 * to advertise both, only report advertising at 2500BaseX.
692 */
693 phylink_helper_basex_speed(state);
694 }
695
mv88e6xxx_mac_config(struct dsa_switch * ds,int port,unsigned int mode,const struct phylink_link_state * state)696 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
697 unsigned int mode,
698 const struct phylink_link_state *state)
699 {
700 struct mv88e6xxx_chip *chip = ds->priv;
701 struct mv88e6xxx_port *p;
702 int err = 0;
703
704 p = &chip->ports[port];
705
706 mv88e6xxx_reg_lock(chip);
707
708 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(ds, port)) {
709 /* In inband mode, the link may come up at any time while the
710 * link is not forced down. Force the link down while we
711 * reconfigure the interface mode.
712 */
713 if (mode == MLO_AN_INBAND &&
714 p->interface != state->interface &&
715 chip->info->ops->port_set_link)
716 chip->info->ops->port_set_link(chip, port,
717 LINK_FORCED_DOWN);
718
719 err = mv88e6xxx_port_config_interface(chip, port,
720 state->interface);
721 if (err && err != -EOPNOTSUPP)
722 goto err_unlock;
723
724 err = mv88e6xxx_serdes_pcs_config(chip, port, mode,
725 state->interface,
726 state->advertising);
727 /* FIXME: we should restart negotiation if something changed -
728 * which is something we get if we convert to using phylinks
729 * PCS operations.
730 */
731 if (err > 0)
732 err = 0;
733 }
734
735 /* Undo the forced down state above after completing configuration
736 * irrespective of its state on entry, which allows the link to come
737 * up in the in-band case where there is no separate SERDES. Also
738 * ensure that the link can come up if the PPU is in use and we are
739 * in PHY mode (we treat the PPU as an effective in-band mechanism.)
740 */
741 if (chip->info->ops->port_set_link &&
742 ((mode == MLO_AN_INBAND && p->interface != state->interface) ||
743 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port))))
744 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
745
746 p->interface = state->interface;
747
748 err_unlock:
749 mv88e6xxx_reg_unlock(chip);
750
751 if (err && err != -EOPNOTSUPP)
752 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port);
753 }
754
mv88e6xxx_mac_link_down(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)755 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
756 unsigned int mode,
757 phy_interface_t interface)
758 {
759 struct mv88e6xxx_chip *chip = ds->priv;
760 const struct mv88e6xxx_ops *ops;
761 int err = 0;
762
763 ops = chip->info->ops;
764
765 mv88e6xxx_reg_lock(chip);
766 /* Force the link down if we know the port may not be automatically
767 * updated by the switch or if we are using fixed-link mode.
768 */
769 if ((!mv88e6xxx_port_ppu_updates(chip, port) ||
770 mode == MLO_AN_FIXED) && ops->port_sync_link)
771 err = ops->port_sync_link(chip, port, mode, false);
772
773 if (!err && ops->port_set_speed_duplex)
774 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED,
775 DUPLEX_UNFORCED);
776 mv88e6xxx_reg_unlock(chip);
777
778 if (err)
779 dev_err(chip->dev,
780 "p%d: failed to force MAC link down\n", port);
781 }
782
mv88e6xxx_mac_link_up(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface,struct phy_device * phydev,int speed,int duplex,bool tx_pause,bool rx_pause)783 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
784 unsigned int mode, phy_interface_t interface,
785 struct phy_device *phydev,
786 int speed, int duplex,
787 bool tx_pause, bool rx_pause)
788 {
789 struct mv88e6xxx_chip *chip = ds->priv;
790 const struct mv88e6xxx_ops *ops;
791 int err = 0;
792
793 ops = chip->info->ops;
794
795 mv88e6xxx_reg_lock(chip);
796 /* Configure and force the link up if we know that the port may not
797 * automatically updated by the switch or if we are using fixed-link
798 * mode.
799 */
800 if (!mv88e6xxx_port_ppu_updates(chip, port) ||
801 mode == MLO_AN_FIXED) {
802 /* FIXME: for an automedia port, should we force the link
803 * down here - what if the link comes up due to "other" media
804 * while we're bringing the port up, how is the exclusivity
805 * handled in the Marvell hardware? E.g. port 2 on 88E6390
806 * shared between internal PHY and Serdes.
807 */
808 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed,
809 duplex);
810 if (err)
811 goto error;
812
813 if (ops->port_set_speed_duplex) {
814 err = ops->port_set_speed_duplex(chip, port,
815 speed, duplex);
816 if (err && err != -EOPNOTSUPP)
817 goto error;
818 }
819
820 if (ops->port_sync_link)
821 err = ops->port_sync_link(chip, port, mode, true);
822 }
823 error:
824 mv88e6xxx_reg_unlock(chip);
825
826 if (err && err != -EOPNOTSUPP)
827 dev_err(ds->dev,
828 "p%d: failed to configure MAC link up\n", port);
829 }
830
mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip * chip,int port)831 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
832 {
833 if (!chip->info->ops->stats_snapshot)
834 return -EOPNOTSUPP;
835
836 return chip->info->ops->stats_snapshot(chip, port);
837 }
838
839 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
840 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
841 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
842 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
843 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
844 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
845 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
846 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
847 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
848 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
849 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
850 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
851 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
852 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
853 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
854 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
855 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
856 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
857 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
858 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
859 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
860 { "single", 4, 0x14, STATS_TYPE_BANK0, },
861 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
862 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
863 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
864 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
865 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
866 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
867 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
868 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
869 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
870 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
871 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
872 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
873 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
874 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
875 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
876 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
877 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
878 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
879 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
880 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
881 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
882 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
883 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
884 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
885 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
886 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
887 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
888 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
889 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
890 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
891 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
892 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
893 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
894 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
895 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
896 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
897 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
898 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
899 };
900
_mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip * chip,struct mv88e6xxx_hw_stat * s,int port,u16 bank1_select,u16 histogram)901 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
902 struct mv88e6xxx_hw_stat *s,
903 int port, u16 bank1_select,
904 u16 histogram)
905 {
906 u32 low;
907 u32 high = 0;
908 u16 reg = 0;
909 int err;
910 u64 value;
911
912 switch (s->type) {
913 case STATS_TYPE_PORT:
914 err = mv88e6xxx_port_read(chip, port, s->reg, ®);
915 if (err)
916 return U64_MAX;
917
918 low = reg;
919 if (s->size == 4) {
920 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
921 if (err)
922 return U64_MAX;
923 low |= ((u32)reg) << 16;
924 }
925 break;
926 case STATS_TYPE_BANK1:
927 reg = bank1_select;
928 fallthrough;
929 case STATS_TYPE_BANK0:
930 reg |= s->reg | histogram;
931 mv88e6xxx_g1_stats_read(chip, reg, &low);
932 if (s->size == 8)
933 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
934 break;
935 default:
936 return U64_MAX;
937 }
938 value = (((u64)high) << 32) | low;
939 return value;
940 }
941
mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data,int types)942 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
943 uint8_t *data, int types)
944 {
945 struct mv88e6xxx_hw_stat *stat;
946 int i, j;
947
948 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
949 stat = &mv88e6xxx_hw_stats[i];
950 if (stat->type & types) {
951 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
952 ETH_GSTRING_LEN);
953 j++;
954 }
955 }
956
957 return j;
958 }
959
mv88e6095_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data)960 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
961 uint8_t *data)
962 {
963 return mv88e6xxx_stats_get_strings(chip, data,
964 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
965 }
966
mv88e6250_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data)967 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
968 uint8_t *data)
969 {
970 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
971 }
972
mv88e6320_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data)973 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
974 uint8_t *data)
975 {
976 return mv88e6xxx_stats_get_strings(chip, data,
977 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
978 }
979
980 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
981 "atu_member_violation",
982 "atu_miss_violation",
983 "atu_full_violation",
984 "vtu_member_violation",
985 "vtu_miss_violation",
986 };
987
mv88e6xxx_atu_vtu_get_strings(uint8_t * data)988 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
989 {
990 unsigned int i;
991
992 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
993 strlcpy(data + i * ETH_GSTRING_LEN,
994 mv88e6xxx_atu_vtu_stats_strings[i],
995 ETH_GSTRING_LEN);
996 }
997
mv88e6xxx_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * data)998 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
999 u32 stringset, uint8_t *data)
1000 {
1001 struct mv88e6xxx_chip *chip = ds->priv;
1002 int count = 0;
1003
1004 if (stringset != ETH_SS_STATS)
1005 return;
1006
1007 mv88e6xxx_reg_lock(chip);
1008
1009 if (chip->info->ops->stats_get_strings)
1010 count = chip->info->ops->stats_get_strings(chip, data);
1011
1012 if (chip->info->ops->serdes_get_strings) {
1013 data += count * ETH_GSTRING_LEN;
1014 count = chip->info->ops->serdes_get_strings(chip, port, data);
1015 }
1016
1017 data += count * ETH_GSTRING_LEN;
1018 mv88e6xxx_atu_vtu_get_strings(data);
1019
1020 mv88e6xxx_reg_unlock(chip);
1021 }
1022
mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip * chip,int types)1023 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
1024 int types)
1025 {
1026 struct mv88e6xxx_hw_stat *stat;
1027 int i, j;
1028
1029 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1030 stat = &mv88e6xxx_hw_stats[i];
1031 if (stat->type & types)
1032 j++;
1033 }
1034 return j;
1035 }
1036
mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip * chip)1037 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1038 {
1039 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1040 STATS_TYPE_PORT);
1041 }
1042
mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip * chip)1043 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1044 {
1045 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
1046 }
1047
mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip * chip)1048 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1049 {
1050 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1051 STATS_TYPE_BANK1);
1052 }
1053
mv88e6xxx_get_sset_count(struct dsa_switch * ds,int port,int sset)1054 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
1055 {
1056 struct mv88e6xxx_chip *chip = ds->priv;
1057 int serdes_count = 0;
1058 int count = 0;
1059
1060 if (sset != ETH_SS_STATS)
1061 return 0;
1062
1063 mv88e6xxx_reg_lock(chip);
1064 if (chip->info->ops->stats_get_sset_count)
1065 count = chip->info->ops->stats_get_sset_count(chip);
1066 if (count < 0)
1067 goto out;
1068
1069 if (chip->info->ops->serdes_get_sset_count)
1070 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1071 port);
1072 if (serdes_count < 0) {
1073 count = serdes_count;
1074 goto out;
1075 }
1076 count += serdes_count;
1077 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1078
1079 out:
1080 mv88e6xxx_reg_unlock(chip);
1081
1082 return count;
1083 }
1084
mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data,int types,u16 bank1_select,u16 histogram)1085 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1086 uint64_t *data, int types,
1087 u16 bank1_select, u16 histogram)
1088 {
1089 struct mv88e6xxx_hw_stat *stat;
1090 int i, j;
1091
1092 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1093 stat = &mv88e6xxx_hw_stats[i];
1094 if (stat->type & types) {
1095 mv88e6xxx_reg_lock(chip);
1096 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1097 bank1_select,
1098 histogram);
1099 mv88e6xxx_reg_unlock(chip);
1100
1101 j++;
1102 }
1103 }
1104 return j;
1105 }
1106
mv88e6095_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1107 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1108 uint64_t *data)
1109 {
1110 return mv88e6xxx_stats_get_stats(chip, port, data,
1111 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
1112 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1113 }
1114
mv88e6250_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1115 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1116 uint64_t *data)
1117 {
1118 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,
1119 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1120 }
1121
mv88e6320_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1122 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1123 uint64_t *data)
1124 {
1125 return mv88e6xxx_stats_get_stats(chip, port, data,
1126 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1127 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1128 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1129 }
1130
mv88e6390_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1131 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1132 uint64_t *data)
1133 {
1134 return mv88e6xxx_stats_get_stats(chip, port, data,
1135 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1136 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1137 0);
1138 }
1139
mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1140 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1141 uint64_t *data)
1142 {
1143 *data++ = chip->ports[port].atu_member_violation;
1144 *data++ = chip->ports[port].atu_miss_violation;
1145 *data++ = chip->ports[port].atu_full_violation;
1146 *data++ = chip->ports[port].vtu_member_violation;
1147 *data++ = chip->ports[port].vtu_miss_violation;
1148 }
1149
mv88e6xxx_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1150 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1151 uint64_t *data)
1152 {
1153 int count = 0;
1154
1155 if (chip->info->ops->stats_get_stats)
1156 count = chip->info->ops->stats_get_stats(chip, port, data);
1157
1158 mv88e6xxx_reg_lock(chip);
1159 if (chip->info->ops->serdes_get_stats) {
1160 data += count;
1161 count = chip->info->ops->serdes_get_stats(chip, port, data);
1162 }
1163 data += count;
1164 mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1165 mv88e6xxx_reg_unlock(chip);
1166 }
1167
mv88e6xxx_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * data)1168 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1169 uint64_t *data)
1170 {
1171 struct mv88e6xxx_chip *chip = ds->priv;
1172 int ret;
1173
1174 mv88e6xxx_reg_lock(chip);
1175
1176 ret = mv88e6xxx_stats_snapshot(chip, port);
1177 mv88e6xxx_reg_unlock(chip);
1178
1179 if (ret < 0)
1180 return;
1181
1182 mv88e6xxx_get_stats(chip, port, data);
1183
1184 }
1185
mv88e6xxx_get_regs_len(struct dsa_switch * ds,int port)1186 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1187 {
1188 struct mv88e6xxx_chip *chip = ds->priv;
1189 int len;
1190
1191 len = 32 * sizeof(u16);
1192 if (chip->info->ops->serdes_get_regs_len)
1193 len += chip->info->ops->serdes_get_regs_len(chip, port);
1194
1195 return len;
1196 }
1197
mv88e6xxx_get_regs(struct dsa_switch * ds,int port,struct ethtool_regs * regs,void * _p)1198 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1199 struct ethtool_regs *regs, void *_p)
1200 {
1201 struct mv88e6xxx_chip *chip = ds->priv;
1202 int err;
1203 u16 reg;
1204 u16 *p = _p;
1205 int i;
1206
1207 regs->version = chip->info->prod_num;
1208
1209 memset(p, 0xff, 32 * sizeof(u16));
1210
1211 mv88e6xxx_reg_lock(chip);
1212
1213 for (i = 0; i < 32; i++) {
1214
1215 err = mv88e6xxx_port_read(chip, port, i, ®);
1216 if (!err)
1217 p[i] = reg;
1218 }
1219
1220 if (chip->info->ops->serdes_get_regs)
1221 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1222
1223 mv88e6xxx_reg_unlock(chip);
1224 }
1225
mv88e6xxx_get_mac_eee(struct dsa_switch * ds,int port,struct ethtool_eee * e)1226 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1227 struct ethtool_eee *e)
1228 {
1229 /* Nothing to do on the port's MAC */
1230 return 0;
1231 }
1232
mv88e6xxx_set_mac_eee(struct dsa_switch * ds,int port,struct ethtool_eee * e)1233 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1234 struct ethtool_eee *e)
1235 {
1236 /* Nothing to do on the port's MAC */
1237 return 0;
1238 }
1239
1240 /* Mask of the local ports allowed to receive frames from a given fabric port */
mv88e6xxx_port_vlan(struct mv88e6xxx_chip * chip,int dev,int port)1241 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1242 {
1243 struct dsa_switch *ds = chip->ds;
1244 struct dsa_switch_tree *dst = ds->dst;
1245 struct net_device *br;
1246 struct dsa_port *dp;
1247 bool found = false;
1248 u16 pvlan;
1249
1250 /* dev is a physical switch */
1251 if (dev <= dst->last_switch) {
1252 list_for_each_entry(dp, &dst->ports, list) {
1253 if (dp->ds->index == dev && dp->index == port) {
1254 /* dp might be a DSA link or a user port, so it
1255 * might or might not have a bridge_dev
1256 * pointer. Use the "found" variable for both
1257 * cases.
1258 */
1259 br = dp->bridge_dev;
1260 found = true;
1261 break;
1262 }
1263 }
1264 /* dev is a virtual bridge */
1265 } else {
1266 list_for_each_entry(dp, &dst->ports, list) {
1267 if (dp->bridge_num < 0)
1268 continue;
1269
1270 if (dp->bridge_num + 1 + dst->last_switch != dev)
1271 continue;
1272
1273 br = dp->bridge_dev;
1274 found = true;
1275 break;
1276 }
1277 }
1278
1279 /* Prevent frames from unknown switch or virtual bridge */
1280 if (!found)
1281 return 0;
1282
1283 /* Frames from DSA links and CPU ports can egress any local port */
1284 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
1285 return mv88e6xxx_port_mask(chip);
1286
1287 pvlan = 0;
1288
1289 /* Frames from user ports can egress any local DSA links and CPU ports,
1290 * as well as any local member of their bridge group.
1291 */
1292 list_for_each_entry(dp, &dst->ports, list)
1293 if (dp->ds == ds &&
1294 (dp->type == DSA_PORT_TYPE_CPU ||
1295 dp->type == DSA_PORT_TYPE_DSA ||
1296 (br && dp->bridge_dev == br)))
1297 pvlan |= BIT(dp->index);
1298
1299 return pvlan;
1300 }
1301
mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip * chip,int port)1302 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1303 {
1304 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1305
1306 /* prevent frames from going back out of the port they came in on */
1307 output_ports &= ~BIT(port);
1308
1309 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1310 }
1311
mv88e6xxx_port_stp_state_set(struct dsa_switch * ds,int port,u8 state)1312 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1313 u8 state)
1314 {
1315 struct mv88e6xxx_chip *chip = ds->priv;
1316 int err;
1317
1318 mv88e6xxx_reg_lock(chip);
1319 err = mv88e6xxx_port_set_state(chip, port, state);
1320 mv88e6xxx_reg_unlock(chip);
1321
1322 if (err)
1323 dev_err(ds->dev, "p%d: failed to update state\n", port);
1324 }
1325
mv88e6xxx_pri_setup(struct mv88e6xxx_chip * chip)1326 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1327 {
1328 int err;
1329
1330 if (chip->info->ops->ieee_pri_map) {
1331 err = chip->info->ops->ieee_pri_map(chip);
1332 if (err)
1333 return err;
1334 }
1335
1336 if (chip->info->ops->ip_pri_map) {
1337 err = chip->info->ops->ip_pri_map(chip);
1338 if (err)
1339 return err;
1340 }
1341
1342 return 0;
1343 }
1344
mv88e6xxx_devmap_setup(struct mv88e6xxx_chip * chip)1345 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1346 {
1347 struct dsa_switch *ds = chip->ds;
1348 int target, port;
1349 int err;
1350
1351 if (!chip->info->global2_addr)
1352 return 0;
1353
1354 /* Initialize the routing port to the 32 possible target devices */
1355 for (target = 0; target < 32; target++) {
1356 port = dsa_routing_port(ds, target);
1357 if (port == ds->num_ports)
1358 port = 0x1f;
1359
1360 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1361 if (err)
1362 return err;
1363 }
1364
1365 if (chip->info->ops->set_cascade_port) {
1366 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1367 err = chip->info->ops->set_cascade_port(chip, port);
1368 if (err)
1369 return err;
1370 }
1371
1372 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1373 if (err)
1374 return err;
1375
1376 return 0;
1377 }
1378
mv88e6xxx_trunk_setup(struct mv88e6xxx_chip * chip)1379 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1380 {
1381 /* Clear all trunk masks and mapping */
1382 if (chip->info->global2_addr)
1383 return mv88e6xxx_g2_trunk_clear(chip);
1384
1385 return 0;
1386 }
1387
mv88e6xxx_rmu_setup(struct mv88e6xxx_chip * chip)1388 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1389 {
1390 if (chip->info->ops->rmu_disable)
1391 return chip->info->ops->rmu_disable(chip);
1392
1393 return 0;
1394 }
1395
mv88e6xxx_pot_setup(struct mv88e6xxx_chip * chip)1396 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1397 {
1398 if (chip->info->ops->pot_clear)
1399 return chip->info->ops->pot_clear(chip);
1400
1401 return 0;
1402 }
1403
mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip * chip)1404 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1405 {
1406 if (chip->info->ops->mgmt_rsvd2cpu)
1407 return chip->info->ops->mgmt_rsvd2cpu(chip);
1408
1409 return 0;
1410 }
1411
mv88e6xxx_atu_setup(struct mv88e6xxx_chip * chip)1412 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1413 {
1414 int err;
1415
1416 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1417 if (err)
1418 return err;
1419
1420 /* The chips that have a "learn2all" bit in Global1, ATU
1421 * Control are precisely those whose port registers have a
1422 * Message Port bit in Port Control 1 and hence implement
1423 * ->port_setup_message_port.
1424 */
1425 if (chip->info->ops->port_setup_message_port) {
1426 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1427 if (err)
1428 return err;
1429 }
1430
1431 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1432 }
1433
mv88e6xxx_irl_setup(struct mv88e6xxx_chip * chip)1434 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1435 {
1436 int port;
1437 int err;
1438
1439 if (!chip->info->ops->irl_init_all)
1440 return 0;
1441
1442 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1443 /* Disable ingress rate limiting by resetting all per port
1444 * ingress rate limit resources to their initial state.
1445 */
1446 err = chip->info->ops->irl_init_all(chip, port);
1447 if (err)
1448 return err;
1449 }
1450
1451 return 0;
1452 }
1453
mv88e6xxx_mac_setup(struct mv88e6xxx_chip * chip)1454 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1455 {
1456 if (chip->info->ops->set_switch_mac) {
1457 u8 addr[ETH_ALEN];
1458
1459 eth_random_addr(addr);
1460
1461 return chip->info->ops->set_switch_mac(chip, addr);
1462 }
1463
1464 return 0;
1465 }
1466
mv88e6xxx_pvt_map(struct mv88e6xxx_chip * chip,int dev,int port)1467 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1468 {
1469 struct dsa_switch_tree *dst = chip->ds->dst;
1470 struct dsa_switch *ds;
1471 struct dsa_port *dp;
1472 u16 pvlan = 0;
1473
1474 if (!mv88e6xxx_has_pvt(chip))
1475 return 0;
1476
1477 /* Skip the local source device, which uses in-chip port VLAN */
1478 if (dev != chip->ds->index) {
1479 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1480
1481 ds = dsa_switch_find(dst->index, dev);
1482 dp = ds ? dsa_to_port(ds, port) : NULL;
1483 if (dp && dp->lag_dev) {
1484 /* As the PVT is used to limit flooding of
1485 * FORWARD frames, which use the LAG ID as the
1486 * source port, we must translate dev/port to
1487 * the special "LAG device" in the PVT, using
1488 * the LAG ID as the port number.
1489 */
1490 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK;
1491 port = dsa_lag_id(dst, dp->lag_dev);
1492 }
1493 }
1494
1495 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1496 }
1497
mv88e6xxx_pvt_setup(struct mv88e6xxx_chip * chip)1498 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1499 {
1500 int dev, port;
1501 int err;
1502
1503 if (!mv88e6xxx_has_pvt(chip))
1504 return 0;
1505
1506 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1507 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1508 */
1509 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1510 if (err)
1511 return err;
1512
1513 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1514 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1515 err = mv88e6xxx_pvt_map(chip, dev, port);
1516 if (err)
1517 return err;
1518 }
1519 }
1520
1521 return 0;
1522 }
1523
mv88e6xxx_port_fast_age(struct dsa_switch * ds,int port)1524 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1525 {
1526 struct mv88e6xxx_chip *chip = ds->priv;
1527 int err;
1528
1529 if (dsa_to_port(ds, port)->lag_dev)
1530 /* Hardware is incapable of fast-aging a LAG through a
1531 * regular ATU move operation. Until we have something
1532 * more fancy in place this is a no-op.
1533 */
1534 return;
1535
1536 mv88e6xxx_reg_lock(chip);
1537 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1538 mv88e6xxx_reg_unlock(chip);
1539
1540 if (err)
1541 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
1542 }
1543
mv88e6xxx_vtu_setup(struct mv88e6xxx_chip * chip)1544 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1545 {
1546 if (!mv88e6xxx_max_vid(chip))
1547 return 0;
1548
1549 return mv88e6xxx_g1_vtu_flush(chip);
1550 }
1551
mv88e6xxx_vtu_get(struct mv88e6xxx_chip * chip,u16 vid,struct mv88e6xxx_vtu_entry * entry)1552 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1553 struct mv88e6xxx_vtu_entry *entry)
1554 {
1555 int err;
1556
1557 if (!chip->info->ops->vtu_getnext)
1558 return -EOPNOTSUPP;
1559
1560 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip);
1561 entry->valid = false;
1562
1563 err = chip->info->ops->vtu_getnext(chip, entry);
1564
1565 if (entry->vid != vid)
1566 entry->valid = false;
1567
1568 return err;
1569 }
1570
mv88e6xxx_vtu_walk(struct mv88e6xxx_chip * chip,int (* cb)(struct mv88e6xxx_chip * chip,const struct mv88e6xxx_vtu_entry * entry,void * priv),void * priv)1571 static int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip,
1572 int (*cb)(struct mv88e6xxx_chip *chip,
1573 const struct mv88e6xxx_vtu_entry *entry,
1574 void *priv),
1575 void *priv)
1576 {
1577 struct mv88e6xxx_vtu_entry entry = {
1578 .vid = mv88e6xxx_max_vid(chip),
1579 .valid = false,
1580 };
1581 int err;
1582
1583 if (!chip->info->ops->vtu_getnext)
1584 return -EOPNOTSUPP;
1585
1586 do {
1587 err = chip->info->ops->vtu_getnext(chip, &entry);
1588 if (err)
1589 return err;
1590
1591 if (!entry.valid)
1592 break;
1593
1594 err = cb(chip, &entry, priv);
1595 if (err)
1596 return err;
1597 } while (entry.vid < mv88e6xxx_max_vid(chip));
1598
1599 return 0;
1600 }
1601
mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip * chip,struct mv88e6xxx_vtu_entry * entry)1602 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1603 struct mv88e6xxx_vtu_entry *entry)
1604 {
1605 if (!chip->info->ops->vtu_loadpurge)
1606 return -EOPNOTSUPP;
1607
1608 return chip->info->ops->vtu_loadpurge(chip, entry);
1609 }
1610
mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip * chip,const struct mv88e6xxx_vtu_entry * entry,void * _fid_bitmap)1611 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip,
1612 const struct mv88e6xxx_vtu_entry *entry,
1613 void *_fid_bitmap)
1614 {
1615 unsigned long *fid_bitmap = _fid_bitmap;
1616
1617 set_bit(entry->fid, fid_bitmap);
1618 return 0;
1619 }
1620
mv88e6xxx_fid_map(struct mv88e6xxx_chip * chip,unsigned long * fid_bitmap)1621 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap)
1622 {
1623 int i, err;
1624 u16 fid;
1625
1626 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1627
1628 /* Set every FID bit used by the (un)bridged ports */
1629 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1630 err = mv88e6xxx_port_get_fid(chip, i, &fid);
1631 if (err)
1632 return err;
1633
1634 set_bit(fid, fid_bitmap);
1635 }
1636
1637 /* Set every FID bit used by the VLAN entries */
1638 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap);
1639 }
1640
mv88e6xxx_atu_new(struct mv88e6xxx_chip * chip,u16 * fid)1641 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1642 {
1643 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1644 int err;
1645
1646 err = mv88e6xxx_fid_map(chip, fid_bitmap);
1647 if (err)
1648 return err;
1649
1650 /* The reset value 0x000 is used to indicate that multiple address
1651 * databases are not needed. Return the next positive available.
1652 */
1653 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1654 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1655 return -ENOSPC;
1656
1657 /* Clear the database */
1658 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1659 }
1660
mv88e6xxx_port_check_hw_vlan(struct dsa_switch * ds,int port,u16 vid)1661 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1662 u16 vid)
1663 {
1664 struct mv88e6xxx_chip *chip = ds->priv;
1665 struct mv88e6xxx_vtu_entry vlan;
1666 int i, err;
1667
1668 /* DSA and CPU ports have to be members of multiple vlans */
1669 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1670 return 0;
1671
1672 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
1673 if (err)
1674 return err;
1675
1676 if (!vlan.valid)
1677 return 0;
1678
1679 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1680 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1681 continue;
1682
1683 if (!dsa_to_port(ds, i)->slave)
1684 continue;
1685
1686 if (vlan.member[i] ==
1687 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1688 continue;
1689
1690 if (dsa_to_port(ds, i)->bridge_dev ==
1691 dsa_to_port(ds, port)->bridge_dev)
1692 break; /* same bridge, check next VLAN */
1693
1694 if (!dsa_to_port(ds, i)->bridge_dev)
1695 continue;
1696
1697 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
1698 port, vlan.vid, i,
1699 netdev_name(dsa_to_port(ds, i)->bridge_dev));
1700 return -EOPNOTSUPP;
1701 }
1702
1703 return 0;
1704 }
1705
mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip * chip,int port)1706 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port)
1707 {
1708 struct dsa_port *dp = dsa_to_port(chip->ds, port);
1709 struct mv88e6xxx_port *p = &chip->ports[port];
1710 u16 pvid = MV88E6XXX_VID_STANDALONE;
1711 bool drop_untagged = false;
1712 int err;
1713
1714 if (dp->bridge_dev) {
1715 if (br_vlan_enabled(dp->bridge_dev)) {
1716 pvid = p->bridge_pvid.vid;
1717 drop_untagged = !p->bridge_pvid.valid;
1718 } else {
1719 pvid = MV88E6XXX_VID_BRIDGED;
1720 }
1721 }
1722
1723 err = mv88e6xxx_port_set_pvid(chip, port, pvid);
1724 if (err)
1725 return err;
1726
1727 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged);
1728 }
1729
mv88e6xxx_port_vlan_filtering(struct dsa_switch * ds,int port,bool vlan_filtering,struct netlink_ext_ack * extack)1730 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1731 bool vlan_filtering,
1732 struct netlink_ext_ack *extack)
1733 {
1734 struct mv88e6xxx_chip *chip = ds->priv;
1735 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1736 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1737 int err;
1738
1739 if (!mv88e6xxx_max_vid(chip))
1740 return -EOPNOTSUPP;
1741
1742 mv88e6xxx_reg_lock(chip);
1743
1744 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1745 if (err)
1746 goto unlock;
1747
1748 err = mv88e6xxx_port_commit_pvid(chip, port);
1749 if (err)
1750 goto unlock;
1751
1752 unlock:
1753 mv88e6xxx_reg_unlock(chip);
1754
1755 return err;
1756 }
1757
1758 static int
mv88e6xxx_port_vlan_prepare(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)1759 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1760 const struct switchdev_obj_port_vlan *vlan)
1761 {
1762 struct mv88e6xxx_chip *chip = ds->priv;
1763 int err;
1764
1765 if (!mv88e6xxx_max_vid(chip))
1766 return -EOPNOTSUPP;
1767
1768 /* If the requested port doesn't belong to the same bridge as the VLAN
1769 * members, do not support it (yet) and fallback to software VLAN.
1770 */
1771 mv88e6xxx_reg_lock(chip);
1772 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid);
1773 mv88e6xxx_reg_unlock(chip);
1774
1775 return err;
1776 }
1777
mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip * chip,int port,const unsigned char * addr,u16 vid,u8 state)1778 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1779 const unsigned char *addr, u16 vid,
1780 u8 state)
1781 {
1782 struct mv88e6xxx_atu_entry entry;
1783 struct mv88e6xxx_vtu_entry vlan;
1784 u16 fid;
1785 int err;
1786
1787 /* Ports have two private address databases: one for when the port is
1788 * standalone and one for when the port is under a bridge and the
1789 * 802.1Q mode is disabled. When the port is standalone, DSA wants its
1790 * address database to remain 100% empty, so we never load an ATU entry
1791 * into a standalone port's database. Therefore, translate the null
1792 * VLAN ID into the port's database used for VLAN-unaware bridging.
1793 */
1794 if (vid == 0) {
1795 fid = MV88E6XXX_FID_BRIDGED;
1796 } else {
1797 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
1798 if (err)
1799 return err;
1800
1801 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1802 if (!vlan.valid)
1803 return -EOPNOTSUPP;
1804
1805 fid = vlan.fid;
1806 }
1807
1808 entry.state = 0;
1809 ether_addr_copy(entry.mac, addr);
1810 eth_addr_dec(entry.mac);
1811
1812 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
1813 if (err)
1814 return err;
1815
1816 /* Initialize a fresh ATU entry if it isn't found */
1817 if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
1818 memset(&entry, 0, sizeof(entry));
1819 ether_addr_copy(entry.mac, addr);
1820 }
1821
1822 /* Purge the ATU entry only if no port is using it anymore */
1823 if (!state) {
1824 entry.portvec &= ~BIT(port);
1825 if (!entry.portvec)
1826 entry.state = 0;
1827 } else {
1828 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
1829 entry.portvec = BIT(port);
1830 else
1831 entry.portvec |= BIT(port);
1832
1833 entry.state = state;
1834 }
1835
1836 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
1837 }
1838
mv88e6xxx_policy_apply(struct mv88e6xxx_chip * chip,int port,const struct mv88e6xxx_policy * policy)1839 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
1840 const struct mv88e6xxx_policy *policy)
1841 {
1842 enum mv88e6xxx_policy_mapping mapping = policy->mapping;
1843 enum mv88e6xxx_policy_action action = policy->action;
1844 const u8 *addr = policy->addr;
1845 u16 vid = policy->vid;
1846 u8 state;
1847 int err;
1848 int id;
1849
1850 if (!chip->info->ops->port_set_policy)
1851 return -EOPNOTSUPP;
1852
1853 switch (mapping) {
1854 case MV88E6XXX_POLICY_MAPPING_DA:
1855 case MV88E6XXX_POLICY_MAPPING_SA:
1856 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1857 state = 0; /* Dissociate the port and address */
1858 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1859 is_multicast_ether_addr(addr))
1860 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
1861 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1862 is_unicast_ether_addr(addr))
1863 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
1864 else
1865 return -EOPNOTSUPP;
1866
1867 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1868 state);
1869 if (err)
1870 return err;
1871 break;
1872 default:
1873 return -EOPNOTSUPP;
1874 }
1875
1876 /* Skip the port's policy clearing if the mapping is still in use */
1877 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1878 idr_for_each_entry(&chip->policies, policy, id)
1879 if (policy->port == port &&
1880 policy->mapping == mapping &&
1881 policy->action != action)
1882 return 0;
1883
1884 return chip->info->ops->port_set_policy(chip, port, mapping, action);
1885 }
1886
mv88e6xxx_policy_insert(struct mv88e6xxx_chip * chip,int port,struct ethtool_rx_flow_spec * fs)1887 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
1888 struct ethtool_rx_flow_spec *fs)
1889 {
1890 struct ethhdr *mac_entry = &fs->h_u.ether_spec;
1891 struct ethhdr *mac_mask = &fs->m_u.ether_spec;
1892 enum mv88e6xxx_policy_mapping mapping;
1893 enum mv88e6xxx_policy_action action;
1894 struct mv88e6xxx_policy *policy;
1895 u16 vid = 0;
1896 u8 *addr;
1897 int err;
1898 int id;
1899
1900 if (fs->location != RX_CLS_LOC_ANY)
1901 return -EINVAL;
1902
1903 if (fs->ring_cookie == RX_CLS_FLOW_DISC)
1904 action = MV88E6XXX_POLICY_ACTION_DISCARD;
1905 else
1906 return -EOPNOTSUPP;
1907
1908 switch (fs->flow_type & ~FLOW_EXT) {
1909 case ETHER_FLOW:
1910 if (!is_zero_ether_addr(mac_mask->h_dest) &&
1911 is_zero_ether_addr(mac_mask->h_source)) {
1912 mapping = MV88E6XXX_POLICY_MAPPING_DA;
1913 addr = mac_entry->h_dest;
1914 } else if (is_zero_ether_addr(mac_mask->h_dest) &&
1915 !is_zero_ether_addr(mac_mask->h_source)) {
1916 mapping = MV88E6XXX_POLICY_MAPPING_SA;
1917 addr = mac_entry->h_source;
1918 } else {
1919 /* Cannot support DA and SA mapping in the same rule */
1920 return -EOPNOTSUPP;
1921 }
1922 break;
1923 default:
1924 return -EOPNOTSUPP;
1925 }
1926
1927 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
1928 if (fs->m_ext.vlan_tci != htons(0xffff))
1929 return -EOPNOTSUPP;
1930 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
1931 }
1932
1933 idr_for_each_entry(&chip->policies, policy, id) {
1934 if (policy->port == port && policy->mapping == mapping &&
1935 policy->action == action && policy->vid == vid &&
1936 ether_addr_equal(policy->addr, addr))
1937 return -EEXIST;
1938 }
1939
1940 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
1941 if (!policy)
1942 return -ENOMEM;
1943
1944 fs->location = 0;
1945 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
1946 GFP_KERNEL);
1947 if (err) {
1948 devm_kfree(chip->dev, policy);
1949 return err;
1950 }
1951
1952 memcpy(&policy->fs, fs, sizeof(*fs));
1953 ether_addr_copy(policy->addr, addr);
1954 policy->mapping = mapping;
1955 policy->action = action;
1956 policy->port = port;
1957 policy->vid = vid;
1958
1959 err = mv88e6xxx_policy_apply(chip, port, policy);
1960 if (err) {
1961 idr_remove(&chip->policies, fs->location);
1962 devm_kfree(chip->dev, policy);
1963 return err;
1964 }
1965
1966 return 0;
1967 }
1968
mv88e6xxx_get_rxnfc(struct dsa_switch * ds,int port,struct ethtool_rxnfc * rxnfc,u32 * rule_locs)1969 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
1970 struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
1971 {
1972 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1973 struct mv88e6xxx_chip *chip = ds->priv;
1974 struct mv88e6xxx_policy *policy;
1975 int err;
1976 int id;
1977
1978 mv88e6xxx_reg_lock(chip);
1979
1980 switch (rxnfc->cmd) {
1981 case ETHTOOL_GRXCLSRLCNT:
1982 rxnfc->data = 0;
1983 rxnfc->data |= RX_CLS_LOC_SPECIAL;
1984 rxnfc->rule_cnt = 0;
1985 idr_for_each_entry(&chip->policies, policy, id)
1986 if (policy->port == port)
1987 rxnfc->rule_cnt++;
1988 err = 0;
1989 break;
1990 case ETHTOOL_GRXCLSRULE:
1991 err = -ENOENT;
1992 policy = idr_find(&chip->policies, fs->location);
1993 if (policy) {
1994 memcpy(fs, &policy->fs, sizeof(*fs));
1995 err = 0;
1996 }
1997 break;
1998 case ETHTOOL_GRXCLSRLALL:
1999 rxnfc->data = 0;
2000 rxnfc->rule_cnt = 0;
2001 idr_for_each_entry(&chip->policies, policy, id)
2002 if (policy->port == port)
2003 rule_locs[rxnfc->rule_cnt++] = id;
2004 err = 0;
2005 break;
2006 default:
2007 err = -EOPNOTSUPP;
2008 break;
2009 }
2010
2011 mv88e6xxx_reg_unlock(chip);
2012
2013 return err;
2014 }
2015
mv88e6xxx_set_rxnfc(struct dsa_switch * ds,int port,struct ethtool_rxnfc * rxnfc)2016 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
2017 struct ethtool_rxnfc *rxnfc)
2018 {
2019 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2020 struct mv88e6xxx_chip *chip = ds->priv;
2021 struct mv88e6xxx_policy *policy;
2022 int err;
2023
2024 mv88e6xxx_reg_lock(chip);
2025
2026 switch (rxnfc->cmd) {
2027 case ETHTOOL_SRXCLSRLINS:
2028 err = mv88e6xxx_policy_insert(chip, port, fs);
2029 break;
2030 case ETHTOOL_SRXCLSRLDEL:
2031 err = -ENOENT;
2032 policy = idr_remove(&chip->policies, fs->location);
2033 if (policy) {
2034 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
2035 err = mv88e6xxx_policy_apply(chip, port, policy);
2036 devm_kfree(chip->dev, policy);
2037 }
2038 break;
2039 default:
2040 err = -EOPNOTSUPP;
2041 break;
2042 }
2043
2044 mv88e6xxx_reg_unlock(chip);
2045
2046 return err;
2047 }
2048
mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip * chip,int port,u16 vid)2049 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
2050 u16 vid)
2051 {
2052 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2053 u8 broadcast[ETH_ALEN];
2054
2055 eth_broadcast_addr(broadcast);
2056
2057 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
2058 }
2059
mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip * chip,u16 vid)2060 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
2061 {
2062 int port;
2063 int err;
2064
2065 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2066 struct dsa_port *dp = dsa_to_port(chip->ds, port);
2067 struct net_device *brport;
2068
2069 if (dsa_is_unused_port(chip->ds, port))
2070 continue;
2071
2072 brport = dsa_port_to_bridge_port(dp);
2073 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD))
2074 /* Skip bridged user ports where broadcast
2075 * flooding is disabled.
2076 */
2077 continue;
2078
2079 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
2080 if (err)
2081 return err;
2082 }
2083
2084 return 0;
2085 }
2086
2087 struct mv88e6xxx_port_broadcast_sync_ctx {
2088 int port;
2089 bool flood;
2090 };
2091
2092 static int
mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip * chip,const struct mv88e6xxx_vtu_entry * vlan,void * _ctx)2093 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip,
2094 const struct mv88e6xxx_vtu_entry *vlan,
2095 void *_ctx)
2096 {
2097 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx;
2098 u8 broadcast[ETH_ALEN];
2099 u8 state;
2100
2101 if (ctx->flood)
2102 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2103 else
2104 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED;
2105
2106 eth_broadcast_addr(broadcast);
2107
2108 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast,
2109 vlan->vid, state);
2110 }
2111
mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip * chip,int port,bool flood)2112 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port,
2113 bool flood)
2114 {
2115 struct mv88e6xxx_port_broadcast_sync_ctx ctx = {
2116 .port = port,
2117 .flood = flood,
2118 };
2119 struct mv88e6xxx_vtu_entry vid0 = {
2120 .vid = 0,
2121 };
2122 int err;
2123
2124 /* Update the port's private database... */
2125 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx);
2126 if (err)
2127 return err;
2128
2129 /* ...and the database for all VLANs. */
2130 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan,
2131 &ctx);
2132 }
2133
mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip * chip,int port,u16 vid,u8 member,bool warn)2134 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
2135 u16 vid, u8 member, bool warn)
2136 {
2137 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2138 struct mv88e6xxx_vtu_entry vlan;
2139 int i, err;
2140
2141 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2142 if (err)
2143 return err;
2144
2145 if (!vlan.valid) {
2146 memset(&vlan, 0, sizeof(vlan));
2147
2148 err = mv88e6xxx_atu_new(chip, &vlan.fid);
2149 if (err)
2150 return err;
2151
2152 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2153 if (i == port)
2154 vlan.member[i] = member;
2155 else
2156 vlan.member[i] = non_member;
2157
2158 vlan.vid = vid;
2159 vlan.valid = true;
2160
2161 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2162 if (err)
2163 return err;
2164
2165 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
2166 if (err)
2167 return err;
2168 } else if (vlan.member[port] != member) {
2169 vlan.member[port] = member;
2170
2171 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2172 if (err)
2173 return err;
2174 } else if (warn) {
2175 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
2176 port, vid);
2177 }
2178
2179 return 0;
2180 }
2181
mv88e6xxx_port_vlan_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan,struct netlink_ext_ack * extack)2182 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
2183 const struct switchdev_obj_port_vlan *vlan,
2184 struct netlink_ext_ack *extack)
2185 {
2186 struct mv88e6xxx_chip *chip = ds->priv;
2187 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2188 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2189 struct mv88e6xxx_port *p = &chip->ports[port];
2190 bool warn;
2191 u8 member;
2192 int err;
2193
2194 if (!vlan->vid)
2195 return 0;
2196
2197 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan);
2198 if (err)
2199 return err;
2200
2201 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
2202 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
2203 else if (untagged)
2204 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
2205 else
2206 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
2207
2208 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port
2209 * and then the CPU port. Do not warn for duplicates for the CPU port.
2210 */
2211 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
2212
2213 mv88e6xxx_reg_lock(chip);
2214
2215 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn);
2216 if (err) {
2217 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
2218 vlan->vid, untagged ? 'u' : 't');
2219 goto out;
2220 }
2221
2222 if (pvid) {
2223 p->bridge_pvid.vid = vlan->vid;
2224 p->bridge_pvid.valid = true;
2225
2226 err = mv88e6xxx_port_commit_pvid(chip, port);
2227 if (err)
2228 goto out;
2229 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) {
2230 /* The old pvid was reinstalled as a non-pvid VLAN */
2231 p->bridge_pvid.valid = false;
2232
2233 err = mv88e6xxx_port_commit_pvid(chip, port);
2234 if (err)
2235 goto out;
2236 }
2237
2238 out:
2239 mv88e6xxx_reg_unlock(chip);
2240
2241 return err;
2242 }
2243
mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip * chip,int port,u16 vid)2244 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
2245 int port, u16 vid)
2246 {
2247 struct mv88e6xxx_vtu_entry vlan;
2248 int i, err;
2249
2250 if (!vid)
2251 return 0;
2252
2253 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2254 if (err)
2255 return err;
2256
2257 /* If the VLAN doesn't exist in hardware or the port isn't a member,
2258 * tell switchdev that this VLAN is likely handled in software.
2259 */
2260 if (!vlan.valid ||
2261 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2262 return -EOPNOTSUPP;
2263
2264 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2265
2266 /* keep the VLAN unless all ports are excluded */
2267 vlan.valid = false;
2268 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2269 if (vlan.member[i] !=
2270 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2271 vlan.valid = true;
2272 break;
2273 }
2274 }
2275
2276 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2277 if (err)
2278 return err;
2279
2280 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
2281 }
2282
mv88e6xxx_port_vlan_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)2283 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2284 const struct switchdev_obj_port_vlan *vlan)
2285 {
2286 struct mv88e6xxx_chip *chip = ds->priv;
2287 struct mv88e6xxx_port *p = &chip->ports[port];
2288 int err = 0;
2289 u16 pvid;
2290
2291 if (!mv88e6xxx_max_vid(chip))
2292 return -EOPNOTSUPP;
2293
2294 mv88e6xxx_reg_lock(chip);
2295
2296 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
2297 if (err)
2298 goto unlock;
2299
2300 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid);
2301 if (err)
2302 goto unlock;
2303
2304 if (vlan->vid == pvid) {
2305 p->bridge_pvid.valid = false;
2306
2307 err = mv88e6xxx_port_commit_pvid(chip, port);
2308 if (err)
2309 goto unlock;
2310 }
2311
2312 unlock:
2313 mv88e6xxx_reg_unlock(chip);
2314
2315 return err;
2316 }
2317
mv88e6xxx_port_fdb_add(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid)2318 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2319 const unsigned char *addr, u16 vid)
2320 {
2321 struct mv88e6xxx_chip *chip = ds->priv;
2322 int err;
2323
2324 mv88e6xxx_reg_lock(chip);
2325 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2326 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2327 mv88e6xxx_reg_unlock(chip);
2328
2329 return err;
2330 }
2331
mv88e6xxx_port_fdb_del(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid)2332 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2333 const unsigned char *addr, u16 vid)
2334 {
2335 struct mv88e6xxx_chip *chip = ds->priv;
2336 int err;
2337
2338 mv88e6xxx_reg_lock(chip);
2339 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
2340 mv88e6xxx_reg_unlock(chip);
2341
2342 return err;
2343 }
2344
mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip * chip,u16 fid,u16 vid,int port,dsa_fdb_dump_cb_t * cb,void * data)2345 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2346 u16 fid, u16 vid, int port,
2347 dsa_fdb_dump_cb_t *cb, void *data)
2348 {
2349 struct mv88e6xxx_atu_entry addr;
2350 bool is_static;
2351 int err;
2352
2353 addr.state = 0;
2354 eth_broadcast_addr(addr.mac);
2355
2356 do {
2357 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
2358 if (err)
2359 return err;
2360
2361 if (!addr.state)
2362 break;
2363
2364 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
2365 continue;
2366
2367 if (!is_unicast_ether_addr(addr.mac))
2368 continue;
2369
2370 is_static = (addr.state ==
2371 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2372 err = cb(addr.mac, vid, is_static, data);
2373 if (err)
2374 return err;
2375 } while (!is_broadcast_ether_addr(addr.mac));
2376
2377 return err;
2378 }
2379
2380 struct mv88e6xxx_port_db_dump_vlan_ctx {
2381 int port;
2382 dsa_fdb_dump_cb_t *cb;
2383 void *data;
2384 };
2385
mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip * chip,const struct mv88e6xxx_vtu_entry * entry,void * _data)2386 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip,
2387 const struct mv88e6xxx_vtu_entry *entry,
2388 void *_data)
2389 {
2390 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data;
2391
2392 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid,
2393 ctx->port, ctx->cb, ctx->data);
2394 }
2395
mv88e6xxx_port_db_dump(struct mv88e6xxx_chip * chip,int port,dsa_fdb_dump_cb_t * cb,void * data)2396 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2397 dsa_fdb_dump_cb_t *cb, void *data)
2398 {
2399 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = {
2400 .port = port,
2401 .cb = cb,
2402 .data = data,
2403 };
2404 u16 fid;
2405 int err;
2406
2407 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2408 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2409 if (err)
2410 return err;
2411
2412 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2413 if (err)
2414 return err;
2415
2416 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx);
2417 }
2418
mv88e6xxx_port_fdb_dump(struct dsa_switch * ds,int port,dsa_fdb_dump_cb_t * cb,void * data)2419 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2420 dsa_fdb_dump_cb_t *cb, void *data)
2421 {
2422 struct mv88e6xxx_chip *chip = ds->priv;
2423 int err;
2424
2425 mv88e6xxx_reg_lock(chip);
2426 err = mv88e6xxx_port_db_dump(chip, port, cb, data);
2427 mv88e6xxx_reg_unlock(chip);
2428
2429 return err;
2430 }
2431
mv88e6xxx_bridge_map(struct mv88e6xxx_chip * chip,struct net_device * br)2432 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2433 struct net_device *br)
2434 {
2435 struct dsa_switch *ds = chip->ds;
2436 struct dsa_switch_tree *dst = ds->dst;
2437 struct dsa_port *dp;
2438 int err;
2439
2440 list_for_each_entry(dp, &dst->ports, list) {
2441 if (dp->bridge_dev == br) {
2442 if (dp->ds == ds) {
2443 /* This is a local bridge group member,
2444 * remap its Port VLAN Map.
2445 */
2446 err = mv88e6xxx_port_vlan_map(chip, dp->index);
2447 if (err)
2448 return err;
2449 } else {
2450 /* This is an external bridge group member,
2451 * remap its cross-chip Port VLAN Table entry.
2452 */
2453 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2454 dp->index);
2455 if (err)
2456 return err;
2457 }
2458 }
2459 }
2460
2461 return 0;
2462 }
2463
mv88e6xxx_port_bridge_join(struct dsa_switch * ds,int port,struct net_device * br)2464 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2465 struct net_device *br)
2466 {
2467 struct mv88e6xxx_chip *chip = ds->priv;
2468 int err;
2469
2470 mv88e6xxx_reg_lock(chip);
2471
2472 err = mv88e6xxx_bridge_map(chip, br);
2473 if (err)
2474 goto unlock;
2475
2476 err = mv88e6xxx_port_commit_pvid(chip, port);
2477 if (err)
2478 goto unlock;
2479
2480 unlock:
2481 mv88e6xxx_reg_unlock(chip);
2482
2483 return err;
2484 }
2485
mv88e6xxx_port_bridge_leave(struct dsa_switch * ds,int port,struct net_device * br)2486 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2487 struct net_device *br)
2488 {
2489 struct mv88e6xxx_chip *chip = ds->priv;
2490 int err;
2491
2492 mv88e6xxx_reg_lock(chip);
2493
2494 if (mv88e6xxx_bridge_map(chip, br) ||
2495 mv88e6xxx_port_vlan_map(chip, port))
2496 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
2497
2498 err = mv88e6xxx_port_commit_pvid(chip, port);
2499 if (err)
2500 dev_err(ds->dev,
2501 "port %d failed to restore standalone pvid: %pe\n",
2502 port, ERR_PTR(err));
2503
2504 mv88e6xxx_reg_unlock(chip);
2505 }
2506
mv88e6xxx_crosschip_bridge_join(struct dsa_switch * ds,int tree_index,int sw_index,int port,struct net_device * br)2507 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds,
2508 int tree_index, int sw_index,
2509 int port, struct net_device *br)
2510 {
2511 struct mv88e6xxx_chip *chip = ds->priv;
2512 int err;
2513
2514 if (tree_index != ds->dst->index)
2515 return 0;
2516
2517 mv88e6xxx_reg_lock(chip);
2518 err = mv88e6xxx_pvt_map(chip, sw_index, port);
2519 mv88e6xxx_reg_unlock(chip);
2520
2521 return err;
2522 }
2523
mv88e6xxx_crosschip_bridge_leave(struct dsa_switch * ds,int tree_index,int sw_index,int port,struct net_device * br)2524 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds,
2525 int tree_index, int sw_index,
2526 int port, struct net_device *br)
2527 {
2528 struct mv88e6xxx_chip *chip = ds->priv;
2529
2530 if (tree_index != ds->dst->index)
2531 return;
2532
2533 mv88e6xxx_reg_lock(chip);
2534 if (mv88e6xxx_pvt_map(chip, sw_index, port))
2535 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2536 mv88e6xxx_reg_unlock(chip);
2537 }
2538
2539 /* Treat the software bridge as a virtual single-port switch behind the
2540 * CPU and map in the PVT. First dst->last_switch elements are taken by
2541 * physical switches, so start from beyond that range.
2542 */
mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch * ds,int bridge_num)2543 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds,
2544 int bridge_num)
2545 {
2546 u8 dev = bridge_num + ds->dst->last_switch + 1;
2547 struct mv88e6xxx_chip *chip = ds->priv;
2548 int err;
2549
2550 mv88e6xxx_reg_lock(chip);
2551 err = mv88e6xxx_pvt_map(chip, dev, 0);
2552 mv88e6xxx_reg_unlock(chip);
2553
2554 return err;
2555 }
2556
mv88e6xxx_bridge_tx_fwd_offload(struct dsa_switch * ds,int port,struct net_device * br,int bridge_num)2557 static int mv88e6xxx_bridge_tx_fwd_offload(struct dsa_switch *ds, int port,
2558 struct net_device *br,
2559 int bridge_num)
2560 {
2561 return mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge_num);
2562 }
2563
mv88e6xxx_bridge_tx_fwd_unoffload(struct dsa_switch * ds,int port,struct net_device * br,int bridge_num)2564 static void mv88e6xxx_bridge_tx_fwd_unoffload(struct dsa_switch *ds, int port,
2565 struct net_device *br,
2566 int bridge_num)
2567 {
2568 int err;
2569
2570 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge_num);
2571 if (err) {
2572 dev_err(ds->dev, "failed to remap cross-chip Port VLAN: %pe\n",
2573 ERR_PTR(err));
2574 }
2575 }
2576
mv88e6xxx_software_reset(struct mv88e6xxx_chip * chip)2577 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2578 {
2579 if (chip->info->ops->reset)
2580 return chip->info->ops->reset(chip);
2581
2582 return 0;
2583 }
2584
mv88e6xxx_hardware_reset(struct mv88e6xxx_chip * chip)2585 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2586 {
2587 struct gpio_desc *gpiod = chip->reset;
2588
2589 /* If there is a GPIO connected to the reset pin, toggle it */
2590 if (gpiod) {
2591 /* If the switch has just been reset and not yet completed
2592 * loading EEPROM, the reset may interrupt the I2C transaction
2593 * mid-byte, causing the first EEPROM read after the reset
2594 * from the wrong location resulting in the switch booting
2595 * to wrong mode and inoperable.
2596 */
2597 if (chip->info->ops->get_eeprom)
2598 mv88e6xxx_g2_eeprom_wait(chip);
2599
2600 gpiod_set_value_cansleep(gpiod, 1);
2601 usleep_range(10000, 20000);
2602 gpiod_set_value_cansleep(gpiod, 0);
2603 usleep_range(10000, 20000);
2604
2605 if (chip->info->ops->get_eeprom)
2606 mv88e6xxx_g2_eeprom_wait(chip);
2607 }
2608 }
2609
mv88e6xxx_disable_ports(struct mv88e6xxx_chip * chip)2610 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
2611 {
2612 int i, err;
2613
2614 /* Set all ports to the Disabled state */
2615 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2616 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
2617 if (err)
2618 return err;
2619 }
2620
2621 /* Wait for transmit queues to drain,
2622 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2623 */
2624 usleep_range(2000, 4000);
2625
2626 return 0;
2627 }
2628
mv88e6xxx_switch_reset(struct mv88e6xxx_chip * chip)2629 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2630 {
2631 int err;
2632
2633 err = mv88e6xxx_disable_ports(chip);
2634 if (err)
2635 return err;
2636
2637 mv88e6xxx_hardware_reset(chip);
2638
2639 return mv88e6xxx_software_reset(chip);
2640 }
2641
mv88e6xxx_set_port_mode(struct mv88e6xxx_chip * chip,int port,enum mv88e6xxx_frame_mode frame,enum mv88e6xxx_egress_mode egress,u16 etype)2642 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
2643 enum mv88e6xxx_frame_mode frame,
2644 enum mv88e6xxx_egress_mode egress, u16 etype)
2645 {
2646 int err;
2647
2648 if (!chip->info->ops->port_set_frame_mode)
2649 return -EOPNOTSUPP;
2650
2651 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
2652 if (err)
2653 return err;
2654
2655 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
2656 if (err)
2657 return err;
2658
2659 if (chip->info->ops->port_set_ether_type)
2660 return chip->info->ops->port_set_ether_type(chip, port, etype);
2661
2662 return 0;
2663 }
2664
mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip * chip,int port)2665 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
2666 {
2667 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
2668 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2669 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2670 }
2671
mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip * chip,int port)2672 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
2673 {
2674 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
2675 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2676 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2677 }
2678
mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip * chip,int port)2679 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
2680 {
2681 return mv88e6xxx_set_port_mode(chip, port,
2682 MV88E6XXX_FRAME_MODE_ETHERTYPE,
2683 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
2684 ETH_P_EDSA);
2685 }
2686
mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip * chip,int port)2687 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
2688 {
2689 if (dsa_is_dsa_port(chip->ds, port))
2690 return mv88e6xxx_set_port_mode_dsa(chip, port);
2691
2692 if (dsa_is_user_port(chip->ds, port))
2693 return mv88e6xxx_set_port_mode_normal(chip, port);
2694
2695 /* Setup CPU port mode depending on its supported tag format */
2696 if (chip->tag_protocol == DSA_TAG_PROTO_DSA)
2697 return mv88e6xxx_set_port_mode_dsa(chip, port);
2698
2699 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA)
2700 return mv88e6xxx_set_port_mode_edsa(chip, port);
2701
2702 return -EINVAL;
2703 }
2704
mv88e6xxx_setup_message_port(struct mv88e6xxx_chip * chip,int port)2705 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2706 {
2707 bool message = dsa_is_dsa_port(chip->ds, port);
2708
2709 return mv88e6xxx_port_set_message_port(chip, port, message);
2710 }
2711
mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip * chip,int port)2712 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
2713 {
2714 int err;
2715
2716 if (chip->info->ops->port_set_ucast_flood) {
2717 err = chip->info->ops->port_set_ucast_flood(chip, port, true);
2718 if (err)
2719 return err;
2720 }
2721 if (chip->info->ops->port_set_mcast_flood) {
2722 err = chip->info->ops->port_set_mcast_flood(chip, port, true);
2723 if (err)
2724 return err;
2725 }
2726
2727 return 0;
2728 }
2729
mv88e6xxx_serdes_irq_thread_fn(int irq,void * dev_id)2730 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id)
2731 {
2732 struct mv88e6xxx_port *mvp = dev_id;
2733 struct mv88e6xxx_chip *chip = mvp->chip;
2734 irqreturn_t ret = IRQ_NONE;
2735 int port = mvp->port;
2736 int lane;
2737
2738 mv88e6xxx_reg_lock(chip);
2739 lane = mv88e6xxx_serdes_get_lane(chip, port);
2740 if (lane >= 0)
2741 ret = mv88e6xxx_serdes_irq_status(chip, port, lane);
2742 mv88e6xxx_reg_unlock(chip);
2743
2744 return ret;
2745 }
2746
mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip * chip,int port,int lane)2747 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port,
2748 int lane)
2749 {
2750 struct mv88e6xxx_port *dev_id = &chip->ports[port];
2751 unsigned int irq;
2752 int err;
2753
2754 /* Nothing to request if this SERDES port has no IRQ */
2755 irq = mv88e6xxx_serdes_irq_mapping(chip, port);
2756 if (!irq)
2757 return 0;
2758
2759 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name),
2760 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port);
2761
2762 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */
2763 mv88e6xxx_reg_unlock(chip);
2764 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn,
2765 IRQF_ONESHOT, dev_id->serdes_irq_name,
2766 dev_id);
2767 mv88e6xxx_reg_lock(chip);
2768 if (err)
2769 return err;
2770
2771 dev_id->serdes_irq = irq;
2772
2773 return mv88e6xxx_serdes_irq_enable(chip, port, lane);
2774 }
2775
mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip * chip,int port,int lane)2776 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port,
2777 int lane)
2778 {
2779 struct mv88e6xxx_port *dev_id = &chip->ports[port];
2780 unsigned int irq = dev_id->serdes_irq;
2781 int err;
2782
2783 /* Nothing to free if no IRQ has been requested */
2784 if (!irq)
2785 return 0;
2786
2787 err = mv88e6xxx_serdes_irq_disable(chip, port, lane);
2788
2789 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */
2790 mv88e6xxx_reg_unlock(chip);
2791 free_irq(irq, dev_id);
2792 mv88e6xxx_reg_lock(chip);
2793
2794 dev_id->serdes_irq = 0;
2795
2796 return err;
2797 }
2798
mv88e6xxx_serdes_power(struct mv88e6xxx_chip * chip,int port,bool on)2799 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
2800 bool on)
2801 {
2802 int lane;
2803 int err;
2804
2805 lane = mv88e6xxx_serdes_get_lane(chip, port);
2806 if (lane < 0)
2807 return 0;
2808
2809 if (on) {
2810 err = mv88e6xxx_serdes_power_up(chip, port, lane);
2811 if (err)
2812 return err;
2813
2814 err = mv88e6xxx_serdes_irq_request(chip, port, lane);
2815 } else {
2816 err = mv88e6xxx_serdes_irq_free(chip, port, lane);
2817 if (err)
2818 return err;
2819
2820 err = mv88e6xxx_serdes_power_down(chip, port, lane);
2821 }
2822
2823 return err;
2824 }
2825
mv88e6xxx_set_egress_port(struct mv88e6xxx_chip * chip,enum mv88e6xxx_egress_direction direction,int port)2826 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip,
2827 enum mv88e6xxx_egress_direction direction,
2828 int port)
2829 {
2830 int err;
2831
2832 if (!chip->info->ops->set_egress_port)
2833 return -EOPNOTSUPP;
2834
2835 err = chip->info->ops->set_egress_port(chip, direction, port);
2836 if (err)
2837 return err;
2838
2839 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS)
2840 chip->ingress_dest_port = port;
2841 else
2842 chip->egress_dest_port = port;
2843
2844 return 0;
2845 }
2846
mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip * chip,int port)2847 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
2848 {
2849 struct dsa_switch *ds = chip->ds;
2850 int upstream_port;
2851 int err;
2852
2853 upstream_port = dsa_upstream_port(ds, port);
2854 if (chip->info->ops->port_set_upstream_port) {
2855 err = chip->info->ops->port_set_upstream_port(chip, port,
2856 upstream_port);
2857 if (err)
2858 return err;
2859 }
2860
2861 if (port == upstream_port) {
2862 if (chip->info->ops->set_cpu_port) {
2863 err = chip->info->ops->set_cpu_port(chip,
2864 upstream_port);
2865 if (err)
2866 return err;
2867 }
2868
2869 err = mv88e6xxx_set_egress_port(chip,
2870 MV88E6XXX_EGRESS_DIR_INGRESS,
2871 upstream_port);
2872 if (err && err != -EOPNOTSUPP)
2873 return err;
2874
2875 err = mv88e6xxx_set_egress_port(chip,
2876 MV88E6XXX_EGRESS_DIR_EGRESS,
2877 upstream_port);
2878 if (err && err != -EOPNOTSUPP)
2879 return err;
2880 }
2881
2882 return 0;
2883 }
2884
mv88e6xxx_setup_port(struct mv88e6xxx_chip * chip,int port)2885 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2886 {
2887 struct dsa_switch *ds = chip->ds;
2888 int err;
2889 u16 reg;
2890
2891 chip->ports[port].chip = chip;
2892 chip->ports[port].port = port;
2893
2894 /* MAC Forcing register: don't force link, speed, duplex or flow control
2895 * state to any particular values on physical ports, but force the CPU
2896 * port and all DSA ports to their maximum bandwidth and full duplex.
2897 */
2898 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2899 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2900 SPEED_MAX, DUPLEX_FULL,
2901 PAUSE_OFF,
2902 PHY_INTERFACE_MODE_NA);
2903 else
2904 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2905 SPEED_UNFORCED, DUPLEX_UNFORCED,
2906 PAUSE_ON,
2907 PHY_INTERFACE_MODE_NA);
2908 if (err)
2909 return err;
2910
2911 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2912 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2913 * tunneling, determine priority by looking at 802.1p and IP
2914 * priority fields (IP prio has precedence), and set STP state
2915 * to Forwarding.
2916 *
2917 * If this is the CPU link, use DSA or EDSA tagging depending
2918 * on which tagging mode was configured.
2919 *
2920 * If this is a link to another switch, use DSA tagging mode.
2921 *
2922 * If this is the upstream port for this switch, enable
2923 * forwarding of unknown unicasts and multicasts.
2924 */
2925 reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
2926 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2927 /* Forward any IPv4 IGMP or IPv6 MLD frames received
2928 * by a USER port to the CPU port to allow snooping.
2929 */
2930 if (dsa_is_user_port(ds, port))
2931 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP;
2932
2933 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
2934 if (err)
2935 return err;
2936
2937 err = mv88e6xxx_setup_port_mode(chip, port);
2938 if (err)
2939 return err;
2940
2941 err = mv88e6xxx_setup_egress_floods(chip, port);
2942 if (err)
2943 return err;
2944
2945 /* Port Control 2: don't force a good FCS, set the MTU size to
2946 * 10222 bytes, disable 802.1q tags checking, don't discard tagged or
2947 * untagged frames on this port, do a destination address lookup on all
2948 * received packets as usual, disable ARP mirroring and don't send a
2949 * copy of all transmitted/received frames on this port to the CPU.
2950 */
2951 err = mv88e6xxx_port_set_map_da(chip, port);
2952 if (err)
2953 return err;
2954
2955 err = mv88e6xxx_setup_upstream_port(chip, port);
2956 if (err)
2957 return err;
2958
2959 err = mv88e6xxx_port_set_8021q_mode(chip, port,
2960 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
2961 if (err)
2962 return err;
2963
2964 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the
2965 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as
2966 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used
2967 * as the private PVID on ports under a VLAN-unaware bridge.
2968 * Shared (DSA and CPU) ports must also be members of it, to translate
2969 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of
2970 * relying on their port default FID.
2971 */
2972 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED,
2973 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED,
2974 false);
2975 if (err)
2976 return err;
2977
2978 if (chip->info->ops->port_set_jumbo_size) {
2979 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218);
2980 if (err)
2981 return err;
2982 }
2983
2984 /* Port Association Vector: disable automatic address learning
2985 * on all user ports since they start out in standalone
2986 * mode. When joining a bridge, learning will be configured to
2987 * match the bridge port settings. Enable learning on all
2988 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the
2989 * learning process.
2990 *
2991 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData,
2992 * and RefreshLocked. I.e. setup standard automatic learning.
2993 */
2994 if (dsa_is_user_port(ds, port))
2995 reg = 0;
2996 else
2997 reg = 1 << port;
2998
2999 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
3000 reg);
3001 if (err)
3002 return err;
3003
3004 /* Egress rate control 2: disable egress rate control. */
3005 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
3006 0x0000);
3007 if (err)
3008 return err;
3009
3010 if (chip->info->ops->port_pause_limit) {
3011 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
3012 if (err)
3013 return err;
3014 }
3015
3016 if (chip->info->ops->port_disable_learn_limit) {
3017 err = chip->info->ops->port_disable_learn_limit(chip, port);
3018 if (err)
3019 return err;
3020 }
3021
3022 if (chip->info->ops->port_disable_pri_override) {
3023 err = chip->info->ops->port_disable_pri_override(chip, port);
3024 if (err)
3025 return err;
3026 }
3027
3028 if (chip->info->ops->port_tag_remap) {
3029 err = chip->info->ops->port_tag_remap(chip, port);
3030 if (err)
3031 return err;
3032 }
3033
3034 if (chip->info->ops->port_egress_rate_limiting) {
3035 err = chip->info->ops->port_egress_rate_limiting(chip, port);
3036 if (err)
3037 return err;
3038 }
3039
3040 if (chip->info->ops->port_setup_message_port) {
3041 err = chip->info->ops->port_setup_message_port(chip, port);
3042 if (err)
3043 return err;
3044 }
3045
3046 /* Port based VLAN map: give each port the same default address
3047 * database, and allow bidirectional communication between the
3048 * CPU and DSA port(s), and the other ports.
3049 */
3050 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE);
3051 if (err)
3052 return err;
3053
3054 err = mv88e6xxx_port_vlan_map(chip, port);
3055 if (err)
3056 return err;
3057
3058 /* Default VLAN ID and priority: don't set a default VLAN
3059 * ID, and set the default packet priority to zero.
3060 */
3061 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
3062 }
3063
mv88e6xxx_get_max_mtu(struct dsa_switch * ds,int port)3064 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
3065 {
3066 struct mv88e6xxx_chip *chip = ds->priv;
3067
3068 if (chip->info->ops->port_set_jumbo_size)
3069 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3070 else if (chip->info->ops->set_max_frame_size)
3071 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3072 return ETH_DATA_LEN;
3073 }
3074
mv88e6xxx_change_mtu(struct dsa_switch * ds,int port,int new_mtu)3075 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
3076 {
3077 struct mv88e6xxx_chip *chip = ds->priv;
3078 int ret = 0;
3079
3080 /* For families where we don't know how to alter the MTU,
3081 * just accept any value up to ETH_DATA_LEN
3082 */
3083 if (!chip->info->ops->port_set_jumbo_size &&
3084 !chip->info->ops->set_max_frame_size) {
3085 if (new_mtu > ETH_DATA_LEN)
3086 return -EINVAL;
3087
3088 return 0;
3089 }
3090
3091 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
3092 new_mtu += EDSA_HLEN;
3093
3094 mv88e6xxx_reg_lock(chip);
3095 if (chip->info->ops->port_set_jumbo_size)
3096 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
3097 else if (chip->info->ops->set_max_frame_size)
3098 ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
3099 mv88e6xxx_reg_unlock(chip);
3100
3101 return ret;
3102 }
3103
mv88e6xxx_port_enable(struct dsa_switch * ds,int port,struct phy_device * phydev)3104 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
3105 struct phy_device *phydev)
3106 {
3107 struct mv88e6xxx_chip *chip = ds->priv;
3108 int err;
3109
3110 mv88e6xxx_reg_lock(chip);
3111 err = mv88e6xxx_serdes_power(chip, port, true);
3112 mv88e6xxx_reg_unlock(chip);
3113
3114 return err;
3115 }
3116
mv88e6xxx_port_disable(struct dsa_switch * ds,int port)3117 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port)
3118 {
3119 struct mv88e6xxx_chip *chip = ds->priv;
3120
3121 mv88e6xxx_reg_lock(chip);
3122 if (mv88e6xxx_serdes_power(chip, port, false))
3123 dev_err(chip->dev, "failed to power off SERDES\n");
3124 mv88e6xxx_reg_unlock(chip);
3125 }
3126
mv88e6xxx_set_ageing_time(struct dsa_switch * ds,unsigned int ageing_time)3127 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
3128 unsigned int ageing_time)
3129 {
3130 struct mv88e6xxx_chip *chip = ds->priv;
3131 int err;
3132
3133 mv88e6xxx_reg_lock(chip);
3134 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
3135 mv88e6xxx_reg_unlock(chip);
3136
3137 return err;
3138 }
3139
mv88e6xxx_stats_setup(struct mv88e6xxx_chip * chip)3140 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
3141 {
3142 int err;
3143
3144 /* Initialize the statistics unit */
3145 if (chip->info->ops->stats_set_histogram) {
3146 err = chip->info->ops->stats_set_histogram(chip);
3147 if (err)
3148 return err;
3149 }
3150
3151 return mv88e6xxx_g1_stats_clear(chip);
3152 }
3153
3154 /* Check if the errata has already been applied. */
mv88e6390_setup_errata_applied(struct mv88e6xxx_chip * chip)3155 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
3156 {
3157 int port;
3158 int err;
3159 u16 val;
3160
3161 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3162 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
3163 if (err) {
3164 dev_err(chip->dev,
3165 "Error reading hidden register: %d\n", err);
3166 return false;
3167 }
3168 if (val != 0x01c0)
3169 return false;
3170 }
3171
3172 return true;
3173 }
3174
3175 /* The 6390 copper ports have an errata which require poking magic
3176 * values into undocumented hidden registers and then performing a
3177 * software reset.
3178 */
mv88e6390_setup_errata(struct mv88e6xxx_chip * chip)3179 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
3180 {
3181 int port;
3182 int err;
3183
3184 if (mv88e6390_setup_errata_applied(chip))
3185 return 0;
3186
3187 /* Set the ports into blocking mode */
3188 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3189 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
3190 if (err)
3191 return err;
3192 }
3193
3194 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3195 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
3196 if (err)
3197 return err;
3198 }
3199
3200 return mv88e6xxx_software_reset(chip);
3201 }
3202
mv88e6xxx_teardown(struct dsa_switch * ds)3203 static void mv88e6xxx_teardown(struct dsa_switch *ds)
3204 {
3205 mv88e6xxx_teardown_devlink_params(ds);
3206 dsa_devlink_resources_unregister(ds);
3207 mv88e6xxx_teardown_devlink_regions_global(ds);
3208 }
3209
mv88e6xxx_setup(struct dsa_switch * ds)3210 static int mv88e6xxx_setup(struct dsa_switch *ds)
3211 {
3212 struct mv88e6xxx_chip *chip = ds->priv;
3213 u8 cmode;
3214 int err;
3215 int i;
3216
3217 chip->ds = ds;
3218 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
3219
3220 /* Since virtual bridges are mapped in the PVT, the number we support
3221 * depends on the physical switch topology. We need to let DSA figure
3222 * that out and therefore we cannot set this at dsa_register_switch()
3223 * time.
3224 */
3225 if (mv88e6xxx_has_pvt(chip))
3226 ds->num_fwd_offloading_bridges = MV88E6XXX_MAX_PVT_SWITCHES -
3227 ds->dst->last_switch - 1;
3228
3229 mv88e6xxx_reg_lock(chip);
3230
3231 if (chip->info->ops->setup_errata) {
3232 err = chip->info->ops->setup_errata(chip);
3233 if (err)
3234 goto unlock;
3235 }
3236
3237 /* Cache the cmode of each port. */
3238 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3239 if (chip->info->ops->port_get_cmode) {
3240 err = chip->info->ops->port_get_cmode(chip, i, &cmode);
3241 if (err)
3242 goto unlock;
3243
3244 chip->ports[i].cmode = cmode;
3245 }
3246 }
3247
3248 err = mv88e6xxx_vtu_setup(chip);
3249 if (err)
3250 goto unlock;
3251
3252 /* Setup Switch Port Registers */
3253 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3254 if (dsa_is_unused_port(ds, i))
3255 continue;
3256
3257 /* Prevent the use of an invalid port. */
3258 if (mv88e6xxx_is_invalid_port(chip, i)) {
3259 dev_err(chip->dev, "port %d is invalid\n", i);
3260 err = -EINVAL;
3261 goto unlock;
3262 }
3263
3264 err = mv88e6xxx_setup_port(chip, i);
3265 if (err)
3266 goto unlock;
3267 }
3268
3269 err = mv88e6xxx_irl_setup(chip);
3270 if (err)
3271 goto unlock;
3272
3273 err = mv88e6xxx_mac_setup(chip);
3274 if (err)
3275 goto unlock;
3276
3277 err = mv88e6xxx_phy_setup(chip);
3278 if (err)
3279 goto unlock;
3280
3281 err = mv88e6xxx_pvt_setup(chip);
3282 if (err)
3283 goto unlock;
3284
3285 err = mv88e6xxx_atu_setup(chip);
3286 if (err)
3287 goto unlock;
3288
3289 err = mv88e6xxx_broadcast_setup(chip, 0);
3290 if (err)
3291 goto unlock;
3292
3293 err = mv88e6xxx_pot_setup(chip);
3294 if (err)
3295 goto unlock;
3296
3297 err = mv88e6xxx_rmu_setup(chip);
3298 if (err)
3299 goto unlock;
3300
3301 err = mv88e6xxx_rsvd2cpu_setup(chip);
3302 if (err)
3303 goto unlock;
3304
3305 err = mv88e6xxx_trunk_setup(chip);
3306 if (err)
3307 goto unlock;
3308
3309 err = mv88e6xxx_devmap_setup(chip);
3310 if (err)
3311 goto unlock;
3312
3313 err = mv88e6xxx_pri_setup(chip);
3314 if (err)
3315 goto unlock;
3316
3317 /* Setup PTP Hardware Clock and timestamping */
3318 if (chip->info->ptp_support) {
3319 err = mv88e6xxx_ptp_setup(chip);
3320 if (err)
3321 goto unlock;
3322
3323 err = mv88e6xxx_hwtstamp_setup(chip);
3324 if (err)
3325 goto unlock;
3326 }
3327
3328 err = mv88e6xxx_stats_setup(chip);
3329 if (err)
3330 goto unlock;
3331
3332 unlock:
3333 mv88e6xxx_reg_unlock(chip);
3334
3335 if (err)
3336 return err;
3337
3338 /* Have to be called without holding the register lock, since
3339 * they take the devlink lock, and we later take the locks in
3340 * the reverse order when getting/setting parameters or
3341 * resource occupancy.
3342 */
3343 err = mv88e6xxx_setup_devlink_resources(ds);
3344 if (err)
3345 return err;
3346
3347 err = mv88e6xxx_setup_devlink_params(ds);
3348 if (err)
3349 goto out_resources;
3350
3351 err = mv88e6xxx_setup_devlink_regions_global(ds);
3352 if (err)
3353 goto out_params;
3354
3355 return 0;
3356
3357 out_params:
3358 mv88e6xxx_teardown_devlink_params(ds);
3359 out_resources:
3360 dsa_devlink_resources_unregister(ds);
3361
3362 return err;
3363 }
3364
mv88e6xxx_port_setup(struct dsa_switch * ds,int port)3365 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port)
3366 {
3367 return mv88e6xxx_setup_devlink_regions_port(ds, port);
3368 }
3369
mv88e6xxx_port_teardown(struct dsa_switch * ds,int port)3370 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port)
3371 {
3372 mv88e6xxx_teardown_devlink_regions_port(ds, port);
3373 }
3374
3375 /* prod_id for switch families which do not have a PHY model number */
3376 static const u16 family_prod_id_table[] = {
3377 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3378 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3379 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
3380 };
3381
mv88e6xxx_mdio_read(struct mii_bus * bus,int phy,int reg)3382 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
3383 {
3384 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3385 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3386 u16 prod_id;
3387 u16 val;
3388 int err;
3389
3390 if (!chip->info->ops->phy_read)
3391 return -EOPNOTSUPP;
3392
3393 mv88e6xxx_reg_lock(chip);
3394 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
3395 mv88e6xxx_reg_unlock(chip);
3396
3397 /* Some internal PHYs don't have a model number. */
3398 if (reg == MII_PHYSID2 && !(val & 0x3f0) &&
3399 chip->info->family < ARRAY_SIZE(family_prod_id_table)) {
3400 prod_id = family_prod_id_table[chip->info->family];
3401 if (prod_id)
3402 val |= prod_id >> 4;
3403 }
3404
3405 return err ? err : val;
3406 }
3407
mv88e6xxx_mdio_write(struct mii_bus * bus,int phy,int reg,u16 val)3408 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3409 {
3410 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3411 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3412 int err;
3413
3414 if (!chip->info->ops->phy_write)
3415 return -EOPNOTSUPP;
3416
3417 mv88e6xxx_reg_lock(chip);
3418 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
3419 mv88e6xxx_reg_unlock(chip);
3420
3421 return err;
3422 }
3423
mv88e6xxx_mdio_register(struct mv88e6xxx_chip * chip,struct device_node * np,bool external)3424 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3425 struct device_node *np,
3426 bool external)
3427 {
3428 static int index;
3429 struct mv88e6xxx_mdio_bus *mdio_bus;
3430 struct mii_bus *bus;
3431 int err;
3432
3433 if (external) {
3434 mv88e6xxx_reg_lock(chip);
3435 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
3436 mv88e6xxx_reg_unlock(chip);
3437
3438 if (err)
3439 return err;
3440 }
3441
3442 bus = mdiobus_alloc_size(sizeof(*mdio_bus));
3443 if (!bus)
3444 return -ENOMEM;
3445
3446 mdio_bus = bus->priv;
3447 mdio_bus->bus = bus;
3448 mdio_bus->chip = chip;
3449 INIT_LIST_HEAD(&mdio_bus->list);
3450 mdio_bus->external = external;
3451
3452 if (np) {
3453 bus->name = np->full_name;
3454 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
3455 } else {
3456 bus->name = "mv88e6xxx SMI";
3457 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3458 }
3459
3460 bus->read = mv88e6xxx_mdio_read;
3461 bus->write = mv88e6xxx_mdio_write;
3462 bus->parent = chip->dev;
3463
3464 if (!external) {
3465 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3466 if (err)
3467 goto out;
3468 }
3469
3470 err = of_mdiobus_register(bus, np);
3471 if (err) {
3472 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3473 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3474 goto out;
3475 }
3476
3477 if (external)
3478 list_add_tail(&mdio_bus->list, &chip->mdios);
3479 else
3480 list_add(&mdio_bus->list, &chip->mdios);
3481
3482 return 0;
3483
3484 out:
3485 mdiobus_free(bus);
3486 return err;
3487 }
3488
mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip * chip)3489 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3490
3491 {
3492 struct mv88e6xxx_mdio_bus *mdio_bus, *p;
3493 struct mii_bus *bus;
3494
3495 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) {
3496 bus = mdio_bus->bus;
3497
3498 if (!mdio_bus->external)
3499 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3500
3501 mdiobus_unregister(bus);
3502 mdiobus_free(bus);
3503 }
3504 }
3505
mv88e6xxx_mdios_register(struct mv88e6xxx_chip * chip,struct device_node * np)3506 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
3507 struct device_node *np)
3508 {
3509 struct device_node *child;
3510 int err;
3511
3512 /* Always register one mdio bus for the internal/default mdio
3513 * bus. This maybe represented in the device tree, but is
3514 * optional.
3515 */
3516 child = of_get_child_by_name(np, "mdio");
3517 err = mv88e6xxx_mdio_register(chip, child, false);
3518 of_node_put(child);
3519 if (err)
3520 return err;
3521
3522 /* Walk the device tree, and see if there are any other nodes
3523 * which say they are compatible with the external mdio
3524 * bus.
3525 */
3526 for_each_available_child_of_node(np, child) {
3527 if (of_device_is_compatible(
3528 child, "marvell,mv88e6xxx-mdio-external")) {
3529 err = mv88e6xxx_mdio_register(chip, child, true);
3530 if (err) {
3531 mv88e6xxx_mdios_unregister(chip);
3532 of_node_put(child);
3533 return err;
3534 }
3535 }
3536 }
3537
3538 return 0;
3539 }
3540
mv88e6xxx_get_eeprom_len(struct dsa_switch * ds)3541 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3542 {
3543 struct mv88e6xxx_chip *chip = ds->priv;
3544
3545 return chip->eeprom_len;
3546 }
3547
mv88e6xxx_get_eeprom(struct dsa_switch * ds,struct ethtool_eeprom * eeprom,u8 * data)3548 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3549 struct ethtool_eeprom *eeprom, u8 *data)
3550 {
3551 struct mv88e6xxx_chip *chip = ds->priv;
3552 int err;
3553
3554 if (!chip->info->ops->get_eeprom)
3555 return -EOPNOTSUPP;
3556
3557 mv88e6xxx_reg_lock(chip);
3558 err = chip->info->ops->get_eeprom(chip, eeprom, data);
3559 mv88e6xxx_reg_unlock(chip);
3560
3561 if (err)
3562 return err;
3563
3564 eeprom->magic = 0xc3ec4951;
3565
3566 return 0;
3567 }
3568
mv88e6xxx_set_eeprom(struct dsa_switch * ds,struct ethtool_eeprom * eeprom,u8 * data)3569 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3570 struct ethtool_eeprom *eeprom, u8 *data)
3571 {
3572 struct mv88e6xxx_chip *chip = ds->priv;
3573 int err;
3574
3575 if (!chip->info->ops->set_eeprom)
3576 return -EOPNOTSUPP;
3577
3578 if (eeprom->magic != 0xc3ec4951)
3579 return -EINVAL;
3580
3581 mv88e6xxx_reg_lock(chip);
3582 err = chip->info->ops->set_eeprom(chip, eeprom, data);
3583 mv88e6xxx_reg_unlock(chip);
3584
3585 return err;
3586 }
3587
3588 static const struct mv88e6xxx_ops mv88e6085_ops = {
3589 /* MV88E6XXX_FAMILY_6097 */
3590 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3591 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3592 .irl_init_all = mv88e6352_g2_irl_init_all,
3593 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3594 .phy_read = mv88e6185_phy_ppu_read,
3595 .phy_write = mv88e6185_phy_ppu_write,
3596 .port_set_link = mv88e6xxx_port_set_link,
3597 .port_sync_link = mv88e6xxx_port_sync_link,
3598 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3599 .port_tag_remap = mv88e6095_port_tag_remap,
3600 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3601 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3602 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3603 .port_set_ether_type = mv88e6351_port_set_ether_type,
3604 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3605 .port_pause_limit = mv88e6097_port_pause_limit,
3606 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3607 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3608 .port_get_cmode = mv88e6185_port_get_cmode,
3609 .port_setup_message_port = mv88e6xxx_setup_message_port,
3610 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3611 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3612 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3613 .stats_get_strings = mv88e6095_stats_get_strings,
3614 .stats_get_stats = mv88e6095_stats_get_stats,
3615 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3616 .set_egress_port = mv88e6095_g1_set_egress_port,
3617 .watchdog_ops = &mv88e6097_watchdog_ops,
3618 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3619 .pot_clear = mv88e6xxx_g2_pot_clear,
3620 .ppu_enable = mv88e6185_g1_ppu_enable,
3621 .ppu_disable = mv88e6185_g1_ppu_disable,
3622 .reset = mv88e6185_g1_reset,
3623 .rmu_disable = mv88e6085_g1_rmu_disable,
3624 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3625 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3626 .phylink_validate = mv88e6185_phylink_validate,
3627 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3628 };
3629
3630 static const struct mv88e6xxx_ops mv88e6095_ops = {
3631 /* MV88E6XXX_FAMILY_6095 */
3632 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3633 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3634 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3635 .phy_read = mv88e6185_phy_ppu_read,
3636 .phy_write = mv88e6185_phy_ppu_write,
3637 .port_set_link = mv88e6xxx_port_set_link,
3638 .port_sync_link = mv88e6185_port_sync_link,
3639 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3640 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3641 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
3642 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
3643 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3644 .port_get_cmode = mv88e6185_port_get_cmode,
3645 .port_setup_message_port = mv88e6xxx_setup_message_port,
3646 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3647 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3648 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3649 .stats_get_strings = mv88e6095_stats_get_strings,
3650 .stats_get_stats = mv88e6095_stats_get_stats,
3651 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3652 .serdes_power = mv88e6185_serdes_power,
3653 .serdes_get_lane = mv88e6185_serdes_get_lane,
3654 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
3655 .ppu_enable = mv88e6185_g1_ppu_enable,
3656 .ppu_disable = mv88e6185_g1_ppu_disable,
3657 .reset = mv88e6185_g1_reset,
3658 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3659 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3660 .phylink_validate = mv88e6185_phylink_validate,
3661 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3662 };
3663
3664 static const struct mv88e6xxx_ops mv88e6097_ops = {
3665 /* MV88E6XXX_FAMILY_6097 */
3666 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3667 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3668 .irl_init_all = mv88e6352_g2_irl_init_all,
3669 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3670 .phy_read = mv88e6xxx_g2_smi_phy_read,
3671 .phy_write = mv88e6xxx_g2_smi_phy_write,
3672 .port_set_link = mv88e6xxx_port_set_link,
3673 .port_sync_link = mv88e6185_port_sync_link,
3674 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3675 .port_tag_remap = mv88e6095_port_tag_remap,
3676 .port_set_policy = mv88e6352_port_set_policy,
3677 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3678 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3679 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3680 .port_set_ether_type = mv88e6351_port_set_ether_type,
3681 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3682 .port_pause_limit = mv88e6097_port_pause_limit,
3683 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3684 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3685 .port_get_cmode = mv88e6185_port_get_cmode,
3686 .port_setup_message_port = mv88e6xxx_setup_message_port,
3687 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3688 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3689 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3690 .stats_get_strings = mv88e6095_stats_get_strings,
3691 .stats_get_stats = mv88e6095_stats_get_stats,
3692 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3693 .set_egress_port = mv88e6095_g1_set_egress_port,
3694 .watchdog_ops = &mv88e6097_watchdog_ops,
3695 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3696 .serdes_power = mv88e6185_serdes_power,
3697 .serdes_get_lane = mv88e6185_serdes_get_lane,
3698 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
3699 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3700 .serdes_irq_enable = mv88e6097_serdes_irq_enable,
3701 .serdes_irq_status = mv88e6097_serdes_irq_status,
3702 .pot_clear = mv88e6xxx_g2_pot_clear,
3703 .reset = mv88e6352_g1_reset,
3704 .rmu_disable = mv88e6085_g1_rmu_disable,
3705 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3706 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3707 .phylink_validate = mv88e6185_phylink_validate,
3708 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3709 };
3710
3711 static const struct mv88e6xxx_ops mv88e6123_ops = {
3712 /* MV88E6XXX_FAMILY_6165 */
3713 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3714 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3715 .irl_init_all = mv88e6352_g2_irl_init_all,
3716 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3717 .phy_read = mv88e6xxx_g2_smi_phy_read,
3718 .phy_write = mv88e6xxx_g2_smi_phy_write,
3719 .port_set_link = mv88e6xxx_port_set_link,
3720 .port_sync_link = mv88e6xxx_port_sync_link,
3721 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3722 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3723 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3724 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3725 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3726 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3727 .port_get_cmode = mv88e6185_port_get_cmode,
3728 .port_setup_message_port = mv88e6xxx_setup_message_port,
3729 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3730 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3731 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3732 .stats_get_strings = mv88e6095_stats_get_strings,
3733 .stats_get_stats = mv88e6095_stats_get_stats,
3734 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3735 .set_egress_port = mv88e6095_g1_set_egress_port,
3736 .watchdog_ops = &mv88e6097_watchdog_ops,
3737 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3738 .pot_clear = mv88e6xxx_g2_pot_clear,
3739 .reset = mv88e6352_g1_reset,
3740 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3741 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3742 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3743 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3744 .phylink_validate = mv88e6185_phylink_validate,
3745 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3746 };
3747
3748 static const struct mv88e6xxx_ops mv88e6131_ops = {
3749 /* MV88E6XXX_FAMILY_6185 */
3750 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3751 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3752 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3753 .phy_read = mv88e6185_phy_ppu_read,
3754 .phy_write = mv88e6185_phy_ppu_write,
3755 .port_set_link = mv88e6xxx_port_set_link,
3756 .port_sync_link = mv88e6xxx_port_sync_link,
3757 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3758 .port_tag_remap = mv88e6095_port_tag_remap,
3759 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3760 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
3761 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
3762 .port_set_ether_type = mv88e6351_port_set_ether_type,
3763 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3764 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3765 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3766 .port_pause_limit = mv88e6097_port_pause_limit,
3767 .port_set_pause = mv88e6185_port_set_pause,
3768 .port_get_cmode = mv88e6185_port_get_cmode,
3769 .port_setup_message_port = mv88e6xxx_setup_message_port,
3770 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3771 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3772 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3773 .stats_get_strings = mv88e6095_stats_get_strings,
3774 .stats_get_stats = mv88e6095_stats_get_stats,
3775 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3776 .set_egress_port = mv88e6095_g1_set_egress_port,
3777 .watchdog_ops = &mv88e6097_watchdog_ops,
3778 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3779 .ppu_enable = mv88e6185_g1_ppu_enable,
3780 .set_cascade_port = mv88e6185_g1_set_cascade_port,
3781 .ppu_disable = mv88e6185_g1_ppu_disable,
3782 .reset = mv88e6185_g1_reset,
3783 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3784 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3785 .phylink_validate = mv88e6185_phylink_validate,
3786 };
3787
3788 static const struct mv88e6xxx_ops mv88e6141_ops = {
3789 /* MV88E6XXX_FAMILY_6341 */
3790 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3791 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3792 .irl_init_all = mv88e6352_g2_irl_init_all,
3793 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3794 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3795 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3796 .phy_read = mv88e6xxx_g2_smi_phy_read,
3797 .phy_write = mv88e6xxx_g2_smi_phy_write,
3798 .port_set_link = mv88e6xxx_port_set_link,
3799 .port_sync_link = mv88e6xxx_port_sync_link,
3800 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3801 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
3802 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
3803 .port_tag_remap = mv88e6095_port_tag_remap,
3804 .port_set_policy = mv88e6352_port_set_policy,
3805 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3806 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3807 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3808 .port_set_ether_type = mv88e6351_port_set_ether_type,
3809 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3810 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3811 .port_pause_limit = mv88e6097_port_pause_limit,
3812 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3813 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3814 .port_get_cmode = mv88e6352_port_get_cmode,
3815 .port_set_cmode = mv88e6341_port_set_cmode,
3816 .port_setup_message_port = mv88e6xxx_setup_message_port,
3817 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3818 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3819 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3820 .stats_get_strings = mv88e6320_stats_get_strings,
3821 .stats_get_stats = mv88e6390_stats_get_stats,
3822 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3823 .set_egress_port = mv88e6390_g1_set_egress_port,
3824 .watchdog_ops = &mv88e6390_watchdog_ops,
3825 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3826 .pot_clear = mv88e6xxx_g2_pot_clear,
3827 .reset = mv88e6352_g1_reset,
3828 .rmu_disable = mv88e6390_g1_rmu_disable,
3829 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3830 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3831 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3832 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3833 .serdes_power = mv88e6390_serdes_power,
3834 .serdes_get_lane = mv88e6341_serdes_get_lane,
3835 /* Check status register pause & lpa register */
3836 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3837 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3838 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3839 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
3840 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3841 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3842 .serdes_irq_status = mv88e6390_serdes_irq_status,
3843 .gpio_ops = &mv88e6352_gpio_ops,
3844 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
3845 .serdes_get_strings = mv88e6390_serdes_get_strings,
3846 .serdes_get_stats = mv88e6390_serdes_get_stats,
3847 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
3848 .serdes_get_regs = mv88e6390_serdes_get_regs,
3849 .phylink_validate = mv88e6341_phylink_validate,
3850 };
3851
3852 static const struct mv88e6xxx_ops mv88e6161_ops = {
3853 /* MV88E6XXX_FAMILY_6165 */
3854 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3855 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3856 .irl_init_all = mv88e6352_g2_irl_init_all,
3857 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3858 .phy_read = mv88e6xxx_g2_smi_phy_read,
3859 .phy_write = mv88e6xxx_g2_smi_phy_write,
3860 .port_set_link = mv88e6xxx_port_set_link,
3861 .port_sync_link = mv88e6xxx_port_sync_link,
3862 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3863 .port_tag_remap = mv88e6095_port_tag_remap,
3864 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3865 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3866 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3867 .port_set_ether_type = mv88e6351_port_set_ether_type,
3868 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3869 .port_pause_limit = mv88e6097_port_pause_limit,
3870 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3871 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3872 .port_get_cmode = mv88e6185_port_get_cmode,
3873 .port_setup_message_port = mv88e6xxx_setup_message_port,
3874 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3875 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3876 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3877 .stats_get_strings = mv88e6095_stats_get_strings,
3878 .stats_get_stats = mv88e6095_stats_get_stats,
3879 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3880 .set_egress_port = mv88e6095_g1_set_egress_port,
3881 .watchdog_ops = &mv88e6097_watchdog_ops,
3882 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3883 .pot_clear = mv88e6xxx_g2_pot_clear,
3884 .reset = mv88e6352_g1_reset,
3885 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3886 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3887 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3888 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3889 .avb_ops = &mv88e6165_avb_ops,
3890 .ptp_ops = &mv88e6165_ptp_ops,
3891 .phylink_validate = mv88e6185_phylink_validate,
3892 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3893 };
3894
3895 static const struct mv88e6xxx_ops mv88e6165_ops = {
3896 /* MV88E6XXX_FAMILY_6165 */
3897 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3898 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3899 .irl_init_all = mv88e6352_g2_irl_init_all,
3900 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3901 .phy_read = mv88e6165_phy_read,
3902 .phy_write = mv88e6165_phy_write,
3903 .port_set_link = mv88e6xxx_port_set_link,
3904 .port_sync_link = mv88e6xxx_port_sync_link,
3905 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3906 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3907 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3908 .port_get_cmode = mv88e6185_port_get_cmode,
3909 .port_setup_message_port = mv88e6xxx_setup_message_port,
3910 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3911 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3912 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3913 .stats_get_strings = mv88e6095_stats_get_strings,
3914 .stats_get_stats = mv88e6095_stats_get_stats,
3915 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3916 .set_egress_port = mv88e6095_g1_set_egress_port,
3917 .watchdog_ops = &mv88e6097_watchdog_ops,
3918 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3919 .pot_clear = mv88e6xxx_g2_pot_clear,
3920 .reset = mv88e6352_g1_reset,
3921 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3922 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3923 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3924 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3925 .avb_ops = &mv88e6165_avb_ops,
3926 .ptp_ops = &mv88e6165_ptp_ops,
3927 .phylink_validate = mv88e6185_phylink_validate,
3928 };
3929
3930 static const struct mv88e6xxx_ops mv88e6171_ops = {
3931 /* MV88E6XXX_FAMILY_6351 */
3932 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3933 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3934 .irl_init_all = mv88e6352_g2_irl_init_all,
3935 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3936 .phy_read = mv88e6xxx_g2_smi_phy_read,
3937 .phy_write = mv88e6xxx_g2_smi_phy_write,
3938 .port_set_link = mv88e6xxx_port_set_link,
3939 .port_sync_link = mv88e6xxx_port_sync_link,
3940 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3941 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3942 .port_tag_remap = mv88e6095_port_tag_remap,
3943 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3944 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3945 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3946 .port_set_ether_type = mv88e6351_port_set_ether_type,
3947 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3948 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3949 .port_pause_limit = mv88e6097_port_pause_limit,
3950 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3951 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3952 .port_get_cmode = mv88e6352_port_get_cmode,
3953 .port_setup_message_port = mv88e6xxx_setup_message_port,
3954 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3955 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3956 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3957 .stats_get_strings = mv88e6095_stats_get_strings,
3958 .stats_get_stats = mv88e6095_stats_get_stats,
3959 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3960 .set_egress_port = mv88e6095_g1_set_egress_port,
3961 .watchdog_ops = &mv88e6097_watchdog_ops,
3962 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3963 .pot_clear = mv88e6xxx_g2_pot_clear,
3964 .reset = mv88e6352_g1_reset,
3965 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3966 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3967 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3968 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3969 .phylink_validate = mv88e6185_phylink_validate,
3970 };
3971
3972 static const struct mv88e6xxx_ops mv88e6172_ops = {
3973 /* MV88E6XXX_FAMILY_6352 */
3974 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3975 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3976 .irl_init_all = mv88e6352_g2_irl_init_all,
3977 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3978 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3979 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3980 .phy_read = mv88e6xxx_g2_smi_phy_read,
3981 .phy_write = mv88e6xxx_g2_smi_phy_write,
3982 .port_set_link = mv88e6xxx_port_set_link,
3983 .port_sync_link = mv88e6xxx_port_sync_link,
3984 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3985 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
3986 .port_tag_remap = mv88e6095_port_tag_remap,
3987 .port_set_policy = mv88e6352_port_set_policy,
3988 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3989 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3990 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3991 .port_set_ether_type = mv88e6351_port_set_ether_type,
3992 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3993 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3994 .port_pause_limit = mv88e6097_port_pause_limit,
3995 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3996 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3997 .port_get_cmode = mv88e6352_port_get_cmode,
3998 .port_setup_message_port = mv88e6xxx_setup_message_port,
3999 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4000 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4001 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4002 .stats_get_strings = mv88e6095_stats_get_strings,
4003 .stats_get_stats = mv88e6095_stats_get_stats,
4004 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4005 .set_egress_port = mv88e6095_g1_set_egress_port,
4006 .watchdog_ops = &mv88e6097_watchdog_ops,
4007 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4008 .pot_clear = mv88e6xxx_g2_pot_clear,
4009 .reset = mv88e6352_g1_reset,
4010 .rmu_disable = mv88e6352_g1_rmu_disable,
4011 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4012 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4013 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4014 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4015 .serdes_get_lane = mv88e6352_serdes_get_lane,
4016 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4017 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4018 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4019 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
4020 .serdes_power = mv88e6352_serdes_power,
4021 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4022 .serdes_get_regs = mv88e6352_serdes_get_regs,
4023 .gpio_ops = &mv88e6352_gpio_ops,
4024 .phylink_validate = mv88e6352_phylink_validate,
4025 };
4026
4027 static const struct mv88e6xxx_ops mv88e6175_ops = {
4028 /* MV88E6XXX_FAMILY_6351 */
4029 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4030 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4031 .irl_init_all = mv88e6352_g2_irl_init_all,
4032 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4033 .phy_read = mv88e6xxx_g2_smi_phy_read,
4034 .phy_write = mv88e6xxx_g2_smi_phy_write,
4035 .port_set_link = mv88e6xxx_port_set_link,
4036 .port_sync_link = mv88e6xxx_port_sync_link,
4037 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4038 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4039 .port_tag_remap = mv88e6095_port_tag_remap,
4040 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4041 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4042 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4043 .port_set_ether_type = mv88e6351_port_set_ether_type,
4044 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4045 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4046 .port_pause_limit = mv88e6097_port_pause_limit,
4047 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4048 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4049 .port_get_cmode = mv88e6352_port_get_cmode,
4050 .port_setup_message_port = mv88e6xxx_setup_message_port,
4051 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4052 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4053 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4054 .stats_get_strings = mv88e6095_stats_get_strings,
4055 .stats_get_stats = mv88e6095_stats_get_stats,
4056 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4057 .set_egress_port = mv88e6095_g1_set_egress_port,
4058 .watchdog_ops = &mv88e6097_watchdog_ops,
4059 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4060 .pot_clear = mv88e6xxx_g2_pot_clear,
4061 .reset = mv88e6352_g1_reset,
4062 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4063 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4064 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4065 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4066 .phylink_validate = mv88e6185_phylink_validate,
4067 };
4068
4069 static const struct mv88e6xxx_ops mv88e6176_ops = {
4070 /* MV88E6XXX_FAMILY_6352 */
4071 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4072 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4073 .irl_init_all = mv88e6352_g2_irl_init_all,
4074 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4075 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4076 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4077 .phy_read = mv88e6xxx_g2_smi_phy_read,
4078 .phy_write = mv88e6xxx_g2_smi_phy_write,
4079 .port_set_link = mv88e6xxx_port_set_link,
4080 .port_sync_link = mv88e6xxx_port_sync_link,
4081 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4082 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4083 .port_tag_remap = mv88e6095_port_tag_remap,
4084 .port_set_policy = mv88e6352_port_set_policy,
4085 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4086 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4087 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4088 .port_set_ether_type = mv88e6351_port_set_ether_type,
4089 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4090 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4091 .port_pause_limit = mv88e6097_port_pause_limit,
4092 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4093 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4094 .port_get_cmode = mv88e6352_port_get_cmode,
4095 .port_setup_message_port = mv88e6xxx_setup_message_port,
4096 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4097 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4098 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4099 .stats_get_strings = mv88e6095_stats_get_strings,
4100 .stats_get_stats = mv88e6095_stats_get_stats,
4101 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4102 .set_egress_port = mv88e6095_g1_set_egress_port,
4103 .watchdog_ops = &mv88e6097_watchdog_ops,
4104 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4105 .pot_clear = mv88e6xxx_g2_pot_clear,
4106 .reset = mv88e6352_g1_reset,
4107 .rmu_disable = mv88e6352_g1_rmu_disable,
4108 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4109 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4110 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4111 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4112 .serdes_get_lane = mv88e6352_serdes_get_lane,
4113 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4114 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4115 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4116 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
4117 .serdes_power = mv88e6352_serdes_power,
4118 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4119 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
4120 .serdes_irq_status = mv88e6352_serdes_irq_status,
4121 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4122 .serdes_get_regs = mv88e6352_serdes_get_regs,
4123 .gpio_ops = &mv88e6352_gpio_ops,
4124 .phylink_validate = mv88e6352_phylink_validate,
4125 };
4126
4127 static const struct mv88e6xxx_ops mv88e6185_ops = {
4128 /* MV88E6XXX_FAMILY_6185 */
4129 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4130 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4131 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4132 .phy_read = mv88e6185_phy_ppu_read,
4133 .phy_write = mv88e6185_phy_ppu_write,
4134 .port_set_link = mv88e6xxx_port_set_link,
4135 .port_sync_link = mv88e6185_port_sync_link,
4136 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4137 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4138 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4139 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4140 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4141 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4142 .port_set_pause = mv88e6185_port_set_pause,
4143 .port_get_cmode = mv88e6185_port_get_cmode,
4144 .port_setup_message_port = mv88e6xxx_setup_message_port,
4145 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4146 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4147 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4148 .stats_get_strings = mv88e6095_stats_get_strings,
4149 .stats_get_stats = mv88e6095_stats_get_stats,
4150 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4151 .set_egress_port = mv88e6095_g1_set_egress_port,
4152 .watchdog_ops = &mv88e6097_watchdog_ops,
4153 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4154 .serdes_power = mv88e6185_serdes_power,
4155 .serdes_get_lane = mv88e6185_serdes_get_lane,
4156 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
4157 .set_cascade_port = mv88e6185_g1_set_cascade_port,
4158 .ppu_enable = mv88e6185_g1_ppu_enable,
4159 .ppu_disable = mv88e6185_g1_ppu_disable,
4160 .reset = mv88e6185_g1_reset,
4161 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4162 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4163 .phylink_validate = mv88e6185_phylink_validate,
4164 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4165 };
4166
4167 static const struct mv88e6xxx_ops mv88e6190_ops = {
4168 /* MV88E6XXX_FAMILY_6390 */
4169 .setup_errata = mv88e6390_setup_errata,
4170 .irl_init_all = mv88e6390_g2_irl_init_all,
4171 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4172 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4173 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4174 .phy_read = mv88e6xxx_g2_smi_phy_read,
4175 .phy_write = mv88e6xxx_g2_smi_phy_write,
4176 .port_set_link = mv88e6xxx_port_set_link,
4177 .port_sync_link = mv88e6xxx_port_sync_link,
4178 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4179 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4180 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4181 .port_tag_remap = mv88e6390_port_tag_remap,
4182 .port_set_policy = mv88e6352_port_set_policy,
4183 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4184 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4185 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4186 .port_set_ether_type = mv88e6351_port_set_ether_type,
4187 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4188 .port_pause_limit = mv88e6390_port_pause_limit,
4189 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4190 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4191 .port_get_cmode = mv88e6352_port_get_cmode,
4192 .port_set_cmode = mv88e6390_port_set_cmode,
4193 .port_setup_message_port = mv88e6xxx_setup_message_port,
4194 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4195 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4196 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4197 .stats_get_strings = mv88e6320_stats_get_strings,
4198 .stats_get_stats = mv88e6390_stats_get_stats,
4199 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4200 .set_egress_port = mv88e6390_g1_set_egress_port,
4201 .watchdog_ops = &mv88e6390_watchdog_ops,
4202 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4203 .pot_clear = mv88e6xxx_g2_pot_clear,
4204 .reset = mv88e6352_g1_reset,
4205 .rmu_disable = mv88e6390_g1_rmu_disable,
4206 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4207 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4208 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4209 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4210 .serdes_power = mv88e6390_serdes_power,
4211 .serdes_get_lane = mv88e6390_serdes_get_lane,
4212 /* Check status register pause & lpa register */
4213 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4214 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4215 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4216 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4217 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4218 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4219 .serdes_irq_status = mv88e6390_serdes_irq_status,
4220 .serdes_get_strings = mv88e6390_serdes_get_strings,
4221 .serdes_get_stats = mv88e6390_serdes_get_stats,
4222 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4223 .serdes_get_regs = mv88e6390_serdes_get_regs,
4224 .gpio_ops = &mv88e6352_gpio_ops,
4225 .phylink_validate = mv88e6390_phylink_validate,
4226 };
4227
4228 static const struct mv88e6xxx_ops mv88e6190x_ops = {
4229 /* MV88E6XXX_FAMILY_6390 */
4230 .setup_errata = mv88e6390_setup_errata,
4231 .irl_init_all = mv88e6390_g2_irl_init_all,
4232 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4233 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4234 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4235 .phy_read = mv88e6xxx_g2_smi_phy_read,
4236 .phy_write = mv88e6xxx_g2_smi_phy_write,
4237 .port_set_link = mv88e6xxx_port_set_link,
4238 .port_sync_link = mv88e6xxx_port_sync_link,
4239 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4240 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
4241 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4242 .port_tag_remap = mv88e6390_port_tag_remap,
4243 .port_set_policy = mv88e6352_port_set_policy,
4244 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4245 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4246 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4247 .port_set_ether_type = mv88e6351_port_set_ether_type,
4248 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4249 .port_pause_limit = mv88e6390_port_pause_limit,
4250 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4251 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4252 .port_get_cmode = mv88e6352_port_get_cmode,
4253 .port_set_cmode = mv88e6390x_port_set_cmode,
4254 .port_setup_message_port = mv88e6xxx_setup_message_port,
4255 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4256 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4257 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4258 .stats_get_strings = mv88e6320_stats_get_strings,
4259 .stats_get_stats = mv88e6390_stats_get_stats,
4260 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4261 .set_egress_port = mv88e6390_g1_set_egress_port,
4262 .watchdog_ops = &mv88e6390_watchdog_ops,
4263 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4264 .pot_clear = mv88e6xxx_g2_pot_clear,
4265 .reset = mv88e6352_g1_reset,
4266 .rmu_disable = mv88e6390_g1_rmu_disable,
4267 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4268 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4269 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4270 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4271 .serdes_power = mv88e6390_serdes_power,
4272 .serdes_get_lane = mv88e6390x_serdes_get_lane,
4273 /* Check status register pause & lpa register */
4274 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4275 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4276 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4277 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4278 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4279 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4280 .serdes_irq_status = mv88e6390_serdes_irq_status,
4281 .serdes_get_strings = mv88e6390_serdes_get_strings,
4282 .serdes_get_stats = mv88e6390_serdes_get_stats,
4283 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4284 .serdes_get_regs = mv88e6390_serdes_get_regs,
4285 .gpio_ops = &mv88e6352_gpio_ops,
4286 .phylink_validate = mv88e6390x_phylink_validate,
4287 };
4288
4289 static const struct mv88e6xxx_ops mv88e6191_ops = {
4290 /* MV88E6XXX_FAMILY_6390 */
4291 .setup_errata = mv88e6390_setup_errata,
4292 .irl_init_all = mv88e6390_g2_irl_init_all,
4293 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4294 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4295 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4296 .phy_read = mv88e6xxx_g2_smi_phy_read,
4297 .phy_write = mv88e6xxx_g2_smi_phy_write,
4298 .port_set_link = mv88e6xxx_port_set_link,
4299 .port_sync_link = mv88e6xxx_port_sync_link,
4300 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4301 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4302 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4303 .port_tag_remap = mv88e6390_port_tag_remap,
4304 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4305 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4306 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4307 .port_set_ether_type = mv88e6351_port_set_ether_type,
4308 .port_pause_limit = mv88e6390_port_pause_limit,
4309 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4310 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4311 .port_get_cmode = mv88e6352_port_get_cmode,
4312 .port_set_cmode = mv88e6390_port_set_cmode,
4313 .port_setup_message_port = mv88e6xxx_setup_message_port,
4314 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4315 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4316 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4317 .stats_get_strings = mv88e6320_stats_get_strings,
4318 .stats_get_stats = mv88e6390_stats_get_stats,
4319 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4320 .set_egress_port = mv88e6390_g1_set_egress_port,
4321 .watchdog_ops = &mv88e6390_watchdog_ops,
4322 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4323 .pot_clear = mv88e6xxx_g2_pot_clear,
4324 .reset = mv88e6352_g1_reset,
4325 .rmu_disable = mv88e6390_g1_rmu_disable,
4326 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4327 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4328 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4329 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4330 .serdes_power = mv88e6390_serdes_power,
4331 .serdes_get_lane = mv88e6390_serdes_get_lane,
4332 /* Check status register pause & lpa register */
4333 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4334 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4335 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4336 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4337 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4338 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4339 .serdes_irq_status = mv88e6390_serdes_irq_status,
4340 .serdes_get_strings = mv88e6390_serdes_get_strings,
4341 .serdes_get_stats = mv88e6390_serdes_get_stats,
4342 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4343 .serdes_get_regs = mv88e6390_serdes_get_regs,
4344 .avb_ops = &mv88e6390_avb_ops,
4345 .ptp_ops = &mv88e6352_ptp_ops,
4346 .phylink_validate = mv88e6390_phylink_validate,
4347 };
4348
4349 static const struct mv88e6xxx_ops mv88e6240_ops = {
4350 /* MV88E6XXX_FAMILY_6352 */
4351 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4352 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4353 .irl_init_all = mv88e6352_g2_irl_init_all,
4354 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4355 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4356 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4357 .phy_read = mv88e6xxx_g2_smi_phy_read,
4358 .phy_write = mv88e6xxx_g2_smi_phy_write,
4359 .port_set_link = mv88e6xxx_port_set_link,
4360 .port_sync_link = mv88e6xxx_port_sync_link,
4361 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4362 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4363 .port_tag_remap = mv88e6095_port_tag_remap,
4364 .port_set_policy = mv88e6352_port_set_policy,
4365 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4366 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4367 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4368 .port_set_ether_type = mv88e6351_port_set_ether_type,
4369 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4370 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4371 .port_pause_limit = mv88e6097_port_pause_limit,
4372 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4373 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4374 .port_get_cmode = mv88e6352_port_get_cmode,
4375 .port_setup_message_port = mv88e6xxx_setup_message_port,
4376 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4377 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4378 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4379 .stats_get_strings = mv88e6095_stats_get_strings,
4380 .stats_get_stats = mv88e6095_stats_get_stats,
4381 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4382 .set_egress_port = mv88e6095_g1_set_egress_port,
4383 .watchdog_ops = &mv88e6097_watchdog_ops,
4384 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4385 .pot_clear = mv88e6xxx_g2_pot_clear,
4386 .reset = mv88e6352_g1_reset,
4387 .rmu_disable = mv88e6352_g1_rmu_disable,
4388 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4389 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4390 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4391 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4392 .serdes_get_lane = mv88e6352_serdes_get_lane,
4393 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4394 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4395 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4396 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
4397 .serdes_power = mv88e6352_serdes_power,
4398 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4399 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
4400 .serdes_irq_status = mv88e6352_serdes_irq_status,
4401 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4402 .serdes_get_regs = mv88e6352_serdes_get_regs,
4403 .gpio_ops = &mv88e6352_gpio_ops,
4404 .avb_ops = &mv88e6352_avb_ops,
4405 .ptp_ops = &mv88e6352_ptp_ops,
4406 .phylink_validate = mv88e6352_phylink_validate,
4407 };
4408
4409 static const struct mv88e6xxx_ops mv88e6250_ops = {
4410 /* MV88E6XXX_FAMILY_6250 */
4411 .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
4412 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4413 .irl_init_all = mv88e6352_g2_irl_init_all,
4414 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4415 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4416 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4417 .phy_read = mv88e6xxx_g2_smi_phy_read,
4418 .phy_write = mv88e6xxx_g2_smi_phy_write,
4419 .port_set_link = mv88e6xxx_port_set_link,
4420 .port_sync_link = mv88e6xxx_port_sync_link,
4421 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4422 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
4423 .port_tag_remap = mv88e6095_port_tag_remap,
4424 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4425 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4426 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4427 .port_set_ether_type = mv88e6351_port_set_ether_type,
4428 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4429 .port_pause_limit = mv88e6097_port_pause_limit,
4430 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4431 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4432 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4433 .stats_get_sset_count = mv88e6250_stats_get_sset_count,
4434 .stats_get_strings = mv88e6250_stats_get_strings,
4435 .stats_get_stats = mv88e6250_stats_get_stats,
4436 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4437 .set_egress_port = mv88e6095_g1_set_egress_port,
4438 .watchdog_ops = &mv88e6250_watchdog_ops,
4439 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4440 .pot_clear = mv88e6xxx_g2_pot_clear,
4441 .reset = mv88e6250_g1_reset,
4442 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4443 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4444 .avb_ops = &mv88e6352_avb_ops,
4445 .ptp_ops = &mv88e6250_ptp_ops,
4446 .phylink_validate = mv88e6065_phylink_validate,
4447 };
4448
4449 static const struct mv88e6xxx_ops mv88e6290_ops = {
4450 /* MV88E6XXX_FAMILY_6390 */
4451 .setup_errata = mv88e6390_setup_errata,
4452 .irl_init_all = mv88e6390_g2_irl_init_all,
4453 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4454 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4455 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4456 .phy_read = mv88e6xxx_g2_smi_phy_read,
4457 .phy_write = mv88e6xxx_g2_smi_phy_write,
4458 .port_set_link = mv88e6xxx_port_set_link,
4459 .port_sync_link = mv88e6xxx_port_sync_link,
4460 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4461 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4462 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4463 .port_tag_remap = mv88e6390_port_tag_remap,
4464 .port_set_policy = mv88e6352_port_set_policy,
4465 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4466 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4467 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4468 .port_set_ether_type = mv88e6351_port_set_ether_type,
4469 .port_pause_limit = mv88e6390_port_pause_limit,
4470 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4471 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4472 .port_get_cmode = mv88e6352_port_get_cmode,
4473 .port_set_cmode = mv88e6390_port_set_cmode,
4474 .port_setup_message_port = mv88e6xxx_setup_message_port,
4475 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4476 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4477 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4478 .stats_get_strings = mv88e6320_stats_get_strings,
4479 .stats_get_stats = mv88e6390_stats_get_stats,
4480 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4481 .set_egress_port = mv88e6390_g1_set_egress_port,
4482 .watchdog_ops = &mv88e6390_watchdog_ops,
4483 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4484 .pot_clear = mv88e6xxx_g2_pot_clear,
4485 .reset = mv88e6352_g1_reset,
4486 .rmu_disable = mv88e6390_g1_rmu_disable,
4487 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4488 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4489 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4490 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4491 .serdes_power = mv88e6390_serdes_power,
4492 .serdes_get_lane = mv88e6390_serdes_get_lane,
4493 /* Check status register pause & lpa register */
4494 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4495 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4496 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4497 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4498 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4499 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4500 .serdes_irq_status = mv88e6390_serdes_irq_status,
4501 .serdes_get_strings = mv88e6390_serdes_get_strings,
4502 .serdes_get_stats = mv88e6390_serdes_get_stats,
4503 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4504 .serdes_get_regs = mv88e6390_serdes_get_regs,
4505 .gpio_ops = &mv88e6352_gpio_ops,
4506 .avb_ops = &mv88e6390_avb_ops,
4507 .ptp_ops = &mv88e6352_ptp_ops,
4508 .phylink_validate = mv88e6390_phylink_validate,
4509 };
4510
4511 static const struct mv88e6xxx_ops mv88e6320_ops = {
4512 /* MV88E6XXX_FAMILY_6320 */
4513 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4514 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4515 .irl_init_all = mv88e6352_g2_irl_init_all,
4516 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4517 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4518 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4519 .phy_read = mv88e6xxx_g2_smi_phy_read,
4520 .phy_write = mv88e6xxx_g2_smi_phy_write,
4521 .port_set_link = mv88e6xxx_port_set_link,
4522 .port_sync_link = mv88e6xxx_port_sync_link,
4523 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4524 .port_tag_remap = mv88e6095_port_tag_remap,
4525 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4526 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4527 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4528 .port_set_ether_type = mv88e6351_port_set_ether_type,
4529 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4530 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4531 .port_pause_limit = mv88e6097_port_pause_limit,
4532 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4533 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4534 .port_get_cmode = mv88e6352_port_get_cmode,
4535 .port_setup_message_port = mv88e6xxx_setup_message_port,
4536 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4537 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4538 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4539 .stats_get_strings = mv88e6320_stats_get_strings,
4540 .stats_get_stats = mv88e6320_stats_get_stats,
4541 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4542 .set_egress_port = mv88e6095_g1_set_egress_port,
4543 .watchdog_ops = &mv88e6390_watchdog_ops,
4544 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4545 .pot_clear = mv88e6xxx_g2_pot_clear,
4546 .reset = mv88e6352_g1_reset,
4547 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4548 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4549 .gpio_ops = &mv88e6352_gpio_ops,
4550 .avb_ops = &mv88e6352_avb_ops,
4551 .ptp_ops = &mv88e6352_ptp_ops,
4552 .phylink_validate = mv88e6185_phylink_validate,
4553 };
4554
4555 static const struct mv88e6xxx_ops mv88e6321_ops = {
4556 /* MV88E6XXX_FAMILY_6320 */
4557 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4558 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4559 .irl_init_all = mv88e6352_g2_irl_init_all,
4560 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4561 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4562 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4563 .phy_read = mv88e6xxx_g2_smi_phy_read,
4564 .phy_write = mv88e6xxx_g2_smi_phy_write,
4565 .port_set_link = mv88e6xxx_port_set_link,
4566 .port_sync_link = mv88e6xxx_port_sync_link,
4567 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4568 .port_tag_remap = mv88e6095_port_tag_remap,
4569 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4570 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4571 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4572 .port_set_ether_type = mv88e6351_port_set_ether_type,
4573 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4574 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4575 .port_pause_limit = mv88e6097_port_pause_limit,
4576 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4577 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4578 .port_get_cmode = mv88e6352_port_get_cmode,
4579 .port_setup_message_port = mv88e6xxx_setup_message_port,
4580 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4581 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4582 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4583 .stats_get_strings = mv88e6320_stats_get_strings,
4584 .stats_get_stats = mv88e6320_stats_get_stats,
4585 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4586 .set_egress_port = mv88e6095_g1_set_egress_port,
4587 .watchdog_ops = &mv88e6390_watchdog_ops,
4588 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4589 .reset = mv88e6352_g1_reset,
4590 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4591 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4592 .gpio_ops = &mv88e6352_gpio_ops,
4593 .avb_ops = &mv88e6352_avb_ops,
4594 .ptp_ops = &mv88e6352_ptp_ops,
4595 .phylink_validate = mv88e6185_phylink_validate,
4596 };
4597
4598 static const struct mv88e6xxx_ops mv88e6341_ops = {
4599 /* MV88E6XXX_FAMILY_6341 */
4600 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4601 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4602 .irl_init_all = mv88e6352_g2_irl_init_all,
4603 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4604 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4605 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4606 .phy_read = mv88e6xxx_g2_smi_phy_read,
4607 .phy_write = mv88e6xxx_g2_smi_phy_write,
4608 .port_set_link = mv88e6xxx_port_set_link,
4609 .port_sync_link = mv88e6xxx_port_sync_link,
4610 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4611 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
4612 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
4613 .port_tag_remap = mv88e6095_port_tag_remap,
4614 .port_set_policy = mv88e6352_port_set_policy,
4615 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4616 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4617 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4618 .port_set_ether_type = mv88e6351_port_set_ether_type,
4619 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4620 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4621 .port_pause_limit = mv88e6097_port_pause_limit,
4622 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4623 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4624 .port_get_cmode = mv88e6352_port_get_cmode,
4625 .port_set_cmode = mv88e6341_port_set_cmode,
4626 .port_setup_message_port = mv88e6xxx_setup_message_port,
4627 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4628 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4629 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4630 .stats_get_strings = mv88e6320_stats_get_strings,
4631 .stats_get_stats = mv88e6390_stats_get_stats,
4632 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4633 .set_egress_port = mv88e6390_g1_set_egress_port,
4634 .watchdog_ops = &mv88e6390_watchdog_ops,
4635 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4636 .pot_clear = mv88e6xxx_g2_pot_clear,
4637 .reset = mv88e6352_g1_reset,
4638 .rmu_disable = mv88e6390_g1_rmu_disable,
4639 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4640 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4641 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4642 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4643 .serdes_power = mv88e6390_serdes_power,
4644 .serdes_get_lane = mv88e6341_serdes_get_lane,
4645 /* Check status register pause & lpa register */
4646 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4647 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4648 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4649 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4650 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4651 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4652 .serdes_irq_status = mv88e6390_serdes_irq_status,
4653 .gpio_ops = &mv88e6352_gpio_ops,
4654 .avb_ops = &mv88e6390_avb_ops,
4655 .ptp_ops = &mv88e6352_ptp_ops,
4656 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4657 .serdes_get_strings = mv88e6390_serdes_get_strings,
4658 .serdes_get_stats = mv88e6390_serdes_get_stats,
4659 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4660 .serdes_get_regs = mv88e6390_serdes_get_regs,
4661 .phylink_validate = mv88e6341_phylink_validate,
4662 };
4663
4664 static const struct mv88e6xxx_ops mv88e6350_ops = {
4665 /* MV88E6XXX_FAMILY_6351 */
4666 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4667 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4668 .irl_init_all = mv88e6352_g2_irl_init_all,
4669 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4670 .phy_read = mv88e6xxx_g2_smi_phy_read,
4671 .phy_write = mv88e6xxx_g2_smi_phy_write,
4672 .port_set_link = mv88e6xxx_port_set_link,
4673 .port_sync_link = mv88e6xxx_port_sync_link,
4674 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4675 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4676 .port_tag_remap = mv88e6095_port_tag_remap,
4677 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4678 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4679 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4680 .port_set_ether_type = mv88e6351_port_set_ether_type,
4681 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4682 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4683 .port_pause_limit = mv88e6097_port_pause_limit,
4684 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4685 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4686 .port_get_cmode = mv88e6352_port_get_cmode,
4687 .port_setup_message_port = mv88e6xxx_setup_message_port,
4688 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4689 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4690 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4691 .stats_get_strings = mv88e6095_stats_get_strings,
4692 .stats_get_stats = mv88e6095_stats_get_stats,
4693 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4694 .set_egress_port = mv88e6095_g1_set_egress_port,
4695 .watchdog_ops = &mv88e6097_watchdog_ops,
4696 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4697 .pot_clear = mv88e6xxx_g2_pot_clear,
4698 .reset = mv88e6352_g1_reset,
4699 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4700 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4701 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4702 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4703 .phylink_validate = mv88e6185_phylink_validate,
4704 };
4705
4706 static const struct mv88e6xxx_ops mv88e6351_ops = {
4707 /* MV88E6XXX_FAMILY_6351 */
4708 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4709 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4710 .irl_init_all = mv88e6352_g2_irl_init_all,
4711 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4712 .phy_read = mv88e6xxx_g2_smi_phy_read,
4713 .phy_write = mv88e6xxx_g2_smi_phy_write,
4714 .port_set_link = mv88e6xxx_port_set_link,
4715 .port_sync_link = mv88e6xxx_port_sync_link,
4716 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4717 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4718 .port_tag_remap = mv88e6095_port_tag_remap,
4719 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4720 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4721 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4722 .port_set_ether_type = mv88e6351_port_set_ether_type,
4723 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4724 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4725 .port_pause_limit = mv88e6097_port_pause_limit,
4726 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4727 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4728 .port_get_cmode = mv88e6352_port_get_cmode,
4729 .port_setup_message_port = mv88e6xxx_setup_message_port,
4730 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4731 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4732 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4733 .stats_get_strings = mv88e6095_stats_get_strings,
4734 .stats_get_stats = mv88e6095_stats_get_stats,
4735 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4736 .set_egress_port = mv88e6095_g1_set_egress_port,
4737 .watchdog_ops = &mv88e6097_watchdog_ops,
4738 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4739 .pot_clear = mv88e6xxx_g2_pot_clear,
4740 .reset = mv88e6352_g1_reset,
4741 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4742 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4743 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4744 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4745 .avb_ops = &mv88e6352_avb_ops,
4746 .ptp_ops = &mv88e6352_ptp_ops,
4747 .phylink_validate = mv88e6185_phylink_validate,
4748 };
4749
4750 static const struct mv88e6xxx_ops mv88e6352_ops = {
4751 /* MV88E6XXX_FAMILY_6352 */
4752 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4753 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4754 .irl_init_all = mv88e6352_g2_irl_init_all,
4755 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4756 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4757 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4758 .phy_read = mv88e6xxx_g2_smi_phy_read,
4759 .phy_write = mv88e6xxx_g2_smi_phy_write,
4760 .port_set_link = mv88e6xxx_port_set_link,
4761 .port_sync_link = mv88e6xxx_port_sync_link,
4762 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4763 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4764 .port_tag_remap = mv88e6095_port_tag_remap,
4765 .port_set_policy = mv88e6352_port_set_policy,
4766 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4767 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4768 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4769 .port_set_ether_type = mv88e6351_port_set_ether_type,
4770 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4771 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4772 .port_pause_limit = mv88e6097_port_pause_limit,
4773 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4774 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4775 .port_get_cmode = mv88e6352_port_get_cmode,
4776 .port_setup_message_port = mv88e6xxx_setup_message_port,
4777 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4778 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4779 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4780 .stats_get_strings = mv88e6095_stats_get_strings,
4781 .stats_get_stats = mv88e6095_stats_get_stats,
4782 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4783 .set_egress_port = mv88e6095_g1_set_egress_port,
4784 .watchdog_ops = &mv88e6097_watchdog_ops,
4785 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4786 .pot_clear = mv88e6xxx_g2_pot_clear,
4787 .reset = mv88e6352_g1_reset,
4788 .rmu_disable = mv88e6352_g1_rmu_disable,
4789 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4790 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4791 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4792 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4793 .serdes_get_lane = mv88e6352_serdes_get_lane,
4794 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4795 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4796 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4797 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
4798 .serdes_power = mv88e6352_serdes_power,
4799 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4800 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
4801 .serdes_irq_status = mv88e6352_serdes_irq_status,
4802 .gpio_ops = &mv88e6352_gpio_ops,
4803 .avb_ops = &mv88e6352_avb_ops,
4804 .ptp_ops = &mv88e6352_ptp_ops,
4805 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
4806 .serdes_get_strings = mv88e6352_serdes_get_strings,
4807 .serdes_get_stats = mv88e6352_serdes_get_stats,
4808 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4809 .serdes_get_regs = mv88e6352_serdes_get_regs,
4810 .phylink_validate = mv88e6352_phylink_validate,
4811 };
4812
4813 static const struct mv88e6xxx_ops mv88e6390_ops = {
4814 /* MV88E6XXX_FAMILY_6390 */
4815 .setup_errata = mv88e6390_setup_errata,
4816 .irl_init_all = mv88e6390_g2_irl_init_all,
4817 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4818 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4819 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4820 .phy_read = mv88e6xxx_g2_smi_phy_read,
4821 .phy_write = mv88e6xxx_g2_smi_phy_write,
4822 .port_set_link = mv88e6xxx_port_set_link,
4823 .port_sync_link = mv88e6xxx_port_sync_link,
4824 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4825 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4826 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4827 .port_tag_remap = mv88e6390_port_tag_remap,
4828 .port_set_policy = mv88e6352_port_set_policy,
4829 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4830 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4831 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4832 .port_set_ether_type = mv88e6351_port_set_ether_type,
4833 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4834 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4835 .port_pause_limit = mv88e6390_port_pause_limit,
4836 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4837 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4838 .port_get_cmode = mv88e6352_port_get_cmode,
4839 .port_set_cmode = mv88e6390_port_set_cmode,
4840 .port_setup_message_port = mv88e6xxx_setup_message_port,
4841 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4842 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4843 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4844 .stats_get_strings = mv88e6320_stats_get_strings,
4845 .stats_get_stats = mv88e6390_stats_get_stats,
4846 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4847 .set_egress_port = mv88e6390_g1_set_egress_port,
4848 .watchdog_ops = &mv88e6390_watchdog_ops,
4849 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4850 .pot_clear = mv88e6xxx_g2_pot_clear,
4851 .reset = mv88e6352_g1_reset,
4852 .rmu_disable = mv88e6390_g1_rmu_disable,
4853 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4854 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4855 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4856 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4857 .serdes_power = mv88e6390_serdes_power,
4858 .serdes_get_lane = mv88e6390_serdes_get_lane,
4859 /* Check status register pause & lpa register */
4860 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4861 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4862 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4863 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4864 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4865 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4866 .serdes_irq_status = mv88e6390_serdes_irq_status,
4867 .gpio_ops = &mv88e6352_gpio_ops,
4868 .avb_ops = &mv88e6390_avb_ops,
4869 .ptp_ops = &mv88e6352_ptp_ops,
4870 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4871 .serdes_get_strings = mv88e6390_serdes_get_strings,
4872 .serdes_get_stats = mv88e6390_serdes_get_stats,
4873 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4874 .serdes_get_regs = mv88e6390_serdes_get_regs,
4875 .phylink_validate = mv88e6390_phylink_validate,
4876 };
4877
4878 static const struct mv88e6xxx_ops mv88e6390x_ops = {
4879 /* MV88E6XXX_FAMILY_6390 */
4880 .setup_errata = mv88e6390_setup_errata,
4881 .irl_init_all = mv88e6390_g2_irl_init_all,
4882 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4883 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4884 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4885 .phy_read = mv88e6xxx_g2_smi_phy_read,
4886 .phy_write = mv88e6xxx_g2_smi_phy_write,
4887 .port_set_link = mv88e6xxx_port_set_link,
4888 .port_sync_link = mv88e6xxx_port_sync_link,
4889 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4890 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
4891 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4892 .port_tag_remap = mv88e6390_port_tag_remap,
4893 .port_set_policy = mv88e6352_port_set_policy,
4894 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4895 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4896 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4897 .port_set_ether_type = mv88e6351_port_set_ether_type,
4898 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4899 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4900 .port_pause_limit = mv88e6390_port_pause_limit,
4901 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4902 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4903 .port_get_cmode = mv88e6352_port_get_cmode,
4904 .port_set_cmode = mv88e6390x_port_set_cmode,
4905 .port_setup_message_port = mv88e6xxx_setup_message_port,
4906 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4907 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4908 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4909 .stats_get_strings = mv88e6320_stats_get_strings,
4910 .stats_get_stats = mv88e6390_stats_get_stats,
4911 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4912 .set_egress_port = mv88e6390_g1_set_egress_port,
4913 .watchdog_ops = &mv88e6390_watchdog_ops,
4914 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4915 .pot_clear = mv88e6xxx_g2_pot_clear,
4916 .reset = mv88e6352_g1_reset,
4917 .rmu_disable = mv88e6390_g1_rmu_disable,
4918 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4919 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4920 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4921 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4922 .serdes_power = mv88e6390_serdes_power,
4923 .serdes_get_lane = mv88e6390x_serdes_get_lane,
4924 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4925 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4926 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4927 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4928 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4929 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4930 .serdes_irq_status = mv88e6390_serdes_irq_status,
4931 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4932 .serdes_get_strings = mv88e6390_serdes_get_strings,
4933 .serdes_get_stats = mv88e6390_serdes_get_stats,
4934 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4935 .serdes_get_regs = mv88e6390_serdes_get_regs,
4936 .gpio_ops = &mv88e6352_gpio_ops,
4937 .avb_ops = &mv88e6390_avb_ops,
4938 .ptp_ops = &mv88e6352_ptp_ops,
4939 .phylink_validate = mv88e6390x_phylink_validate,
4940 };
4941
4942 static const struct mv88e6xxx_ops mv88e6393x_ops = {
4943 /* MV88E6XXX_FAMILY_6393 */
4944 .setup_errata = mv88e6393x_serdes_setup_errata,
4945 .irl_init_all = mv88e6390_g2_irl_init_all,
4946 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4947 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4948 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4949 .phy_read = mv88e6xxx_g2_smi_phy_read,
4950 .phy_write = mv88e6xxx_g2_smi_phy_write,
4951 .port_set_link = mv88e6xxx_port_set_link,
4952 .port_sync_link = mv88e6xxx_port_sync_link,
4953 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4954 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex,
4955 .port_max_speed_mode = mv88e6393x_port_max_speed_mode,
4956 .port_tag_remap = mv88e6390_port_tag_remap,
4957 .port_set_policy = mv88e6393x_port_set_policy,
4958 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4959 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4960 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4961 .port_set_ether_type = mv88e6393x_port_set_ether_type,
4962 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4963 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4964 .port_pause_limit = mv88e6390_port_pause_limit,
4965 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4966 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4967 .port_get_cmode = mv88e6352_port_get_cmode,
4968 .port_set_cmode = mv88e6393x_port_set_cmode,
4969 .port_setup_message_port = mv88e6xxx_setup_message_port,
4970 .port_set_upstream_port = mv88e6393x_port_set_upstream_port,
4971 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4972 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4973 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4974 .stats_get_strings = mv88e6320_stats_get_strings,
4975 .stats_get_stats = mv88e6390_stats_get_stats,
4976 /* .set_cpu_port is missing because this family does not support a global
4977 * CPU port, only per port CPU port which is set via
4978 * .port_set_upstream_port method.
4979 */
4980 .set_egress_port = mv88e6393x_set_egress_port,
4981 .watchdog_ops = &mv88e6393x_watchdog_ops,
4982 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu,
4983 .pot_clear = mv88e6xxx_g2_pot_clear,
4984 .reset = mv88e6352_g1_reset,
4985 .rmu_disable = mv88e6390_g1_rmu_disable,
4986 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4987 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4988 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4989 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4990 .serdes_power = mv88e6393x_serdes_power,
4991 .serdes_get_lane = mv88e6393x_serdes_get_lane,
4992 .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state,
4993 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4994 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4995 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4996 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4997 .serdes_irq_enable = mv88e6393x_serdes_irq_enable,
4998 .serdes_irq_status = mv88e6393x_serdes_irq_status,
4999 /* TODO: serdes stats */
5000 .gpio_ops = &mv88e6352_gpio_ops,
5001 .avb_ops = &mv88e6390_avb_ops,
5002 .ptp_ops = &mv88e6352_ptp_ops,
5003 .phylink_validate = mv88e6393x_phylink_validate,
5004 };
5005
5006 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
5007 [MV88E6085] = {
5008 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
5009 .family = MV88E6XXX_FAMILY_6097,
5010 .name = "Marvell 88E6085",
5011 .num_databases = 4096,
5012 .num_macs = 8192,
5013 .num_ports = 10,
5014 .num_internal_phys = 5,
5015 .max_vid = 4095,
5016 .port_base_addr = 0x10,
5017 .phy_base_addr = 0x0,
5018 .global1_addr = 0x1b,
5019 .global2_addr = 0x1c,
5020 .age_time_coeff = 15000,
5021 .g1_irqs = 8,
5022 .g2_irqs = 10,
5023 .atu_move_port_mask = 0xf,
5024 .pvt = true,
5025 .multi_chip = true,
5026 .ops = &mv88e6085_ops,
5027 },
5028
5029 [MV88E6095] = {
5030 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
5031 .family = MV88E6XXX_FAMILY_6095,
5032 .name = "Marvell 88E6095/88E6095F",
5033 .num_databases = 256,
5034 .num_macs = 8192,
5035 .num_ports = 11,
5036 .num_internal_phys = 0,
5037 .max_vid = 4095,
5038 .port_base_addr = 0x10,
5039 .phy_base_addr = 0x0,
5040 .global1_addr = 0x1b,
5041 .global2_addr = 0x1c,
5042 .age_time_coeff = 15000,
5043 .g1_irqs = 8,
5044 .atu_move_port_mask = 0xf,
5045 .multi_chip = true,
5046 .ops = &mv88e6095_ops,
5047 },
5048
5049 [MV88E6097] = {
5050 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
5051 .family = MV88E6XXX_FAMILY_6097,
5052 .name = "Marvell 88E6097/88E6097F",
5053 .num_databases = 4096,
5054 .num_macs = 8192,
5055 .num_ports = 11,
5056 .num_internal_phys = 8,
5057 .max_vid = 4095,
5058 .port_base_addr = 0x10,
5059 .phy_base_addr = 0x0,
5060 .global1_addr = 0x1b,
5061 .global2_addr = 0x1c,
5062 .age_time_coeff = 15000,
5063 .g1_irqs = 8,
5064 .g2_irqs = 10,
5065 .atu_move_port_mask = 0xf,
5066 .pvt = true,
5067 .multi_chip = true,
5068 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5069 .ops = &mv88e6097_ops,
5070 },
5071
5072 [MV88E6123] = {
5073 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
5074 .family = MV88E6XXX_FAMILY_6165,
5075 .name = "Marvell 88E6123",
5076 .num_databases = 4096,
5077 .num_macs = 1024,
5078 .num_ports = 3,
5079 .num_internal_phys = 5,
5080 .max_vid = 4095,
5081 .port_base_addr = 0x10,
5082 .phy_base_addr = 0x0,
5083 .global1_addr = 0x1b,
5084 .global2_addr = 0x1c,
5085 .age_time_coeff = 15000,
5086 .g1_irqs = 9,
5087 .g2_irqs = 10,
5088 .atu_move_port_mask = 0xf,
5089 .pvt = true,
5090 .multi_chip = true,
5091 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5092 .ops = &mv88e6123_ops,
5093 },
5094
5095 [MV88E6131] = {
5096 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
5097 .family = MV88E6XXX_FAMILY_6185,
5098 .name = "Marvell 88E6131",
5099 .num_databases = 256,
5100 .num_macs = 8192,
5101 .num_ports = 8,
5102 .num_internal_phys = 0,
5103 .max_vid = 4095,
5104 .port_base_addr = 0x10,
5105 .phy_base_addr = 0x0,
5106 .global1_addr = 0x1b,
5107 .global2_addr = 0x1c,
5108 .age_time_coeff = 15000,
5109 .g1_irqs = 9,
5110 .atu_move_port_mask = 0xf,
5111 .multi_chip = true,
5112 .ops = &mv88e6131_ops,
5113 },
5114
5115 [MV88E6141] = {
5116 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
5117 .family = MV88E6XXX_FAMILY_6341,
5118 .name = "Marvell 88E6141",
5119 .num_databases = 4096,
5120 .num_macs = 2048,
5121 .num_ports = 6,
5122 .num_internal_phys = 5,
5123 .num_gpio = 11,
5124 .max_vid = 4095,
5125 .port_base_addr = 0x10,
5126 .phy_base_addr = 0x10,
5127 .global1_addr = 0x1b,
5128 .global2_addr = 0x1c,
5129 .age_time_coeff = 3750,
5130 .atu_move_port_mask = 0x1f,
5131 .g1_irqs = 9,
5132 .g2_irqs = 10,
5133 .pvt = true,
5134 .multi_chip = true,
5135 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5136 .ops = &mv88e6141_ops,
5137 },
5138
5139 [MV88E6161] = {
5140 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
5141 .family = MV88E6XXX_FAMILY_6165,
5142 .name = "Marvell 88E6161",
5143 .num_databases = 4096,
5144 .num_macs = 1024,
5145 .num_ports = 6,
5146 .num_internal_phys = 5,
5147 .max_vid = 4095,
5148 .port_base_addr = 0x10,
5149 .phy_base_addr = 0x0,
5150 .global1_addr = 0x1b,
5151 .global2_addr = 0x1c,
5152 .age_time_coeff = 15000,
5153 .g1_irqs = 9,
5154 .g2_irqs = 10,
5155 .atu_move_port_mask = 0xf,
5156 .pvt = true,
5157 .multi_chip = true,
5158 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5159 .ptp_support = true,
5160 .ops = &mv88e6161_ops,
5161 },
5162
5163 [MV88E6165] = {
5164 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
5165 .family = MV88E6XXX_FAMILY_6165,
5166 .name = "Marvell 88E6165",
5167 .num_databases = 4096,
5168 .num_macs = 8192,
5169 .num_ports = 6,
5170 .num_internal_phys = 0,
5171 .max_vid = 4095,
5172 .port_base_addr = 0x10,
5173 .phy_base_addr = 0x0,
5174 .global1_addr = 0x1b,
5175 .global2_addr = 0x1c,
5176 .age_time_coeff = 15000,
5177 .g1_irqs = 9,
5178 .g2_irqs = 10,
5179 .atu_move_port_mask = 0xf,
5180 .pvt = true,
5181 .multi_chip = true,
5182 .ptp_support = true,
5183 .ops = &mv88e6165_ops,
5184 },
5185
5186 [MV88E6171] = {
5187 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
5188 .family = MV88E6XXX_FAMILY_6351,
5189 .name = "Marvell 88E6171",
5190 .num_databases = 4096,
5191 .num_macs = 8192,
5192 .num_ports = 7,
5193 .num_internal_phys = 5,
5194 .max_vid = 4095,
5195 .port_base_addr = 0x10,
5196 .phy_base_addr = 0x0,
5197 .global1_addr = 0x1b,
5198 .global2_addr = 0x1c,
5199 .age_time_coeff = 15000,
5200 .g1_irqs = 9,
5201 .g2_irqs = 10,
5202 .atu_move_port_mask = 0xf,
5203 .pvt = true,
5204 .multi_chip = true,
5205 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5206 .ops = &mv88e6171_ops,
5207 },
5208
5209 [MV88E6172] = {
5210 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
5211 .family = MV88E6XXX_FAMILY_6352,
5212 .name = "Marvell 88E6172",
5213 .num_databases = 4096,
5214 .num_macs = 8192,
5215 .num_ports = 7,
5216 .num_internal_phys = 5,
5217 .num_gpio = 15,
5218 .max_vid = 4095,
5219 .port_base_addr = 0x10,
5220 .phy_base_addr = 0x0,
5221 .global1_addr = 0x1b,
5222 .global2_addr = 0x1c,
5223 .age_time_coeff = 15000,
5224 .g1_irqs = 9,
5225 .g2_irqs = 10,
5226 .atu_move_port_mask = 0xf,
5227 .pvt = true,
5228 .multi_chip = true,
5229 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5230 .ops = &mv88e6172_ops,
5231 },
5232
5233 [MV88E6175] = {
5234 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
5235 .family = MV88E6XXX_FAMILY_6351,
5236 .name = "Marvell 88E6175",
5237 .num_databases = 4096,
5238 .num_macs = 8192,
5239 .num_ports = 7,
5240 .num_internal_phys = 5,
5241 .max_vid = 4095,
5242 .port_base_addr = 0x10,
5243 .phy_base_addr = 0x0,
5244 .global1_addr = 0x1b,
5245 .global2_addr = 0x1c,
5246 .age_time_coeff = 15000,
5247 .g1_irqs = 9,
5248 .g2_irqs = 10,
5249 .atu_move_port_mask = 0xf,
5250 .pvt = true,
5251 .multi_chip = true,
5252 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5253 .ops = &mv88e6175_ops,
5254 },
5255
5256 [MV88E6176] = {
5257 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
5258 .family = MV88E6XXX_FAMILY_6352,
5259 .name = "Marvell 88E6176",
5260 .num_databases = 4096,
5261 .num_macs = 8192,
5262 .num_ports = 7,
5263 .num_internal_phys = 5,
5264 .num_gpio = 15,
5265 .max_vid = 4095,
5266 .port_base_addr = 0x10,
5267 .phy_base_addr = 0x0,
5268 .global1_addr = 0x1b,
5269 .global2_addr = 0x1c,
5270 .age_time_coeff = 15000,
5271 .g1_irqs = 9,
5272 .g2_irqs = 10,
5273 .atu_move_port_mask = 0xf,
5274 .pvt = true,
5275 .multi_chip = true,
5276 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5277 .ops = &mv88e6176_ops,
5278 },
5279
5280 [MV88E6185] = {
5281 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
5282 .family = MV88E6XXX_FAMILY_6185,
5283 .name = "Marvell 88E6185",
5284 .num_databases = 256,
5285 .num_macs = 8192,
5286 .num_ports = 10,
5287 .num_internal_phys = 0,
5288 .max_vid = 4095,
5289 .port_base_addr = 0x10,
5290 .phy_base_addr = 0x0,
5291 .global1_addr = 0x1b,
5292 .global2_addr = 0x1c,
5293 .age_time_coeff = 15000,
5294 .g1_irqs = 8,
5295 .atu_move_port_mask = 0xf,
5296 .multi_chip = true,
5297 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5298 .ops = &mv88e6185_ops,
5299 },
5300
5301 [MV88E6190] = {
5302 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
5303 .family = MV88E6XXX_FAMILY_6390,
5304 .name = "Marvell 88E6190",
5305 .num_databases = 4096,
5306 .num_macs = 16384,
5307 .num_ports = 11, /* 10 + Z80 */
5308 .num_internal_phys = 9,
5309 .num_gpio = 16,
5310 .max_vid = 8191,
5311 .port_base_addr = 0x0,
5312 .phy_base_addr = 0x0,
5313 .global1_addr = 0x1b,
5314 .global2_addr = 0x1c,
5315 .age_time_coeff = 3750,
5316 .g1_irqs = 9,
5317 .g2_irqs = 14,
5318 .pvt = true,
5319 .multi_chip = true,
5320 .atu_move_port_mask = 0x1f,
5321 .ops = &mv88e6190_ops,
5322 },
5323
5324 [MV88E6190X] = {
5325 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
5326 .family = MV88E6XXX_FAMILY_6390,
5327 .name = "Marvell 88E6190X",
5328 .num_databases = 4096,
5329 .num_macs = 16384,
5330 .num_ports = 11, /* 10 + Z80 */
5331 .num_internal_phys = 9,
5332 .num_gpio = 16,
5333 .max_vid = 8191,
5334 .port_base_addr = 0x0,
5335 .phy_base_addr = 0x0,
5336 .global1_addr = 0x1b,
5337 .global2_addr = 0x1c,
5338 .age_time_coeff = 3750,
5339 .g1_irqs = 9,
5340 .g2_irqs = 14,
5341 .atu_move_port_mask = 0x1f,
5342 .pvt = true,
5343 .multi_chip = true,
5344 .ops = &mv88e6190x_ops,
5345 },
5346
5347 [MV88E6191] = {
5348 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
5349 .family = MV88E6XXX_FAMILY_6390,
5350 .name = "Marvell 88E6191",
5351 .num_databases = 4096,
5352 .num_macs = 16384,
5353 .num_ports = 11, /* 10 + Z80 */
5354 .num_internal_phys = 9,
5355 .max_vid = 8191,
5356 .port_base_addr = 0x0,
5357 .phy_base_addr = 0x0,
5358 .global1_addr = 0x1b,
5359 .global2_addr = 0x1c,
5360 .age_time_coeff = 3750,
5361 .g1_irqs = 9,
5362 .g2_irqs = 14,
5363 .atu_move_port_mask = 0x1f,
5364 .pvt = true,
5365 .multi_chip = true,
5366 .ptp_support = true,
5367 .ops = &mv88e6191_ops,
5368 },
5369
5370 [MV88E6191X] = {
5371 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X,
5372 .family = MV88E6XXX_FAMILY_6393,
5373 .name = "Marvell 88E6191X",
5374 .num_databases = 4096,
5375 .num_ports = 11, /* 10 + Z80 */
5376 .num_internal_phys = 9,
5377 .max_vid = 8191,
5378 .port_base_addr = 0x0,
5379 .phy_base_addr = 0x0,
5380 .global1_addr = 0x1b,
5381 .global2_addr = 0x1c,
5382 .age_time_coeff = 3750,
5383 .g1_irqs = 10,
5384 .g2_irqs = 14,
5385 .atu_move_port_mask = 0x1f,
5386 .pvt = true,
5387 .multi_chip = true,
5388 .ptp_support = true,
5389 .ops = &mv88e6393x_ops,
5390 },
5391
5392 [MV88E6193X] = {
5393 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X,
5394 .family = MV88E6XXX_FAMILY_6393,
5395 .name = "Marvell 88E6193X",
5396 .num_databases = 4096,
5397 .num_ports = 11, /* 10 + Z80 */
5398 .num_internal_phys = 9,
5399 .max_vid = 8191,
5400 .port_base_addr = 0x0,
5401 .phy_base_addr = 0x0,
5402 .global1_addr = 0x1b,
5403 .global2_addr = 0x1c,
5404 .age_time_coeff = 3750,
5405 .g1_irqs = 10,
5406 .g2_irqs = 14,
5407 .atu_move_port_mask = 0x1f,
5408 .pvt = true,
5409 .multi_chip = true,
5410 .ptp_support = true,
5411 .ops = &mv88e6393x_ops,
5412 },
5413
5414 [MV88E6220] = {
5415 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
5416 .family = MV88E6XXX_FAMILY_6250,
5417 .name = "Marvell 88E6220",
5418 .num_databases = 64,
5419
5420 /* Ports 2-4 are not routed to pins
5421 * => usable ports 0, 1, 5, 6
5422 */
5423 .num_ports = 7,
5424 .num_internal_phys = 2,
5425 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
5426 .max_vid = 4095,
5427 .port_base_addr = 0x08,
5428 .phy_base_addr = 0x00,
5429 .global1_addr = 0x0f,
5430 .global2_addr = 0x07,
5431 .age_time_coeff = 15000,
5432 .g1_irqs = 9,
5433 .g2_irqs = 10,
5434 .atu_move_port_mask = 0xf,
5435 .dual_chip = true,
5436 .ptp_support = true,
5437 .ops = &mv88e6250_ops,
5438 },
5439
5440 [MV88E6240] = {
5441 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
5442 .family = MV88E6XXX_FAMILY_6352,
5443 .name = "Marvell 88E6240",
5444 .num_databases = 4096,
5445 .num_macs = 8192,
5446 .num_ports = 7,
5447 .num_internal_phys = 5,
5448 .num_gpio = 15,
5449 .max_vid = 4095,
5450 .port_base_addr = 0x10,
5451 .phy_base_addr = 0x0,
5452 .global1_addr = 0x1b,
5453 .global2_addr = 0x1c,
5454 .age_time_coeff = 15000,
5455 .g1_irqs = 9,
5456 .g2_irqs = 10,
5457 .atu_move_port_mask = 0xf,
5458 .pvt = true,
5459 .multi_chip = true,
5460 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5461 .ptp_support = true,
5462 .ops = &mv88e6240_ops,
5463 },
5464
5465 [MV88E6250] = {
5466 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
5467 .family = MV88E6XXX_FAMILY_6250,
5468 .name = "Marvell 88E6250",
5469 .num_databases = 64,
5470 .num_ports = 7,
5471 .num_internal_phys = 5,
5472 .max_vid = 4095,
5473 .port_base_addr = 0x08,
5474 .phy_base_addr = 0x00,
5475 .global1_addr = 0x0f,
5476 .global2_addr = 0x07,
5477 .age_time_coeff = 15000,
5478 .g1_irqs = 9,
5479 .g2_irqs = 10,
5480 .atu_move_port_mask = 0xf,
5481 .dual_chip = true,
5482 .ptp_support = true,
5483 .ops = &mv88e6250_ops,
5484 },
5485
5486 [MV88E6290] = {
5487 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
5488 .family = MV88E6XXX_FAMILY_6390,
5489 .name = "Marvell 88E6290",
5490 .num_databases = 4096,
5491 .num_ports = 11, /* 10 + Z80 */
5492 .num_internal_phys = 9,
5493 .num_gpio = 16,
5494 .max_vid = 8191,
5495 .port_base_addr = 0x0,
5496 .phy_base_addr = 0x0,
5497 .global1_addr = 0x1b,
5498 .global2_addr = 0x1c,
5499 .age_time_coeff = 3750,
5500 .g1_irqs = 9,
5501 .g2_irqs = 14,
5502 .atu_move_port_mask = 0x1f,
5503 .pvt = true,
5504 .multi_chip = true,
5505 .ptp_support = true,
5506 .ops = &mv88e6290_ops,
5507 },
5508
5509 [MV88E6320] = {
5510 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
5511 .family = MV88E6XXX_FAMILY_6320,
5512 .name = "Marvell 88E6320",
5513 .num_databases = 4096,
5514 .num_macs = 8192,
5515 .num_ports = 7,
5516 .num_internal_phys = 5,
5517 .num_gpio = 15,
5518 .max_vid = 4095,
5519 .port_base_addr = 0x10,
5520 .phy_base_addr = 0x0,
5521 .global1_addr = 0x1b,
5522 .global2_addr = 0x1c,
5523 .age_time_coeff = 15000,
5524 .g1_irqs = 8,
5525 .g2_irqs = 10,
5526 .atu_move_port_mask = 0xf,
5527 .pvt = true,
5528 .multi_chip = true,
5529 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5530 .ptp_support = true,
5531 .ops = &mv88e6320_ops,
5532 },
5533
5534 [MV88E6321] = {
5535 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
5536 .family = MV88E6XXX_FAMILY_6320,
5537 .name = "Marvell 88E6321",
5538 .num_databases = 4096,
5539 .num_macs = 8192,
5540 .num_ports = 7,
5541 .num_internal_phys = 5,
5542 .num_gpio = 15,
5543 .max_vid = 4095,
5544 .port_base_addr = 0x10,
5545 .phy_base_addr = 0x0,
5546 .global1_addr = 0x1b,
5547 .global2_addr = 0x1c,
5548 .age_time_coeff = 15000,
5549 .g1_irqs = 8,
5550 .g2_irqs = 10,
5551 .atu_move_port_mask = 0xf,
5552 .multi_chip = true,
5553 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5554 .ptp_support = true,
5555 .ops = &mv88e6321_ops,
5556 },
5557
5558 [MV88E6341] = {
5559 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
5560 .family = MV88E6XXX_FAMILY_6341,
5561 .name = "Marvell 88E6341",
5562 .num_databases = 4096,
5563 .num_macs = 2048,
5564 .num_internal_phys = 5,
5565 .num_ports = 6,
5566 .num_gpio = 11,
5567 .max_vid = 4095,
5568 .port_base_addr = 0x10,
5569 .phy_base_addr = 0x10,
5570 .global1_addr = 0x1b,
5571 .global2_addr = 0x1c,
5572 .age_time_coeff = 3750,
5573 .atu_move_port_mask = 0x1f,
5574 .g1_irqs = 9,
5575 .g2_irqs = 10,
5576 .pvt = true,
5577 .multi_chip = true,
5578 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5579 .ptp_support = true,
5580 .ops = &mv88e6341_ops,
5581 },
5582
5583 [MV88E6350] = {
5584 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
5585 .family = MV88E6XXX_FAMILY_6351,
5586 .name = "Marvell 88E6350",
5587 .num_databases = 4096,
5588 .num_macs = 8192,
5589 .num_ports = 7,
5590 .num_internal_phys = 5,
5591 .max_vid = 4095,
5592 .port_base_addr = 0x10,
5593 .phy_base_addr = 0x0,
5594 .global1_addr = 0x1b,
5595 .global2_addr = 0x1c,
5596 .age_time_coeff = 15000,
5597 .g1_irqs = 9,
5598 .g2_irqs = 10,
5599 .atu_move_port_mask = 0xf,
5600 .pvt = true,
5601 .multi_chip = true,
5602 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5603 .ops = &mv88e6350_ops,
5604 },
5605
5606 [MV88E6351] = {
5607 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
5608 .family = MV88E6XXX_FAMILY_6351,
5609 .name = "Marvell 88E6351",
5610 .num_databases = 4096,
5611 .num_macs = 8192,
5612 .num_ports = 7,
5613 .num_internal_phys = 5,
5614 .max_vid = 4095,
5615 .port_base_addr = 0x10,
5616 .phy_base_addr = 0x0,
5617 .global1_addr = 0x1b,
5618 .global2_addr = 0x1c,
5619 .age_time_coeff = 15000,
5620 .g1_irqs = 9,
5621 .g2_irqs = 10,
5622 .atu_move_port_mask = 0xf,
5623 .pvt = true,
5624 .multi_chip = true,
5625 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5626 .ops = &mv88e6351_ops,
5627 },
5628
5629 [MV88E6352] = {
5630 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
5631 .family = MV88E6XXX_FAMILY_6352,
5632 .name = "Marvell 88E6352",
5633 .num_databases = 4096,
5634 .num_macs = 8192,
5635 .num_ports = 7,
5636 .num_internal_phys = 5,
5637 .num_gpio = 15,
5638 .max_vid = 4095,
5639 .port_base_addr = 0x10,
5640 .phy_base_addr = 0x0,
5641 .global1_addr = 0x1b,
5642 .global2_addr = 0x1c,
5643 .age_time_coeff = 15000,
5644 .g1_irqs = 9,
5645 .g2_irqs = 10,
5646 .atu_move_port_mask = 0xf,
5647 .pvt = true,
5648 .multi_chip = true,
5649 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5650 .ptp_support = true,
5651 .ops = &mv88e6352_ops,
5652 },
5653 [MV88E6390] = {
5654 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
5655 .family = MV88E6XXX_FAMILY_6390,
5656 .name = "Marvell 88E6390",
5657 .num_databases = 4096,
5658 .num_macs = 16384,
5659 .num_ports = 11, /* 10 + Z80 */
5660 .num_internal_phys = 9,
5661 .num_gpio = 16,
5662 .max_vid = 8191,
5663 .port_base_addr = 0x0,
5664 .phy_base_addr = 0x0,
5665 .global1_addr = 0x1b,
5666 .global2_addr = 0x1c,
5667 .age_time_coeff = 3750,
5668 .g1_irqs = 9,
5669 .g2_irqs = 14,
5670 .atu_move_port_mask = 0x1f,
5671 .pvt = true,
5672 .multi_chip = true,
5673 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
5674 .ptp_support = true,
5675 .ops = &mv88e6390_ops,
5676 },
5677 [MV88E6390X] = {
5678 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
5679 .family = MV88E6XXX_FAMILY_6390,
5680 .name = "Marvell 88E6390X",
5681 .num_databases = 4096,
5682 .num_macs = 16384,
5683 .num_ports = 11, /* 10 + Z80 */
5684 .num_internal_phys = 9,
5685 .num_gpio = 16,
5686 .max_vid = 8191,
5687 .port_base_addr = 0x0,
5688 .phy_base_addr = 0x0,
5689 .global1_addr = 0x1b,
5690 .global2_addr = 0x1c,
5691 .age_time_coeff = 3750,
5692 .g1_irqs = 9,
5693 .g2_irqs = 14,
5694 .atu_move_port_mask = 0x1f,
5695 .pvt = true,
5696 .multi_chip = true,
5697 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
5698 .ptp_support = true,
5699 .ops = &mv88e6390x_ops,
5700 },
5701
5702 [MV88E6393X] = {
5703 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
5704 .family = MV88E6XXX_FAMILY_6393,
5705 .name = "Marvell 88E6393X",
5706 .num_databases = 4096,
5707 .num_ports = 11, /* 10 + Z80 */
5708 .num_internal_phys = 9,
5709 .max_vid = 8191,
5710 .port_base_addr = 0x0,
5711 .phy_base_addr = 0x0,
5712 .global1_addr = 0x1b,
5713 .global2_addr = 0x1c,
5714 .age_time_coeff = 3750,
5715 .g1_irqs = 10,
5716 .g2_irqs = 14,
5717 .atu_move_port_mask = 0x1f,
5718 .pvt = true,
5719 .multi_chip = true,
5720 .ptp_support = true,
5721 .ops = &mv88e6393x_ops,
5722 },
5723 };
5724
mv88e6xxx_lookup_info(unsigned int prod_num)5725 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
5726 {
5727 int i;
5728
5729 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
5730 if (mv88e6xxx_table[i].prod_num == prod_num)
5731 return &mv88e6xxx_table[i];
5732
5733 return NULL;
5734 }
5735
mv88e6xxx_detect(struct mv88e6xxx_chip * chip)5736 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
5737 {
5738 const struct mv88e6xxx_info *info;
5739 unsigned int prod_num, rev;
5740 u16 id;
5741 int err;
5742
5743 mv88e6xxx_reg_lock(chip);
5744 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
5745 mv88e6xxx_reg_unlock(chip);
5746 if (err)
5747 return err;
5748
5749 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
5750 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
5751
5752 info = mv88e6xxx_lookup_info(prod_num);
5753 if (!info)
5754 return -ENODEV;
5755
5756 /* Update the compatible info with the probed one */
5757 chip->info = info;
5758
5759 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
5760 chip->info->prod_num, chip->info->name, rev);
5761
5762 return 0;
5763 }
5764
mv88e6xxx_alloc_chip(struct device * dev)5765 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
5766 {
5767 struct mv88e6xxx_chip *chip;
5768
5769 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
5770 if (!chip)
5771 return NULL;
5772
5773 chip->dev = dev;
5774
5775 mutex_init(&chip->reg_lock);
5776 INIT_LIST_HEAD(&chip->mdios);
5777 idr_init(&chip->policies);
5778
5779 return chip;
5780 }
5781
mv88e6xxx_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol m)5782 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
5783 int port,
5784 enum dsa_tag_protocol m)
5785 {
5786 struct mv88e6xxx_chip *chip = ds->priv;
5787
5788 return chip->tag_protocol;
5789 }
5790
mv88e6xxx_change_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol proto)5791 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, int port,
5792 enum dsa_tag_protocol proto)
5793 {
5794 struct mv88e6xxx_chip *chip = ds->priv;
5795 enum dsa_tag_protocol old_protocol;
5796 int err;
5797
5798 switch (proto) {
5799 case DSA_TAG_PROTO_EDSA:
5800 switch (chip->info->edsa_support) {
5801 case MV88E6XXX_EDSA_UNSUPPORTED:
5802 return -EPROTONOSUPPORT;
5803 case MV88E6XXX_EDSA_UNDOCUMENTED:
5804 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n");
5805 fallthrough;
5806 case MV88E6XXX_EDSA_SUPPORTED:
5807 break;
5808 }
5809 break;
5810 case DSA_TAG_PROTO_DSA:
5811 break;
5812 default:
5813 return -EPROTONOSUPPORT;
5814 }
5815
5816 old_protocol = chip->tag_protocol;
5817 chip->tag_protocol = proto;
5818
5819 mv88e6xxx_reg_lock(chip);
5820 err = mv88e6xxx_setup_port_mode(chip, port);
5821 mv88e6xxx_reg_unlock(chip);
5822
5823 if (err)
5824 chip->tag_protocol = old_protocol;
5825
5826 return err;
5827 }
5828
mv88e6xxx_port_mdb_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb)5829 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
5830 const struct switchdev_obj_port_mdb *mdb)
5831 {
5832 struct mv88e6xxx_chip *chip = ds->priv;
5833 int err;
5834
5835 mv88e6xxx_reg_lock(chip);
5836 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
5837 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC);
5838 mv88e6xxx_reg_unlock(chip);
5839
5840 return err;
5841 }
5842
mv88e6xxx_port_mdb_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb)5843 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
5844 const struct switchdev_obj_port_mdb *mdb)
5845 {
5846 struct mv88e6xxx_chip *chip = ds->priv;
5847 int err;
5848
5849 mv88e6xxx_reg_lock(chip);
5850 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
5851 mv88e6xxx_reg_unlock(chip);
5852
5853 return err;
5854 }
5855
mv88e6xxx_port_mirror_add(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror,bool ingress)5856 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
5857 struct dsa_mall_mirror_tc_entry *mirror,
5858 bool ingress)
5859 {
5860 enum mv88e6xxx_egress_direction direction = ingress ?
5861 MV88E6XXX_EGRESS_DIR_INGRESS :
5862 MV88E6XXX_EGRESS_DIR_EGRESS;
5863 struct mv88e6xxx_chip *chip = ds->priv;
5864 bool other_mirrors = false;
5865 int i;
5866 int err;
5867
5868 mutex_lock(&chip->reg_lock);
5869 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
5870 mirror->to_local_port) {
5871 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5872 other_mirrors |= ingress ?
5873 chip->ports[i].mirror_ingress :
5874 chip->ports[i].mirror_egress;
5875
5876 /* Can't change egress port when other mirror is active */
5877 if (other_mirrors) {
5878 err = -EBUSY;
5879 goto out;
5880 }
5881
5882 err = mv88e6xxx_set_egress_port(chip, direction,
5883 mirror->to_local_port);
5884 if (err)
5885 goto out;
5886 }
5887
5888 err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
5889 out:
5890 mutex_unlock(&chip->reg_lock);
5891
5892 return err;
5893 }
5894
mv88e6xxx_port_mirror_del(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror)5895 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
5896 struct dsa_mall_mirror_tc_entry *mirror)
5897 {
5898 enum mv88e6xxx_egress_direction direction = mirror->ingress ?
5899 MV88E6XXX_EGRESS_DIR_INGRESS :
5900 MV88E6XXX_EGRESS_DIR_EGRESS;
5901 struct mv88e6xxx_chip *chip = ds->priv;
5902 bool other_mirrors = false;
5903 int i;
5904
5905 mutex_lock(&chip->reg_lock);
5906 if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
5907 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
5908
5909 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5910 other_mirrors |= mirror->ingress ?
5911 chip->ports[i].mirror_ingress :
5912 chip->ports[i].mirror_egress;
5913
5914 /* Reset egress port when no other mirror is active */
5915 if (!other_mirrors) {
5916 if (mv88e6xxx_set_egress_port(chip, direction,
5917 dsa_upstream_port(ds, port)))
5918 dev_err(ds->dev, "failed to set egress port\n");
5919 }
5920
5921 mutex_unlock(&chip->reg_lock);
5922 }
5923
mv88e6xxx_port_pre_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)5924 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port,
5925 struct switchdev_brport_flags flags,
5926 struct netlink_ext_ack *extack)
5927 {
5928 struct mv88e6xxx_chip *chip = ds->priv;
5929 const struct mv88e6xxx_ops *ops;
5930
5931 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
5932 BR_BCAST_FLOOD))
5933 return -EINVAL;
5934
5935 ops = chip->info->ops;
5936
5937 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood)
5938 return -EINVAL;
5939
5940 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood)
5941 return -EINVAL;
5942
5943 return 0;
5944 }
5945
mv88e6xxx_port_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)5946 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port,
5947 struct switchdev_brport_flags flags,
5948 struct netlink_ext_ack *extack)
5949 {
5950 struct mv88e6xxx_chip *chip = ds->priv;
5951 int err = -EOPNOTSUPP;
5952
5953 mv88e6xxx_reg_lock(chip);
5954
5955 if (flags.mask & BR_LEARNING) {
5956 bool learning = !!(flags.val & BR_LEARNING);
5957 u16 pav = learning ? (1 << port) : 0;
5958
5959 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav);
5960 if (err)
5961 goto out;
5962 }
5963
5964 if (flags.mask & BR_FLOOD) {
5965 bool unicast = !!(flags.val & BR_FLOOD);
5966
5967 err = chip->info->ops->port_set_ucast_flood(chip, port,
5968 unicast);
5969 if (err)
5970 goto out;
5971 }
5972
5973 if (flags.mask & BR_MCAST_FLOOD) {
5974 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
5975
5976 err = chip->info->ops->port_set_mcast_flood(chip, port,
5977 multicast);
5978 if (err)
5979 goto out;
5980 }
5981
5982 if (flags.mask & BR_BCAST_FLOOD) {
5983 bool broadcast = !!(flags.val & BR_BCAST_FLOOD);
5984
5985 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast);
5986 if (err)
5987 goto out;
5988 }
5989
5990 out:
5991 mv88e6xxx_reg_unlock(chip);
5992
5993 return err;
5994 }
5995
mv88e6xxx_lag_can_offload(struct dsa_switch * ds,struct net_device * lag,struct netdev_lag_upper_info * info)5996 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds,
5997 struct net_device *lag,
5998 struct netdev_lag_upper_info *info)
5999 {
6000 struct mv88e6xxx_chip *chip = ds->priv;
6001 struct dsa_port *dp;
6002 int id, members = 0;
6003
6004 if (!mv88e6xxx_has_lag(chip))
6005 return false;
6006
6007 id = dsa_lag_id(ds->dst, lag);
6008 if (id < 0 || id >= ds->num_lag_ids)
6009 return false;
6010
6011 dsa_lag_foreach_port(dp, ds->dst, lag)
6012 /* Includes the port joining the LAG */
6013 members++;
6014
6015 if (members > 8)
6016 return false;
6017
6018 /* We could potentially relax this to include active
6019 * backup in the future.
6020 */
6021 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
6022 return false;
6023
6024 /* Ideally we would also validate that the hash type matches
6025 * the hardware. Alas, this is always set to unknown on team
6026 * interfaces.
6027 */
6028 return true;
6029 }
6030
mv88e6xxx_lag_sync_map(struct dsa_switch * ds,struct net_device * lag)6031 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct net_device *lag)
6032 {
6033 struct mv88e6xxx_chip *chip = ds->priv;
6034 struct dsa_port *dp;
6035 u16 map = 0;
6036 int id;
6037
6038 id = dsa_lag_id(ds->dst, lag);
6039
6040 /* Build the map of all ports to distribute flows destined for
6041 * this LAG. This can be either a local user port, or a DSA
6042 * port if the LAG port is on a remote chip.
6043 */
6044 dsa_lag_foreach_port(dp, ds->dst, lag)
6045 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index));
6046
6047 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map);
6048 }
6049
6050 static const u8 mv88e6xxx_lag_mask_table[8][8] = {
6051 /* Row number corresponds to the number of active members in a
6052 * LAG. Each column states which of the eight hash buckets are
6053 * mapped to the column:th port in the LAG.
6054 *
6055 * Example: In a LAG with three active ports, the second port
6056 * ([2][1]) would be selected for traffic mapped to buckets
6057 * 3,4,5 (0x38).
6058 */
6059 { 0xff, 0, 0, 0, 0, 0, 0, 0 },
6060 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 },
6061 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 },
6062 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 },
6063 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 },
6064 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 },
6065 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 },
6066 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 },
6067 };
6068
mv88e6xxx_lag_set_port_mask(u16 * mask,int port,int num_tx,int nth)6069 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port,
6070 int num_tx, int nth)
6071 {
6072 u8 active = 0;
6073 int i;
6074
6075 num_tx = num_tx <= 8 ? num_tx : 8;
6076 if (nth < num_tx)
6077 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth];
6078
6079 for (i = 0; i < 8; i++) {
6080 if (BIT(i) & active)
6081 mask[i] |= BIT(port);
6082 }
6083 }
6084
mv88e6xxx_lag_sync_masks(struct dsa_switch * ds)6085 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds)
6086 {
6087 struct mv88e6xxx_chip *chip = ds->priv;
6088 unsigned int id, num_tx;
6089 struct net_device *lag;
6090 struct dsa_port *dp;
6091 int i, err, nth;
6092 u16 mask[8];
6093 u16 ivec;
6094
6095 /* Assume no port is a member of any LAG. */
6096 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1;
6097
6098 /* Disable all masks for ports that _are_ members of a LAG. */
6099 list_for_each_entry(dp, &ds->dst->ports, list) {
6100 if (!dp->lag_dev || dp->ds != ds)
6101 continue;
6102
6103 ivec &= ~BIT(dp->index);
6104 }
6105
6106 for (i = 0; i < 8; i++)
6107 mask[i] = ivec;
6108
6109 /* Enable the correct subset of masks for all LAG ports that
6110 * are in the Tx set.
6111 */
6112 dsa_lags_foreach_id(id, ds->dst) {
6113 lag = dsa_lag_dev(ds->dst, id);
6114 if (!lag)
6115 continue;
6116
6117 num_tx = 0;
6118 dsa_lag_foreach_port(dp, ds->dst, lag) {
6119 if (dp->lag_tx_enabled)
6120 num_tx++;
6121 }
6122
6123 if (!num_tx)
6124 continue;
6125
6126 nth = 0;
6127 dsa_lag_foreach_port(dp, ds->dst, lag) {
6128 if (!dp->lag_tx_enabled)
6129 continue;
6130
6131 if (dp->ds == ds)
6132 mv88e6xxx_lag_set_port_mask(mask, dp->index,
6133 num_tx, nth);
6134
6135 nth++;
6136 }
6137 }
6138
6139 for (i = 0; i < 8; i++) {
6140 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]);
6141 if (err)
6142 return err;
6143 }
6144
6145 return 0;
6146 }
6147
mv88e6xxx_lag_sync_masks_map(struct dsa_switch * ds,struct net_device * lag)6148 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds,
6149 struct net_device *lag)
6150 {
6151 int err;
6152
6153 err = mv88e6xxx_lag_sync_masks(ds);
6154
6155 if (!err)
6156 err = mv88e6xxx_lag_sync_map(ds, lag);
6157
6158 return err;
6159 }
6160
mv88e6xxx_port_lag_change(struct dsa_switch * ds,int port)6161 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port)
6162 {
6163 struct mv88e6xxx_chip *chip = ds->priv;
6164 int err;
6165
6166 mv88e6xxx_reg_lock(chip);
6167 err = mv88e6xxx_lag_sync_masks(ds);
6168 mv88e6xxx_reg_unlock(chip);
6169 return err;
6170 }
6171
mv88e6xxx_port_lag_join(struct dsa_switch * ds,int port,struct net_device * lag,struct netdev_lag_upper_info * info)6172 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port,
6173 struct net_device *lag,
6174 struct netdev_lag_upper_info *info)
6175 {
6176 struct mv88e6xxx_chip *chip = ds->priv;
6177 int err, id;
6178
6179 if (!mv88e6xxx_lag_can_offload(ds, lag, info))
6180 return -EOPNOTSUPP;
6181
6182 id = dsa_lag_id(ds->dst, lag);
6183
6184 mv88e6xxx_reg_lock(chip);
6185
6186 err = mv88e6xxx_port_set_trunk(chip, port, true, id);
6187 if (err)
6188 goto err_unlock;
6189
6190 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6191 if (err)
6192 goto err_clear_trunk;
6193
6194 mv88e6xxx_reg_unlock(chip);
6195 return 0;
6196
6197 err_clear_trunk:
6198 mv88e6xxx_port_set_trunk(chip, port, false, 0);
6199 err_unlock:
6200 mv88e6xxx_reg_unlock(chip);
6201 return err;
6202 }
6203
mv88e6xxx_port_lag_leave(struct dsa_switch * ds,int port,struct net_device * lag)6204 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port,
6205 struct net_device *lag)
6206 {
6207 struct mv88e6xxx_chip *chip = ds->priv;
6208 int err_sync, err_trunk;
6209
6210 mv88e6xxx_reg_lock(chip);
6211 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6212 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0);
6213 mv88e6xxx_reg_unlock(chip);
6214 return err_sync ? : err_trunk;
6215 }
6216
mv88e6xxx_crosschip_lag_change(struct dsa_switch * ds,int sw_index,int port)6217 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index,
6218 int port)
6219 {
6220 struct mv88e6xxx_chip *chip = ds->priv;
6221 int err;
6222
6223 mv88e6xxx_reg_lock(chip);
6224 err = mv88e6xxx_lag_sync_masks(ds);
6225 mv88e6xxx_reg_unlock(chip);
6226 return err;
6227 }
6228
mv88e6xxx_crosschip_lag_join(struct dsa_switch * ds,int sw_index,int port,struct net_device * lag,struct netdev_lag_upper_info * info)6229 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index,
6230 int port, struct net_device *lag,
6231 struct netdev_lag_upper_info *info)
6232 {
6233 struct mv88e6xxx_chip *chip = ds->priv;
6234 int err;
6235
6236 if (!mv88e6xxx_lag_can_offload(ds, lag, info))
6237 return -EOPNOTSUPP;
6238
6239 mv88e6xxx_reg_lock(chip);
6240
6241 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6242 if (err)
6243 goto unlock;
6244
6245 err = mv88e6xxx_pvt_map(chip, sw_index, port);
6246
6247 unlock:
6248 mv88e6xxx_reg_unlock(chip);
6249 return err;
6250 }
6251
mv88e6xxx_crosschip_lag_leave(struct dsa_switch * ds,int sw_index,int port,struct net_device * lag)6252 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index,
6253 int port, struct net_device *lag)
6254 {
6255 struct mv88e6xxx_chip *chip = ds->priv;
6256 int err_sync, err_pvt;
6257
6258 mv88e6xxx_reg_lock(chip);
6259 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6260 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port);
6261 mv88e6xxx_reg_unlock(chip);
6262 return err_sync ? : err_pvt;
6263 }
6264
6265 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
6266 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
6267 .change_tag_protocol = mv88e6xxx_change_tag_protocol,
6268 .setup = mv88e6xxx_setup,
6269 .teardown = mv88e6xxx_teardown,
6270 .port_setup = mv88e6xxx_port_setup,
6271 .port_teardown = mv88e6xxx_port_teardown,
6272 .phylink_validate = mv88e6xxx_validate,
6273 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state,
6274 .phylink_mac_config = mv88e6xxx_mac_config,
6275 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart,
6276 .phylink_mac_link_down = mv88e6xxx_mac_link_down,
6277 .phylink_mac_link_up = mv88e6xxx_mac_link_up,
6278 .get_strings = mv88e6xxx_get_strings,
6279 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
6280 .get_sset_count = mv88e6xxx_get_sset_count,
6281 .port_enable = mv88e6xxx_port_enable,
6282 .port_disable = mv88e6xxx_port_disable,
6283 .port_max_mtu = mv88e6xxx_get_max_mtu,
6284 .port_change_mtu = mv88e6xxx_change_mtu,
6285 .get_mac_eee = mv88e6xxx_get_mac_eee,
6286 .set_mac_eee = mv88e6xxx_set_mac_eee,
6287 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
6288 .get_eeprom = mv88e6xxx_get_eeprom,
6289 .set_eeprom = mv88e6xxx_set_eeprom,
6290 .get_regs_len = mv88e6xxx_get_regs_len,
6291 .get_regs = mv88e6xxx_get_regs,
6292 .get_rxnfc = mv88e6xxx_get_rxnfc,
6293 .set_rxnfc = mv88e6xxx_set_rxnfc,
6294 .set_ageing_time = mv88e6xxx_set_ageing_time,
6295 .port_bridge_join = mv88e6xxx_port_bridge_join,
6296 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
6297 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags,
6298 .port_bridge_flags = mv88e6xxx_port_bridge_flags,
6299 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
6300 .port_fast_age = mv88e6xxx_port_fast_age,
6301 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
6302 .port_vlan_add = mv88e6xxx_port_vlan_add,
6303 .port_vlan_del = mv88e6xxx_port_vlan_del,
6304 .port_fdb_add = mv88e6xxx_port_fdb_add,
6305 .port_fdb_del = mv88e6xxx_port_fdb_del,
6306 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
6307 .port_mdb_add = mv88e6xxx_port_mdb_add,
6308 .port_mdb_del = mv88e6xxx_port_mdb_del,
6309 .port_mirror_add = mv88e6xxx_port_mirror_add,
6310 .port_mirror_del = mv88e6xxx_port_mirror_del,
6311 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
6312 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
6313 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set,
6314 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get,
6315 .port_txtstamp = mv88e6xxx_port_txtstamp,
6316 .port_rxtstamp = mv88e6xxx_port_rxtstamp,
6317 .get_ts_info = mv88e6xxx_get_ts_info,
6318 .devlink_param_get = mv88e6xxx_devlink_param_get,
6319 .devlink_param_set = mv88e6xxx_devlink_param_set,
6320 .devlink_info_get = mv88e6xxx_devlink_info_get,
6321 .port_lag_change = mv88e6xxx_port_lag_change,
6322 .port_lag_join = mv88e6xxx_port_lag_join,
6323 .port_lag_leave = mv88e6xxx_port_lag_leave,
6324 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change,
6325 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join,
6326 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave,
6327 .port_bridge_tx_fwd_offload = mv88e6xxx_bridge_tx_fwd_offload,
6328 .port_bridge_tx_fwd_unoffload = mv88e6xxx_bridge_tx_fwd_unoffload,
6329 };
6330
mv88e6xxx_register_switch(struct mv88e6xxx_chip * chip)6331 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
6332 {
6333 struct device *dev = chip->dev;
6334 struct dsa_switch *ds;
6335
6336 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
6337 if (!ds)
6338 return -ENOMEM;
6339
6340 ds->dev = dev;
6341 ds->num_ports = mv88e6xxx_num_ports(chip);
6342 ds->priv = chip;
6343 ds->dev = dev;
6344 ds->ops = &mv88e6xxx_switch_ops;
6345 ds->ageing_time_min = chip->info->age_time_coeff;
6346 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
6347
6348 /* Some chips support up to 32, but that requires enabling the
6349 * 5-bit port mode, which we do not support. 640k^W16 ought to
6350 * be enough for anyone.
6351 */
6352 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0;
6353
6354 dev_set_drvdata(dev, ds);
6355
6356 return dsa_register_switch(ds);
6357 }
6358
mv88e6xxx_unregister_switch(struct mv88e6xxx_chip * chip)6359 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
6360 {
6361 dsa_unregister_switch(chip->ds);
6362 }
6363
pdata_device_get_match_data(struct device * dev)6364 static const void *pdata_device_get_match_data(struct device *dev)
6365 {
6366 const struct of_device_id *matches = dev->driver->of_match_table;
6367 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
6368
6369 for (; matches->name[0] || matches->type[0] || matches->compatible[0];
6370 matches++) {
6371 if (!strcmp(pdata->compatible, matches->compatible))
6372 return matches->data;
6373 }
6374 return NULL;
6375 }
6376
6377 /* There is no suspend to RAM support at DSA level yet, the switch configuration
6378 * would be lost after a power cycle so prevent it to be suspended.
6379 */
mv88e6xxx_suspend(struct device * dev)6380 static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
6381 {
6382 return -EOPNOTSUPP;
6383 }
6384
mv88e6xxx_resume(struct device * dev)6385 static int __maybe_unused mv88e6xxx_resume(struct device *dev)
6386 {
6387 return 0;
6388 }
6389
6390 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
6391
mv88e6xxx_probe(struct mdio_device * mdiodev)6392 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
6393 {
6394 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
6395 const struct mv88e6xxx_info *compat_info = NULL;
6396 struct device *dev = &mdiodev->dev;
6397 struct device_node *np = dev->of_node;
6398 struct mv88e6xxx_chip *chip;
6399 int port;
6400 int err;
6401
6402 if (!np && !pdata)
6403 return -EINVAL;
6404
6405 if (np)
6406 compat_info = of_device_get_match_data(dev);
6407
6408 if (pdata) {
6409 compat_info = pdata_device_get_match_data(dev);
6410
6411 if (!pdata->netdev)
6412 return -EINVAL;
6413
6414 for (port = 0; port < DSA_MAX_PORTS; port++) {
6415 if (!(pdata->enabled_ports & (1 << port)))
6416 continue;
6417 if (strcmp(pdata->cd.port_names[port], "cpu"))
6418 continue;
6419 pdata->cd.netdev[port] = &pdata->netdev->dev;
6420 break;
6421 }
6422 }
6423
6424 if (!compat_info)
6425 return -EINVAL;
6426
6427 chip = mv88e6xxx_alloc_chip(dev);
6428 if (!chip) {
6429 err = -ENOMEM;
6430 goto out;
6431 }
6432
6433 chip->info = compat_info;
6434
6435 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
6436 if (err)
6437 goto out;
6438
6439 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
6440 if (IS_ERR(chip->reset)) {
6441 err = PTR_ERR(chip->reset);
6442 goto out;
6443 }
6444 if (chip->reset)
6445 usleep_range(10000, 20000);
6446
6447 err = mv88e6xxx_detect(chip);
6448 if (err)
6449 goto out;
6450
6451 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED)
6452 chip->tag_protocol = DSA_TAG_PROTO_EDSA;
6453 else
6454 chip->tag_protocol = DSA_TAG_PROTO_DSA;
6455
6456 mv88e6xxx_phy_init(chip);
6457
6458 if (chip->info->ops->get_eeprom) {
6459 if (np)
6460 of_property_read_u32(np, "eeprom-length",
6461 &chip->eeprom_len);
6462 else
6463 chip->eeprom_len = pdata->eeprom_len;
6464 }
6465
6466 mv88e6xxx_reg_lock(chip);
6467 err = mv88e6xxx_switch_reset(chip);
6468 mv88e6xxx_reg_unlock(chip);
6469 if (err)
6470 goto out;
6471
6472 if (np) {
6473 chip->irq = of_irq_get(np, 0);
6474 if (chip->irq == -EPROBE_DEFER) {
6475 err = chip->irq;
6476 goto out;
6477 }
6478 }
6479
6480 if (pdata)
6481 chip->irq = pdata->irq;
6482
6483 /* Has to be performed before the MDIO bus is created, because
6484 * the PHYs will link their interrupts to these interrupt
6485 * controllers
6486 */
6487 mv88e6xxx_reg_lock(chip);
6488 if (chip->irq > 0)
6489 err = mv88e6xxx_g1_irq_setup(chip);
6490 else
6491 err = mv88e6xxx_irq_poll_setup(chip);
6492 mv88e6xxx_reg_unlock(chip);
6493
6494 if (err)
6495 goto out;
6496
6497 if (chip->info->g2_irqs > 0) {
6498 err = mv88e6xxx_g2_irq_setup(chip);
6499 if (err)
6500 goto out_g1_irq;
6501 }
6502
6503 err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
6504 if (err)
6505 goto out_g2_irq;
6506
6507 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
6508 if (err)
6509 goto out_g1_atu_prob_irq;
6510
6511 err = mv88e6xxx_mdios_register(chip, np);
6512 if (err)
6513 goto out_g1_vtu_prob_irq;
6514
6515 err = mv88e6xxx_register_switch(chip);
6516 if (err)
6517 goto out_mdio;
6518
6519 return 0;
6520
6521 out_mdio:
6522 mv88e6xxx_mdios_unregister(chip);
6523 out_g1_vtu_prob_irq:
6524 mv88e6xxx_g1_vtu_prob_irq_free(chip);
6525 out_g1_atu_prob_irq:
6526 mv88e6xxx_g1_atu_prob_irq_free(chip);
6527 out_g2_irq:
6528 if (chip->info->g2_irqs > 0)
6529 mv88e6xxx_g2_irq_free(chip);
6530 out_g1_irq:
6531 if (chip->irq > 0)
6532 mv88e6xxx_g1_irq_free(chip);
6533 else
6534 mv88e6xxx_irq_poll_free(chip);
6535 out:
6536 if (pdata)
6537 dev_put(pdata->netdev);
6538
6539 return err;
6540 }
6541
mv88e6xxx_remove(struct mdio_device * mdiodev)6542 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
6543 {
6544 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
6545 struct mv88e6xxx_chip *chip;
6546
6547 if (!ds)
6548 return;
6549
6550 chip = ds->priv;
6551
6552 if (chip->info->ptp_support) {
6553 mv88e6xxx_hwtstamp_free(chip);
6554 mv88e6xxx_ptp_free(chip);
6555 }
6556
6557 mv88e6xxx_phy_destroy(chip);
6558 mv88e6xxx_unregister_switch(chip);
6559 mv88e6xxx_mdios_unregister(chip);
6560
6561 mv88e6xxx_g1_vtu_prob_irq_free(chip);
6562 mv88e6xxx_g1_atu_prob_irq_free(chip);
6563
6564 if (chip->info->g2_irqs > 0)
6565 mv88e6xxx_g2_irq_free(chip);
6566
6567 if (chip->irq > 0)
6568 mv88e6xxx_g1_irq_free(chip);
6569 else
6570 mv88e6xxx_irq_poll_free(chip);
6571
6572 dev_set_drvdata(&mdiodev->dev, NULL);
6573 }
6574
mv88e6xxx_shutdown(struct mdio_device * mdiodev)6575 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev)
6576 {
6577 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
6578
6579 if (!ds)
6580 return;
6581
6582 dsa_switch_shutdown(ds);
6583
6584 dev_set_drvdata(&mdiodev->dev, NULL);
6585 }
6586
6587 static const struct of_device_id mv88e6xxx_of_match[] = {
6588 {
6589 .compatible = "marvell,mv88e6085",
6590 .data = &mv88e6xxx_table[MV88E6085],
6591 },
6592 {
6593 .compatible = "marvell,mv88e6190",
6594 .data = &mv88e6xxx_table[MV88E6190],
6595 },
6596 {
6597 .compatible = "marvell,mv88e6250",
6598 .data = &mv88e6xxx_table[MV88E6250],
6599 },
6600 { /* sentinel */ },
6601 };
6602
6603 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
6604
6605 static struct mdio_driver mv88e6xxx_driver = {
6606 .probe = mv88e6xxx_probe,
6607 .remove = mv88e6xxx_remove,
6608 .shutdown = mv88e6xxx_shutdown,
6609 .mdiodrv.driver = {
6610 .name = "mv88e6085",
6611 .of_match_table = mv88e6xxx_of_match,
6612 .pm = &mv88e6xxx_pm_ops,
6613 },
6614 };
6615
6616 mdio_module_driver(mv88e6xxx_driver);
6617
6618 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
6619 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
6620 MODULE_LICENSE("GPL");
6621