1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH 3 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com> 4 */ 5 #ifndef _SJA1105_H 6 #define _SJA1105_H 7 8 #include <linux/ptp_clock_kernel.h> 9 #include <linux/timecounter.h> 10 #include <linux/dsa/sja1105.h> 11 #include <linux/dsa/8021q.h> 12 #include <net/dsa.h> 13 #include <linux/mutex.h> 14 #include "sja1105_static_config.h" 15 16 #define SJA1105ET_FDB_BIN_SIZE 4 17 /* The hardware value is in multiples of 10 ms. 18 * The passed parameter is in multiples of 1 ms. 19 */ 20 #define SJA1105_AGEING_TIME_MS(ms) ((ms) / 10) 21 #define SJA1105_NUM_L2_POLICERS SJA1110_MAX_L2_POLICING_COUNT 22 23 typedef enum { 24 SPI_READ = 0, 25 SPI_WRITE = 1, 26 } sja1105_spi_rw_mode_t; 27 28 #include "sja1105_tas.h" 29 #include "sja1105_ptp.h" 30 31 enum sja1105_stats_area { 32 MAC, 33 HL1, 34 HL2, 35 ETHER, 36 __MAX_SJA1105_STATS_AREA, 37 }; 38 39 /* Keeps the different addresses between E/T and P/Q/R/S */ 40 struct sja1105_regs { 41 u64 device_id; 42 u64 prod_id; 43 u64 status; 44 u64 port_control; 45 u64 rgu; 46 u64 vl_status; 47 u64 config; 48 u64 rmii_pll1; 49 u64 ptppinst; 50 u64 ptppindur; 51 u64 ptp_control; 52 u64 ptpclkval; 53 u64 ptpclkrate; 54 u64 ptpclkcorp; 55 u64 ptpsyncts; 56 u64 ptpschtm; 57 u64 ptpegr_ts[SJA1105_MAX_NUM_PORTS]; 58 u64 pad_mii_tx[SJA1105_MAX_NUM_PORTS]; 59 u64 pad_mii_rx[SJA1105_MAX_NUM_PORTS]; 60 u64 pad_mii_id[SJA1105_MAX_NUM_PORTS]; 61 u64 cgu_idiv[SJA1105_MAX_NUM_PORTS]; 62 u64 mii_tx_clk[SJA1105_MAX_NUM_PORTS]; 63 u64 mii_rx_clk[SJA1105_MAX_NUM_PORTS]; 64 u64 mii_ext_tx_clk[SJA1105_MAX_NUM_PORTS]; 65 u64 mii_ext_rx_clk[SJA1105_MAX_NUM_PORTS]; 66 u64 rgmii_tx_clk[SJA1105_MAX_NUM_PORTS]; 67 u64 rmii_ref_clk[SJA1105_MAX_NUM_PORTS]; 68 u64 rmii_ext_tx_clk[SJA1105_MAX_NUM_PORTS]; 69 u64 stats[__MAX_SJA1105_STATS_AREA][SJA1105_MAX_NUM_PORTS]; 70 u64 mdio_100base_tx; 71 u64 mdio_100base_t1; 72 u64 pcs_base[SJA1105_MAX_NUM_PORTS]; 73 }; 74 75 struct sja1105_mdio_private { 76 struct sja1105_private *priv; 77 }; 78 79 enum { 80 SJA1105_SPEED_AUTO, 81 SJA1105_SPEED_10MBPS, 82 SJA1105_SPEED_100MBPS, 83 SJA1105_SPEED_1000MBPS, 84 SJA1105_SPEED_2500MBPS, 85 SJA1105_SPEED_MAX, 86 }; 87 88 enum sja1105_internal_phy_t { 89 SJA1105_NO_PHY = 0, 90 SJA1105_PHY_BASE_TX, 91 SJA1105_PHY_BASE_T1, 92 }; 93 94 struct sja1105_info { 95 u64 device_id; 96 /* Needed for distinction between P and R, and between Q and S 97 * (since the parts with/without SGMII share the same 98 * switch core and device_id) 99 */ 100 u64 part_no; 101 /* E/T and P/Q/R/S have partial timestamps of different sizes. 102 * They must be reconstructed on both families anyway to get the full 103 * 64-bit values back. 104 */ 105 int ptp_ts_bits; 106 /* Also SPI commands are of different sizes to retrieve 107 * the egress timestamps. 108 */ 109 int ptpegr_ts_bytes; 110 int num_cbs_shapers; 111 int max_frame_mem; 112 int num_ports; 113 bool multiple_cascade_ports; 114 /* Every {port, TXQ} has its own CBS shaper */ 115 bool fixed_cbs_mapping; 116 enum dsa_tag_protocol tag_proto; 117 const struct sja1105_dynamic_table_ops *dyn_ops; 118 const struct sja1105_table_ops *static_ops; 119 const struct sja1105_regs *regs; 120 bool can_limit_mcast_flood; 121 int (*reset_cmd)(struct dsa_switch *ds); 122 int (*setup_rgmii_delay)(const void *ctx, int port); 123 /* Prototypes from include/net/dsa.h */ 124 int (*fdb_add_cmd)(struct dsa_switch *ds, int port, 125 const unsigned char *addr, u16 vid); 126 int (*fdb_del_cmd)(struct dsa_switch *ds, int port, 127 const unsigned char *addr, u16 vid); 128 void (*ptp_cmd_packing)(u8 *buf, struct sja1105_ptp_cmd *cmd, 129 enum packing_op op); 130 bool (*rxtstamp)(struct dsa_switch *ds, int port, struct sk_buff *skb); 131 void (*txtstamp)(struct dsa_switch *ds, int port, struct sk_buff *skb); 132 int (*clocking_setup)(struct sja1105_private *priv); 133 int (*pcs_mdio_read)(struct mii_bus *bus, int phy, int reg); 134 int (*pcs_mdio_write)(struct mii_bus *bus, int phy, int reg, u16 val); 135 int (*disable_microcontroller)(struct sja1105_private *priv); 136 const char *name; 137 bool supports_mii[SJA1105_MAX_NUM_PORTS]; 138 bool supports_rmii[SJA1105_MAX_NUM_PORTS]; 139 bool supports_rgmii[SJA1105_MAX_NUM_PORTS]; 140 bool supports_sgmii[SJA1105_MAX_NUM_PORTS]; 141 bool supports_2500basex[SJA1105_MAX_NUM_PORTS]; 142 enum sja1105_internal_phy_t internal_phy[SJA1105_MAX_NUM_PORTS]; 143 const u64 port_speed[SJA1105_SPEED_MAX]; 144 }; 145 146 enum sja1105_key_type { 147 SJA1105_KEY_BCAST, 148 SJA1105_KEY_TC, 149 SJA1105_KEY_VLAN_UNAWARE_VL, 150 SJA1105_KEY_VLAN_AWARE_VL, 151 }; 152 153 struct sja1105_key { 154 enum sja1105_key_type type; 155 156 union { 157 /* SJA1105_KEY_TC */ 158 struct { 159 int pcp; 160 } tc; 161 162 /* SJA1105_KEY_VLAN_UNAWARE_VL */ 163 /* SJA1105_KEY_VLAN_AWARE_VL */ 164 struct { 165 u64 dmac; 166 u16 vid; 167 u16 pcp; 168 } vl; 169 }; 170 }; 171 172 enum sja1105_rule_type { 173 SJA1105_RULE_BCAST_POLICER, 174 SJA1105_RULE_TC_POLICER, 175 SJA1105_RULE_VL, 176 }; 177 178 enum sja1105_vl_type { 179 SJA1105_VL_NONCRITICAL, 180 SJA1105_VL_RATE_CONSTRAINED, 181 SJA1105_VL_TIME_TRIGGERED, 182 }; 183 184 struct sja1105_rule { 185 struct list_head list; 186 unsigned long cookie; 187 unsigned long port_mask; 188 struct sja1105_key key; 189 enum sja1105_rule_type type; 190 191 /* Action */ 192 union { 193 /* SJA1105_RULE_BCAST_POLICER */ 194 struct { 195 int sharindx; 196 } bcast_pol; 197 198 /* SJA1105_RULE_TC_POLICER */ 199 struct { 200 int sharindx; 201 } tc_pol; 202 203 /* SJA1105_RULE_VL */ 204 struct { 205 enum sja1105_vl_type type; 206 unsigned long destports; 207 int sharindx; 208 int maxlen; 209 int ipv; 210 u64 base_time; 211 u64 cycle_time; 212 int num_entries; 213 struct action_gate_entry *entries; 214 struct flow_stats stats; 215 } vl; 216 }; 217 }; 218 219 struct sja1105_flow_block { 220 struct list_head rules; 221 bool l2_policer_used[SJA1105_NUM_L2_POLICERS]; 222 int num_virtual_links; 223 }; 224 225 struct sja1105_private { 226 struct sja1105_static_config static_config; 227 bool rgmii_rx_delay[SJA1105_MAX_NUM_PORTS]; 228 bool rgmii_tx_delay[SJA1105_MAX_NUM_PORTS]; 229 phy_interface_t phy_mode[SJA1105_MAX_NUM_PORTS]; 230 bool fixed_link[SJA1105_MAX_NUM_PORTS]; 231 bool vlan_aware; 232 unsigned long ucast_egress_floods; 233 unsigned long bcast_egress_floods; 234 const struct sja1105_info *info; 235 size_t max_xfer_len; 236 struct gpio_desc *reset_gpio; 237 struct spi_device *spidev; 238 struct dsa_switch *ds; 239 u16 bridge_pvid[SJA1105_MAX_NUM_PORTS]; 240 u16 tag_8021q_pvid[SJA1105_MAX_NUM_PORTS]; 241 struct sja1105_flow_block flow_block; 242 struct sja1105_port ports[SJA1105_MAX_NUM_PORTS]; 243 /* Serializes transmission of management frames so that 244 * the switch doesn't confuse them with one another. 245 */ 246 struct mutex mgmt_lock; 247 struct devlink_region **regions; 248 struct sja1105_cbs_entry *cbs; 249 struct mii_bus *mdio_base_t1; 250 struct mii_bus *mdio_base_tx; 251 struct mii_bus *mdio_pcs; 252 struct dw_xpcs *xpcs[SJA1105_MAX_NUM_PORTS]; 253 struct sja1105_tagger_data tagger_data; 254 struct sja1105_ptp_data ptp_data; 255 struct sja1105_tas_data tas_data; 256 }; 257 258 #include "sja1105_dynamic_config.h" 259 260 struct sja1105_spi_message { 261 u64 access; 262 u64 read_count; 263 u64 address; 264 }; 265 266 /* From sja1105_main.c */ 267 enum sja1105_reset_reason { 268 SJA1105_VLAN_FILTERING = 0, 269 SJA1105_RX_HWTSTAMPING, 270 SJA1105_AGEING_TIME, 271 SJA1105_SCHEDULING, 272 SJA1105_BEST_EFFORT_POLICING, 273 SJA1105_VIRTUAL_LINKS, 274 }; 275 276 int sja1105_static_config_reload(struct sja1105_private *priv, 277 enum sja1105_reset_reason reason); 278 int sja1105_vlan_filtering(struct dsa_switch *ds, int port, bool enabled, 279 struct netlink_ext_ack *extack); 280 void sja1105_frame_memory_partitioning(struct sja1105_private *priv); 281 282 /* From sja1105_mdio.c */ 283 int sja1105_mdiobus_register(struct dsa_switch *ds); 284 void sja1105_mdiobus_unregister(struct dsa_switch *ds); 285 int sja1105_pcs_mdio_read(struct mii_bus *bus, int phy, int reg); 286 int sja1105_pcs_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val); 287 int sja1110_pcs_mdio_read(struct mii_bus *bus, int phy, int reg); 288 int sja1110_pcs_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val); 289 290 /* From sja1105_devlink.c */ 291 int sja1105_devlink_setup(struct dsa_switch *ds); 292 void sja1105_devlink_teardown(struct dsa_switch *ds); 293 int sja1105_devlink_info_get(struct dsa_switch *ds, 294 struct devlink_info_req *req, 295 struct netlink_ext_ack *extack); 296 297 /* From sja1105_spi.c */ 298 int sja1105_xfer_buf(const struct sja1105_private *priv, 299 sja1105_spi_rw_mode_t rw, u64 reg_addr, 300 u8 *buf, size_t len); 301 int sja1105_xfer_u32(const struct sja1105_private *priv, 302 sja1105_spi_rw_mode_t rw, u64 reg_addr, u32 *value, 303 struct ptp_system_timestamp *ptp_sts); 304 int sja1105_xfer_u64(const struct sja1105_private *priv, 305 sja1105_spi_rw_mode_t rw, u64 reg_addr, u64 *value, 306 struct ptp_system_timestamp *ptp_sts); 307 int static_config_buf_prepare_for_upload(struct sja1105_private *priv, 308 void *config_buf, int buf_len); 309 int sja1105_static_config_upload(struct sja1105_private *priv); 310 int sja1105_inhibit_tx(const struct sja1105_private *priv, 311 unsigned long port_bitmap, bool tx_inhibited); 312 313 extern const struct sja1105_info sja1105e_info; 314 extern const struct sja1105_info sja1105t_info; 315 extern const struct sja1105_info sja1105p_info; 316 extern const struct sja1105_info sja1105q_info; 317 extern const struct sja1105_info sja1105r_info; 318 extern const struct sja1105_info sja1105s_info; 319 extern const struct sja1105_info sja1110a_info; 320 extern const struct sja1105_info sja1110b_info; 321 extern const struct sja1105_info sja1110c_info; 322 extern const struct sja1105_info sja1110d_info; 323 324 /* From sja1105_clocking.c */ 325 326 typedef enum { 327 XMII_MAC = 0, 328 XMII_PHY = 1, 329 } sja1105_mii_role_t; 330 331 typedef enum { 332 XMII_MODE_MII = 0, 333 XMII_MODE_RMII = 1, 334 XMII_MODE_RGMII = 2, 335 XMII_MODE_SGMII = 3, 336 } sja1105_phy_interface_t; 337 338 int sja1105pqrs_setup_rgmii_delay(const void *ctx, int port); 339 int sja1110_setup_rgmii_delay(const void *ctx, int port); 340 int sja1105_clocking_setup_port(struct sja1105_private *priv, int port); 341 int sja1105_clocking_setup(struct sja1105_private *priv); 342 int sja1110_disable_microcontroller(struct sja1105_private *priv); 343 344 /* From sja1105_ethtool.c */ 345 void sja1105_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data); 346 void sja1105_get_strings(struct dsa_switch *ds, int port, 347 u32 stringset, u8 *data); 348 int sja1105_get_sset_count(struct dsa_switch *ds, int port, int sset); 349 350 /* From sja1105_dynamic_config.c */ 351 int sja1105_dynamic_config_read(struct sja1105_private *priv, 352 enum sja1105_blk_idx blk_idx, 353 int index, void *entry); 354 int sja1105_dynamic_config_write(struct sja1105_private *priv, 355 enum sja1105_blk_idx blk_idx, 356 int index, void *entry, bool keep); 357 358 enum sja1105_iotag { 359 SJA1105_C_TAG = 0, /* Inner VLAN header */ 360 SJA1105_S_TAG = 1, /* Outer VLAN header */ 361 }; 362 363 enum sja1110_vlan_type { 364 SJA1110_VLAN_INVALID = 0, 365 SJA1110_VLAN_C_TAG = 1, /* Single inner VLAN tag */ 366 SJA1110_VLAN_S_TAG = 2, /* Single outer VLAN tag */ 367 SJA1110_VLAN_D_TAG = 3, /* Double tagged, use outer tag for lookup */ 368 }; 369 370 enum sja1110_shaper_type { 371 SJA1110_LEAKY_BUCKET_SHAPER = 0, 372 SJA1110_CBS_SHAPER = 1, 373 }; 374 375 u8 sja1105et_fdb_hash(struct sja1105_private *priv, const u8 *addr, u16 vid); 376 int sja1105et_fdb_add(struct dsa_switch *ds, int port, 377 const unsigned char *addr, u16 vid); 378 int sja1105et_fdb_del(struct dsa_switch *ds, int port, 379 const unsigned char *addr, u16 vid); 380 int sja1105pqrs_fdb_add(struct dsa_switch *ds, int port, 381 const unsigned char *addr, u16 vid); 382 int sja1105pqrs_fdb_del(struct dsa_switch *ds, int port, 383 const unsigned char *addr, u16 vid); 384 385 /* From sja1105_flower.c */ 386 int sja1105_cls_flower_del(struct dsa_switch *ds, int port, 387 struct flow_cls_offload *cls, bool ingress); 388 int sja1105_cls_flower_add(struct dsa_switch *ds, int port, 389 struct flow_cls_offload *cls, bool ingress); 390 int sja1105_cls_flower_stats(struct dsa_switch *ds, int port, 391 struct flow_cls_offload *cls, bool ingress); 392 void sja1105_flower_setup(struct dsa_switch *ds); 393 void sja1105_flower_teardown(struct dsa_switch *ds); 394 struct sja1105_rule *sja1105_rule_find(struct sja1105_private *priv, 395 unsigned long cookie); 396 397 #endif 398