1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
2 /* Copyright (c) 2016-2018 Mellanox Technologies. All rights reserved */
3
4 #include <linux/err.h>
5 #include <linux/i2c.h>
6 #include <linux/init.h>
7 #include <linux/jiffies.h>
8 #include <linux/kernel.h>
9 #include <linux/mutex.h>
10 #include <linux/module.h>
11 #include <linux/mod_devicetable.h>
12 #include <linux/slab.h>
13
14 #include "cmd.h"
15 #include "core.h"
16 #include "i2c.h"
17 #include "resources.h"
18
19 #define MLXSW_I2C_CIR2_BASE 0x72000
20 #define MLXSW_I2C_CIR_STATUS_OFF 0x18
21 #define MLXSW_I2C_CIR2_OFF_STATUS (MLXSW_I2C_CIR2_BASE + \
22 MLXSW_I2C_CIR_STATUS_OFF)
23 #define MLXSW_I2C_OPMOD_SHIFT 12
24 #define MLXSW_I2C_EVENT_BIT_SHIFT 22
25 #define MLXSW_I2C_GO_BIT_SHIFT 23
26 #define MLXSW_I2C_CIR_CTRL_STATUS_SHIFT 24
27 #define MLXSW_I2C_EVENT_BIT BIT(MLXSW_I2C_EVENT_BIT_SHIFT)
28 #define MLXSW_I2C_GO_BIT BIT(MLXSW_I2C_GO_BIT_SHIFT)
29 #define MLXSW_I2C_GO_OPMODE BIT(MLXSW_I2C_OPMOD_SHIFT)
30 #define MLXSW_I2C_SET_IMM_CMD (MLXSW_I2C_GO_OPMODE | \
31 MLXSW_CMD_OPCODE_QUERY_FW)
32 #define MLXSW_I2C_PUSH_IMM_CMD (MLXSW_I2C_GO_BIT | \
33 MLXSW_I2C_SET_IMM_CMD)
34 #define MLXSW_I2C_SET_CMD (MLXSW_CMD_OPCODE_ACCESS_REG)
35 #define MLXSW_I2C_PUSH_CMD (MLXSW_I2C_GO_BIT | MLXSW_I2C_SET_CMD)
36 #define MLXSW_I2C_TLV_HDR_SIZE 0x10
37 #define MLXSW_I2C_ADDR_WIDTH 4
38 #define MLXSW_I2C_PUSH_CMD_SIZE (MLXSW_I2C_ADDR_WIDTH + 4)
39 #define MLXSW_I2C_SET_EVENT_CMD (MLXSW_I2C_EVENT_BIT)
40 #define MLXSW_I2C_PUSH_EVENT_CMD (MLXSW_I2C_GO_BIT | \
41 MLXSW_I2C_SET_EVENT_CMD)
42 #define MLXSW_I2C_READ_SEMA_SIZE 4
43 #define MLXSW_I2C_PREP_SIZE (MLXSW_I2C_ADDR_WIDTH + 28)
44 #define MLXSW_I2C_MBOX_SIZE 20
45 #define MLXSW_I2C_MBOX_OUT_PARAM_OFF 12
46 #define MLXSW_I2C_MBOX_OFFSET_BITS 20
47 #define MLXSW_I2C_MBOX_SIZE_BITS 12
48 #define MLXSW_I2C_ADDR_BUF_SIZE 4
49 #define MLXSW_I2C_BLK_DEF 32
50 #define MLXSW_I2C_BLK_MAX 100
51 #define MLXSW_I2C_RETRY 5
52 #define MLXSW_I2C_TIMEOUT_MSECS 5000
53 #define MLXSW_I2C_MAX_DATA_SIZE 256
54
55 /**
56 * struct mlxsw_i2c - device private data:
57 * @cmd: command attributes;
58 * @cmd.mb_size_in: input mailbox size;
59 * @cmd.mb_off_in: input mailbox offset in register space;
60 * @cmd.mb_size_out: output mailbox size;
61 * @cmd.mb_off_out: output mailbox offset in register space;
62 * @cmd.lock: command execution lock;
63 * @dev: I2C device;
64 * @core: switch core pointer;
65 * @bus_info: bus info block;
66 * @block_size: maximum block size allowed to pass to under layer;
67 */
68 struct mlxsw_i2c {
69 struct {
70 u32 mb_size_in;
71 u32 mb_off_in;
72 u32 mb_size_out;
73 u32 mb_off_out;
74 struct mutex lock;
75 } cmd;
76 struct device *dev;
77 struct mlxsw_core *core;
78 struct mlxsw_bus_info bus_info;
79 u16 block_size;
80 };
81
82 #define MLXSW_I2C_READ_MSG(_client, _addr_buf, _buf, _len) { \
83 { .addr = (_client)->addr, \
84 .buf = (_addr_buf), \
85 .len = MLXSW_I2C_ADDR_BUF_SIZE, \
86 .flags = 0 }, \
87 { .addr = (_client)->addr, \
88 .buf = (_buf), \
89 .len = (_len), \
90 .flags = I2C_M_RD } }
91
92 #define MLXSW_I2C_WRITE_MSG(_client, _buf, _len) \
93 { .addr = (_client)->addr, \
94 .buf = (u8 *)(_buf), \
95 .len = (_len), \
96 .flags = 0 }
97
98 /* Routine converts in and out mail boxes offset and size. */
99 static inline void
mlxsw_i2c_convert_mbox(struct mlxsw_i2c * mlxsw_i2c,u8 * buf)100 mlxsw_i2c_convert_mbox(struct mlxsw_i2c *mlxsw_i2c, u8 *buf)
101 {
102 u32 tmp;
103
104 /* Local in/out mailboxes: 20 bits for offset, 12 for size */
105 tmp = be32_to_cpup((__be32 *) buf);
106 mlxsw_i2c->cmd.mb_off_in = tmp &
107 GENMASK(MLXSW_I2C_MBOX_OFFSET_BITS - 1, 0);
108 mlxsw_i2c->cmd.mb_size_in = (tmp & GENMASK(31,
109 MLXSW_I2C_MBOX_OFFSET_BITS)) >>
110 MLXSW_I2C_MBOX_OFFSET_BITS;
111
112 tmp = be32_to_cpup((__be32 *) (buf + MLXSW_I2C_ADDR_WIDTH));
113 mlxsw_i2c->cmd.mb_off_out = tmp &
114 GENMASK(MLXSW_I2C_MBOX_OFFSET_BITS - 1, 0);
115 mlxsw_i2c->cmd.mb_size_out = (tmp & GENMASK(31,
116 MLXSW_I2C_MBOX_OFFSET_BITS)) >>
117 MLXSW_I2C_MBOX_OFFSET_BITS;
118 }
119
120 /* Routine obtains register size from mail box buffer. */
mlxsw_i2c_get_reg_size(u8 * in_mbox)121 static inline int mlxsw_i2c_get_reg_size(u8 *in_mbox)
122 {
123 u16 tmp = be16_to_cpup((__be16 *) (in_mbox + MLXSW_I2C_TLV_HDR_SIZE));
124
125 return (tmp & 0x7ff) * 4 + MLXSW_I2C_TLV_HDR_SIZE;
126 }
127
128 /* Routine sets I2C device internal offset in the transaction buffer. */
mlxsw_i2c_set_slave_addr(u8 * buf,u32 off)129 static inline void mlxsw_i2c_set_slave_addr(u8 *buf, u32 off)
130 {
131 __be32 *val = (__be32 *) buf;
132
133 *val = htonl(off);
134 }
135
136 /* Routine waits until go bit is cleared. */
mlxsw_i2c_wait_go_bit(struct i2c_client * client,struct mlxsw_i2c * mlxsw_i2c,u8 * p_status)137 static int mlxsw_i2c_wait_go_bit(struct i2c_client *client,
138 struct mlxsw_i2c *mlxsw_i2c, u8 *p_status)
139 {
140 u8 addr_buf[MLXSW_I2C_ADDR_BUF_SIZE];
141 u8 buf[MLXSW_I2C_READ_SEMA_SIZE];
142 int len = MLXSW_I2C_READ_SEMA_SIZE;
143 struct i2c_msg read_sema[] =
144 MLXSW_I2C_READ_MSG(client, addr_buf, buf, len);
145 bool wait_done = false;
146 unsigned long end;
147 int i = 0, err;
148
149 mlxsw_i2c_set_slave_addr(addr_buf, MLXSW_I2C_CIR2_OFF_STATUS);
150
151 end = jiffies + msecs_to_jiffies(MLXSW_I2C_TIMEOUT_MSECS);
152 do {
153 u32 ctrl;
154
155 err = i2c_transfer(client->adapter, read_sema,
156 ARRAY_SIZE(read_sema));
157
158 ctrl = be32_to_cpu(*(__be32 *) buf);
159 if (err == ARRAY_SIZE(read_sema)) {
160 if (!(ctrl & MLXSW_I2C_GO_BIT)) {
161 wait_done = true;
162 *p_status = ctrl >>
163 MLXSW_I2C_CIR_CTRL_STATUS_SHIFT;
164 break;
165 }
166 }
167 cond_resched();
168 } while ((time_before(jiffies, end)) || (i++ < MLXSW_I2C_RETRY));
169
170 if (wait_done) {
171 if (*p_status)
172 err = -EIO;
173 } else {
174 return -ETIMEDOUT;
175 }
176
177 return err > 0 ? 0 : err;
178 }
179
180 /* Routine posts a command to ASIC through mail box. */
mlxsw_i2c_write_cmd(struct i2c_client * client,struct mlxsw_i2c * mlxsw_i2c,int immediate)181 static int mlxsw_i2c_write_cmd(struct i2c_client *client,
182 struct mlxsw_i2c *mlxsw_i2c,
183 int immediate)
184 {
185 __be32 push_cmd_buf[MLXSW_I2C_PUSH_CMD_SIZE / 4] = {
186 0, cpu_to_be32(MLXSW_I2C_PUSH_IMM_CMD)
187 };
188 __be32 prep_cmd_buf[MLXSW_I2C_PREP_SIZE / 4] = {
189 0, 0, 0, 0, 0, 0,
190 cpu_to_be32(client->adapter->nr & 0xffff),
191 cpu_to_be32(MLXSW_I2C_SET_IMM_CMD)
192 };
193 struct i2c_msg push_cmd =
194 MLXSW_I2C_WRITE_MSG(client, push_cmd_buf,
195 MLXSW_I2C_PUSH_CMD_SIZE);
196 struct i2c_msg prep_cmd =
197 MLXSW_I2C_WRITE_MSG(client, prep_cmd_buf, MLXSW_I2C_PREP_SIZE);
198 int err;
199
200 if (!immediate) {
201 push_cmd_buf[1] = cpu_to_be32(MLXSW_I2C_PUSH_CMD);
202 prep_cmd_buf[7] = cpu_to_be32(MLXSW_I2C_SET_CMD);
203 }
204 mlxsw_i2c_set_slave_addr((u8 *)prep_cmd_buf,
205 MLXSW_I2C_CIR2_BASE);
206 mlxsw_i2c_set_slave_addr((u8 *)push_cmd_buf,
207 MLXSW_I2C_CIR2_OFF_STATUS);
208
209 /* Prepare Command Interface Register for transaction */
210 err = i2c_transfer(client->adapter, &prep_cmd, 1);
211 if (err < 0)
212 return err;
213 else if (err != 1)
214 return -EIO;
215
216 /* Write out Command Interface Register GO bit to push transaction */
217 err = i2c_transfer(client->adapter, &push_cmd, 1);
218 if (err < 0)
219 return err;
220 else if (err != 1)
221 return -EIO;
222
223 return 0;
224 }
225
226 /* Routine posts initialization command to ASIC through mail box. */
227 static int
mlxsw_i2c_write_init_cmd(struct i2c_client * client,struct mlxsw_i2c * mlxsw_i2c,u16 opcode,u32 in_mod)228 mlxsw_i2c_write_init_cmd(struct i2c_client *client,
229 struct mlxsw_i2c *mlxsw_i2c, u16 opcode, u32 in_mod)
230 {
231 __be32 push_cmd_buf[MLXSW_I2C_PUSH_CMD_SIZE / 4] = {
232 0, cpu_to_be32(MLXSW_I2C_PUSH_EVENT_CMD)
233 };
234 __be32 prep_cmd_buf[MLXSW_I2C_PREP_SIZE / 4] = {
235 0, 0, 0, 0, 0, 0,
236 cpu_to_be32(client->adapter->nr & 0xffff),
237 cpu_to_be32(MLXSW_I2C_SET_EVENT_CMD)
238 };
239 struct i2c_msg push_cmd =
240 MLXSW_I2C_WRITE_MSG(client, push_cmd_buf,
241 MLXSW_I2C_PUSH_CMD_SIZE);
242 struct i2c_msg prep_cmd =
243 MLXSW_I2C_WRITE_MSG(client, prep_cmd_buf, MLXSW_I2C_PREP_SIZE);
244 u8 status;
245 int err;
246
247 push_cmd_buf[1] = cpu_to_be32(MLXSW_I2C_PUSH_EVENT_CMD | opcode);
248 prep_cmd_buf[3] = cpu_to_be32(in_mod);
249 prep_cmd_buf[7] = cpu_to_be32(MLXSW_I2C_GO_BIT | opcode);
250 mlxsw_i2c_set_slave_addr((u8 *)prep_cmd_buf,
251 MLXSW_I2C_CIR2_BASE);
252 mlxsw_i2c_set_slave_addr((u8 *)push_cmd_buf,
253 MLXSW_I2C_CIR2_OFF_STATUS);
254
255 /* Prepare Command Interface Register for transaction */
256 err = i2c_transfer(client->adapter, &prep_cmd, 1);
257 if (err < 0)
258 return err;
259 else if (err != 1)
260 return -EIO;
261
262 /* Write out Command Interface Register GO bit to push transaction */
263 err = i2c_transfer(client->adapter, &push_cmd, 1);
264 if (err < 0)
265 return err;
266 else if (err != 1)
267 return -EIO;
268
269 /* Wait until go bit is cleared. */
270 err = mlxsw_i2c_wait_go_bit(client, mlxsw_i2c, &status);
271 if (err) {
272 dev_err(&client->dev, "HW semaphore is not released");
273 return err;
274 }
275
276 /* Validate transaction completion status. */
277 if (status) {
278 dev_err(&client->dev, "Bad transaction completion status %x\n",
279 status);
280 return -EIO;
281 }
282
283 return 0;
284 }
285
286 /* Routine obtains mail box offsets from ASIC register space. */
mlxsw_i2c_get_mbox(struct i2c_client * client,struct mlxsw_i2c * mlxsw_i2c)287 static int mlxsw_i2c_get_mbox(struct i2c_client *client,
288 struct mlxsw_i2c *mlxsw_i2c)
289 {
290 u8 addr_buf[MLXSW_I2C_ADDR_BUF_SIZE];
291 u8 buf[MLXSW_I2C_MBOX_SIZE];
292 struct i2c_msg mbox_cmd[] =
293 MLXSW_I2C_READ_MSG(client, addr_buf, buf, MLXSW_I2C_MBOX_SIZE);
294 int err;
295
296 /* Read mail boxes offsets. */
297 mlxsw_i2c_set_slave_addr(addr_buf, MLXSW_I2C_CIR2_BASE);
298 err = i2c_transfer(client->adapter, mbox_cmd, 2);
299 if (err != 2) {
300 dev_err(&client->dev, "Could not obtain mail boxes\n");
301 if (!err)
302 return -EIO;
303 else
304 return err;
305 }
306
307 /* Convert mail boxes. */
308 mlxsw_i2c_convert_mbox(mlxsw_i2c, &buf[MLXSW_I2C_MBOX_OUT_PARAM_OFF]);
309
310 return err;
311 }
312
313 /* Routine sends I2C write transaction to ASIC device. */
314 static int
mlxsw_i2c_write(struct device * dev,size_t in_mbox_size,u8 * in_mbox,int num,u8 * p_status)315 mlxsw_i2c_write(struct device *dev, size_t in_mbox_size, u8 *in_mbox, int num,
316 u8 *p_status)
317 {
318 struct i2c_client *client = to_i2c_client(dev);
319 struct mlxsw_i2c *mlxsw_i2c = i2c_get_clientdata(client);
320 unsigned long timeout = msecs_to_jiffies(MLXSW_I2C_TIMEOUT_MSECS);
321 int off = mlxsw_i2c->cmd.mb_off_in, chunk_size, i, j;
322 unsigned long end;
323 u8 *tran_buf;
324 struct i2c_msg write_tran =
325 MLXSW_I2C_WRITE_MSG(client, NULL, MLXSW_I2C_PUSH_CMD_SIZE);
326 int err;
327
328 tran_buf = kmalloc(mlxsw_i2c->block_size + MLXSW_I2C_ADDR_BUF_SIZE,
329 GFP_KERNEL);
330 if (!tran_buf)
331 return -ENOMEM;
332
333 write_tran.buf = tran_buf;
334 for (i = 0; i < num; i++) {
335 chunk_size = (in_mbox_size > mlxsw_i2c->block_size) ?
336 mlxsw_i2c->block_size : in_mbox_size;
337 write_tran.len = MLXSW_I2C_ADDR_WIDTH + chunk_size;
338 mlxsw_i2c_set_slave_addr(tran_buf, off);
339 memcpy(&tran_buf[MLXSW_I2C_ADDR_BUF_SIZE], in_mbox +
340 mlxsw_i2c->block_size * i, chunk_size);
341
342 j = 0;
343 end = jiffies + timeout;
344 do {
345 err = i2c_transfer(client->adapter, &write_tran, 1);
346 if (err == 1)
347 break;
348
349 cond_resched();
350 } while ((time_before(jiffies, end)) ||
351 (j++ < MLXSW_I2C_RETRY));
352
353 if (err != 1) {
354 if (!err) {
355 err = -EIO;
356 goto mlxsw_i2c_write_exit;
357 }
358 }
359
360 off += chunk_size;
361 in_mbox_size -= chunk_size;
362 }
363
364 /* Prepare and write out Command Interface Register for transaction. */
365 err = mlxsw_i2c_write_cmd(client, mlxsw_i2c, 0);
366 if (err) {
367 dev_err(&client->dev, "Could not start transaction");
368 err = -EIO;
369 goto mlxsw_i2c_write_exit;
370 }
371
372 /* Wait until go bit is cleared. */
373 err = mlxsw_i2c_wait_go_bit(client, mlxsw_i2c, p_status);
374 if (err) {
375 dev_err(&client->dev, "HW semaphore is not released");
376 goto mlxsw_i2c_write_exit;
377 }
378
379 /* Validate transaction completion status. */
380 if (*p_status) {
381 dev_err(&client->dev, "Bad transaction completion status %x\n",
382 *p_status);
383 err = -EIO;
384 }
385
386 mlxsw_i2c_write_exit:
387 kfree(tran_buf);
388 return err;
389 }
390
391 /* Routine executes I2C command. */
392 static int
mlxsw_i2c_cmd(struct device * dev,u16 opcode,u32 in_mod,size_t in_mbox_size,u8 * in_mbox,size_t out_mbox_size,u8 * out_mbox,u8 * status)393 mlxsw_i2c_cmd(struct device *dev, u16 opcode, u32 in_mod, size_t in_mbox_size,
394 u8 *in_mbox, size_t out_mbox_size, u8 *out_mbox, u8 *status)
395 {
396 struct i2c_client *client = to_i2c_client(dev);
397 struct mlxsw_i2c *mlxsw_i2c = i2c_get_clientdata(client);
398 unsigned long timeout = msecs_to_jiffies(MLXSW_I2C_TIMEOUT_MSECS);
399 u8 tran_buf[MLXSW_I2C_ADDR_BUF_SIZE];
400 int num, chunk_size, reg_size, i, j;
401 int off = mlxsw_i2c->cmd.mb_off_out;
402 unsigned long end;
403 struct i2c_msg read_tran[] =
404 MLXSW_I2C_READ_MSG(client, tran_buf, NULL, 0);
405 int err;
406
407 WARN_ON(in_mbox_size % sizeof(u32) || out_mbox_size % sizeof(u32));
408
409 if (in_mbox) {
410 reg_size = mlxsw_i2c_get_reg_size(in_mbox);
411 num = reg_size / mlxsw_i2c->block_size;
412 if (reg_size % mlxsw_i2c->block_size)
413 num++;
414
415 if (mutex_lock_interruptible(&mlxsw_i2c->cmd.lock) < 0) {
416 dev_err(&client->dev, "Could not acquire lock");
417 return -EINVAL;
418 }
419
420 err = mlxsw_i2c_write(dev, reg_size, in_mbox, num, status);
421 if (err)
422 goto cmd_fail;
423
424 /* No out mailbox is case of write transaction. */
425 if (!out_mbox) {
426 mutex_unlock(&mlxsw_i2c->cmd.lock);
427 return 0;
428 }
429 } else {
430 /* No input mailbox is case of initialization query command. */
431 reg_size = MLXSW_I2C_MAX_DATA_SIZE;
432 num = DIV_ROUND_UP(reg_size, mlxsw_i2c->block_size);
433
434 if (mutex_lock_interruptible(&mlxsw_i2c->cmd.lock) < 0) {
435 dev_err(&client->dev, "Could not acquire lock");
436 return -EINVAL;
437 }
438
439 err = mlxsw_i2c_write_init_cmd(client, mlxsw_i2c, opcode,
440 in_mod);
441 if (err)
442 goto cmd_fail;
443 }
444
445 /* Send read transaction to get output mailbox content. */
446 read_tran[1].buf = out_mbox;
447 for (i = 0; i < num; i++) {
448 chunk_size = (reg_size > mlxsw_i2c->block_size) ?
449 mlxsw_i2c->block_size : reg_size;
450 read_tran[1].len = chunk_size;
451 mlxsw_i2c_set_slave_addr(tran_buf, off);
452
453 j = 0;
454 end = jiffies + timeout;
455 do {
456 err = i2c_transfer(client->adapter, read_tran,
457 ARRAY_SIZE(read_tran));
458 if (err == ARRAY_SIZE(read_tran))
459 break;
460
461 cond_resched();
462 } while ((time_before(jiffies, end)) ||
463 (j++ < MLXSW_I2C_RETRY));
464
465 if (err != ARRAY_SIZE(read_tran)) {
466 if (!err)
467 err = -EIO;
468
469 goto cmd_fail;
470 }
471
472 off += chunk_size;
473 reg_size -= chunk_size;
474 read_tran[1].buf += chunk_size;
475 }
476
477 mutex_unlock(&mlxsw_i2c->cmd.lock);
478
479 return 0;
480
481 cmd_fail:
482 mutex_unlock(&mlxsw_i2c->cmd.lock);
483 return err;
484 }
485
mlxsw_i2c_cmd_exec(void * bus_priv,u16 opcode,u8 opcode_mod,u32 in_mod,bool out_mbox_direct,char * in_mbox,size_t in_mbox_size,char * out_mbox,size_t out_mbox_size,u8 * status)486 static int mlxsw_i2c_cmd_exec(void *bus_priv, u16 opcode, u8 opcode_mod,
487 u32 in_mod, bool out_mbox_direct,
488 char *in_mbox, size_t in_mbox_size,
489 char *out_mbox, size_t out_mbox_size,
490 u8 *status)
491 {
492 struct mlxsw_i2c *mlxsw_i2c = bus_priv;
493
494 return mlxsw_i2c_cmd(mlxsw_i2c->dev, opcode, in_mod, in_mbox_size,
495 in_mbox, out_mbox_size, out_mbox, status);
496 }
497
mlxsw_i2c_skb_transmit_busy(void * bus_priv,const struct mlxsw_tx_info * tx_info)498 static bool mlxsw_i2c_skb_transmit_busy(void *bus_priv,
499 const struct mlxsw_tx_info *tx_info)
500 {
501 return false;
502 }
503
mlxsw_i2c_skb_transmit(void * bus_priv,struct sk_buff * skb,const struct mlxsw_tx_info * tx_info)504 static int mlxsw_i2c_skb_transmit(void *bus_priv, struct sk_buff *skb,
505 const struct mlxsw_tx_info *tx_info)
506 {
507 return 0;
508 }
509
510 static int
mlxsw_i2c_init(void * bus_priv,struct mlxsw_core * mlxsw_core,const struct mlxsw_config_profile * profile,struct mlxsw_res * res)511 mlxsw_i2c_init(void *bus_priv, struct mlxsw_core *mlxsw_core,
512 const struct mlxsw_config_profile *profile,
513 struct mlxsw_res *res)
514 {
515 struct mlxsw_i2c *mlxsw_i2c = bus_priv;
516 char *mbox;
517 int err;
518
519 mlxsw_i2c->core = mlxsw_core;
520
521 mbox = mlxsw_cmd_mbox_alloc();
522 if (!mbox)
523 return -ENOMEM;
524
525 err = mlxsw_cmd_query_fw(mlxsw_core, mbox);
526 if (err)
527 goto mbox_put;
528
529 mlxsw_i2c->bus_info.fw_rev.major =
530 mlxsw_cmd_mbox_query_fw_fw_rev_major_get(mbox);
531 mlxsw_i2c->bus_info.fw_rev.minor =
532 mlxsw_cmd_mbox_query_fw_fw_rev_minor_get(mbox);
533 mlxsw_i2c->bus_info.fw_rev.subminor =
534 mlxsw_cmd_mbox_query_fw_fw_rev_subminor_get(mbox);
535
536 err = mlxsw_core_resources_query(mlxsw_core, mbox, res);
537
538 mbox_put:
539 mlxsw_cmd_mbox_free(mbox);
540 return err;
541 }
542
mlxsw_i2c_fini(void * bus_priv)543 static void mlxsw_i2c_fini(void *bus_priv)
544 {
545 struct mlxsw_i2c *mlxsw_i2c = bus_priv;
546
547 mlxsw_i2c->core = NULL;
548 }
549
550 static const struct mlxsw_bus mlxsw_i2c_bus = {
551 .kind = "i2c",
552 .init = mlxsw_i2c_init,
553 .fini = mlxsw_i2c_fini,
554 .skb_transmit_busy = mlxsw_i2c_skb_transmit_busy,
555 .skb_transmit = mlxsw_i2c_skb_transmit,
556 .cmd_exec = mlxsw_i2c_cmd_exec,
557 };
558
mlxsw_i2c_probe(struct i2c_client * client,const struct i2c_device_id * id)559 static int mlxsw_i2c_probe(struct i2c_client *client,
560 const struct i2c_device_id *id)
561 {
562 const struct i2c_adapter_quirks *quirks = client->adapter->quirks;
563 struct mlxsw_i2c *mlxsw_i2c;
564 u8 status;
565 int err;
566
567 mlxsw_i2c = devm_kzalloc(&client->dev, sizeof(*mlxsw_i2c), GFP_KERNEL);
568 if (!mlxsw_i2c)
569 return -ENOMEM;
570
571 if (quirks) {
572 if ((quirks->max_read_len &&
573 quirks->max_read_len < MLXSW_I2C_BLK_DEF) ||
574 (quirks->max_write_len &&
575 quirks->max_write_len < MLXSW_I2C_BLK_DEF)) {
576 dev_err(&client->dev, "Insufficient transaction buffer length\n");
577 return -EOPNOTSUPP;
578 }
579
580 mlxsw_i2c->block_size = min_t(u16, MLXSW_I2C_BLK_MAX,
581 min_t(u16, quirks->max_read_len,
582 quirks->max_write_len));
583 } else {
584 mlxsw_i2c->block_size = MLXSW_I2C_BLK_DEF;
585 }
586
587 i2c_set_clientdata(client, mlxsw_i2c);
588 mutex_init(&mlxsw_i2c->cmd.lock);
589
590 /* In order to use mailboxes through the i2c, special area is reserved
591 * on the i2c address space that can be used for input and output
592 * mailboxes. Such mailboxes are called local mailboxes. When using a
593 * local mailbox, software should specify 0 as the Input/Output
594 * parameters. The location of the Local Mailbox addresses on the i2c
595 * space can be retrieved through the QUERY_FW command.
596 * For this purpose QUERY_FW is to be issued with opcode modifier equal
597 * 0x01. For such command the output parameter is an immediate value.
598 * Here QUERY_FW command is invoked for ASIC probing and for getting
599 * local mailboxes addresses from immedate output parameters.
600 */
601
602 /* Prepare and write out Command Interface Register for transaction */
603 err = mlxsw_i2c_write_cmd(client, mlxsw_i2c, 1);
604 if (err) {
605 dev_err(&client->dev, "Could not start transaction");
606 goto errout;
607 }
608
609 /* Wait until go bit is cleared. */
610 err = mlxsw_i2c_wait_go_bit(client, mlxsw_i2c, &status);
611 if (err) {
612 dev_err(&client->dev, "HW semaphore is not released");
613 goto errout;
614 }
615
616 /* Validate transaction completion status. */
617 if (status) {
618 dev_err(&client->dev, "Bad transaction completion status %x\n",
619 status);
620 err = -EIO;
621 goto errout;
622 }
623
624 /* Get mailbox offsets. */
625 err = mlxsw_i2c_get_mbox(client, mlxsw_i2c);
626 if (err < 0) {
627 dev_err(&client->dev, "Fail to get mailboxes\n");
628 goto errout;
629 }
630
631 dev_info(&client->dev, "%s mb size=%x off=0x%08x out mb size=%x off=0x%08x\n",
632 id->name, mlxsw_i2c->cmd.mb_size_in,
633 mlxsw_i2c->cmd.mb_off_in, mlxsw_i2c->cmd.mb_size_out,
634 mlxsw_i2c->cmd.mb_off_out);
635
636 /* Register device bus. */
637 mlxsw_i2c->bus_info.device_kind = id->name;
638 mlxsw_i2c->bus_info.device_name = client->name;
639 mlxsw_i2c->bus_info.dev = &client->dev;
640 mlxsw_i2c->bus_info.low_frequency = true;
641 mlxsw_i2c->dev = &client->dev;
642
643 err = mlxsw_core_bus_device_register(&mlxsw_i2c->bus_info,
644 &mlxsw_i2c_bus, mlxsw_i2c, false,
645 NULL, NULL);
646 if (err) {
647 dev_err(&client->dev, "Fail to register core bus\n");
648 return err;
649 }
650
651 return 0;
652
653 errout:
654 mutex_destroy(&mlxsw_i2c->cmd.lock);
655 i2c_set_clientdata(client, NULL);
656
657 return err;
658 }
659
mlxsw_i2c_remove(struct i2c_client * client)660 static int mlxsw_i2c_remove(struct i2c_client *client)
661 {
662 struct mlxsw_i2c *mlxsw_i2c = i2c_get_clientdata(client);
663
664 mlxsw_core_bus_device_unregister(mlxsw_i2c->core, false);
665 mutex_destroy(&mlxsw_i2c->cmd.lock);
666
667 return 0;
668 }
669
mlxsw_i2c_driver_register(struct i2c_driver * i2c_driver)670 int mlxsw_i2c_driver_register(struct i2c_driver *i2c_driver)
671 {
672 i2c_driver->probe = mlxsw_i2c_probe;
673 i2c_driver->remove = mlxsw_i2c_remove;
674 return i2c_add_driver(i2c_driver);
675 }
676 EXPORT_SYMBOL(mlxsw_i2c_driver_register);
677
mlxsw_i2c_driver_unregister(struct i2c_driver * i2c_driver)678 void mlxsw_i2c_driver_unregister(struct i2c_driver *i2c_driver)
679 {
680 i2c_del_driver(i2c_driver);
681 }
682 EXPORT_SYMBOL(mlxsw_i2c_driver_unregister);
683
684 MODULE_AUTHOR("Vadim Pasternak <vadimp@mellanox.com>");
685 MODULE_DESCRIPTION("Mellanox switch I2C interface driver");
686 MODULE_LICENSE("Dual BSD/GPL");
687