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1  /*****************************************************************************/
2  /* ips.h -- driver for the Adaptec / IBM ServeRAID controller                */
3  /*                                                                           */
4  /* Written By: Keith Mitchell, IBM Corporation                               */
5  /*             Jack Hammer, Adaptec, Inc.                                    */
6  /*             David Jeffery, Adaptec, Inc.                                  */
7  /*                                                                           */
8  /* Copyright (C) 1999 IBM Corporation                                        */
9  /* Copyright (C) 2003 Adaptec, Inc.                                          */
10  /*                                                                           */
11  /* This program is free software; you can redistribute it and/or modify      */
12  /* it under the terms of the GNU General Public License as published by      */
13  /* the Free Software Foundation; either version 2 of the License, or         */
14  /* (at your option) any later version.                                       */
15  /*                                                                           */
16  /* This program is distributed in the hope that it will be useful,           */
17  /* but WITHOUT ANY WARRANTY; without even the implied warranty of            */
18  /* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the             */
19  /* GNU General Public License for more details.                              */
20  /*                                                                           */
21  /* NO WARRANTY                                                               */
22  /* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR        */
23  /* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT      */
24  /* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,      */
25  /* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is    */
26  /* solely responsible for determining the appropriateness of using and       */
27  /* distributing the Program and assumes all risks associated with its        */
28  /* exercise of rights under this Agreement, including but not limited to     */
29  /* the risks and costs of program errors, damage to or loss of data,         */
30  /* programs or equipment, and unavailability or interruption of operations.  */
31  /*                                                                           */
32  /* DISCLAIMER OF LIABILITY                                                   */
33  /* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY   */
34  /* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL        */
35  /* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND   */
36  /* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR     */
37  /* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE    */
38  /* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED  */
39  /* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES             */
40  /*                                                                           */
41  /* You should have received a copy of the GNU General Public License         */
42  /* along with this program; if not, write to the Free Software               */
43  /* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA */
44  /*                                                                           */
45  /* Bugs/Comments/Suggestions should be mailed to:                            */
46  /*      ipslinux@adaptec.com                                                 */
47  /*                                                                           */
48  /*****************************************************************************/
49  
50  #ifndef _IPS_H_
51     #define _IPS_H_
52  
53  #include <linux/nmi.h>
54  #include <linux/uaccess.h>
55     #include <asm/io.h>
56  
57     /*
58      * Some handy macros
59      */
60     #define IPS_HA(x)                   ((ips_ha_t *) x->hostdata)
61     #define IPS_COMMAND_ID(ha, scb)     (int) (scb - ha->scbs)
62     #define IPS_IS_TROMBONE(ha)         (((ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) && \
63                                           (ha->pcidev->revision >= IPS_REVID_TROMBONE32) && \
64                                           (ha->pcidev->revision <= IPS_REVID_TROMBONE64)) ? 1 : 0)
65     #define IPS_IS_CLARINET(ha)         (((ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) && \
66                                           (ha->pcidev->revision >= IPS_REVID_CLARINETP1) && \
67                                           (ha->pcidev->revision <= IPS_REVID_CLARINETP3)) ? 1 : 0)
68     #define IPS_IS_MORPHEUS(ha)         (ha->pcidev->device == IPS_DEVICEID_MORPHEUS)
69     #define IPS_IS_MARCO(ha)            (ha->pcidev->device == IPS_DEVICEID_MARCO)
70     #define IPS_USE_I2O_DELIVER(ha)     ((IPS_IS_MORPHEUS(ha) || \
71                                           (IPS_IS_TROMBONE(ha) && \
72                                            (ips_force_i2o))) ? 1 : 0)
73     #define IPS_USE_MEMIO(ha)           ((IPS_IS_MORPHEUS(ha) || \
74                                           ((IPS_IS_TROMBONE(ha) || IPS_IS_CLARINET(ha)) && \
75                                            (ips_force_memio))) ? 1 : 0)
76  
77      #define IPS_HAS_ENH_SGLIST(ha)    (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha))
78      #define IPS_USE_ENH_SGLIST(ha)    ((ha)->flags & IPS_HA_ENH_SG)
79      #define IPS_SGLIST_SIZE(ha)       (IPS_USE_ENH_SGLIST(ha) ? \
80                                           sizeof(IPS_ENH_SG_LIST) : sizeof(IPS_STD_SG_LIST))
81  
82    #define IPS_PRINTK(level, pcidev, format, arg...)                 \
83              dev_printk(level , &((pcidev)->dev) , format , ## arg)
84  
85     #define MDELAY(n)			\
86  	do {				\
87  		mdelay(n);		\
88  		touch_nmi_watchdog();	\
89  	} while (0)
90  
91     #ifndef min
92        #define min(x,y) ((x) < (y) ? x : y)
93     #endif
94  
95     #ifndef __iomem       /* For clean compiles in earlier kernels without __iomem annotations */
96        #define __iomem
97     #endif
98  
99     /*
100      * Adapter address map equates
101      */
102     #define IPS_REG_HISR                 0x08    /* Host Interrupt Status Reg   */
103     #define IPS_REG_CCSAR                0x10    /* Cmd Channel System Addr Reg */
104     #define IPS_REG_CCCR                 0x14    /* Cmd Channel Control Reg     */
105     #define IPS_REG_SQHR                 0x20    /* Status Q Head Reg           */
106     #define IPS_REG_SQTR                 0x24    /* Status Q Tail Reg           */
107     #define IPS_REG_SQER                 0x28    /* Status Q End Reg            */
108     #define IPS_REG_SQSR                 0x2C    /* Status Q Start Reg          */
109     #define IPS_REG_SCPR                 0x05    /* Subsystem control port reg  */
110     #define IPS_REG_ISPR                 0x06    /* interrupt status port reg   */
111     #define IPS_REG_CBSP                 0x07    /* CBSP register               */
112     #define IPS_REG_FLAP                 0x18    /* Flash address port          */
113     #define IPS_REG_FLDP                 0x1C    /* Flash data port             */
114     #define IPS_REG_NDAE                 0x38    /* Anaconda 64 NDAE Register   */
115     #define IPS_REG_I2O_INMSGQ           0x40    /* I2O Inbound Message Queue   */
116     #define IPS_REG_I2O_OUTMSGQ          0x44    /* I2O Outbound Message Queue  */
117     #define IPS_REG_I2O_HIR              0x30    /* I2O Interrupt Status        */
118     #define IPS_REG_I960_IDR             0x20    /* i960 Inbound Doorbell       */
119     #define IPS_REG_I960_MSG0            0x18    /* i960 Outbound Reg 0         */
120     #define IPS_REG_I960_MSG1            0x1C    /* i960 Outbound Reg 1         */
121     #define IPS_REG_I960_OIMR            0x34    /* i960 Oubound Int Mask Reg   */
122  
123     /*
124      * Adapter register bit equates
125      */
126     #define IPS_BIT_GHI                  0x04    /* HISR General Host Interrupt */
127     #define IPS_BIT_SQO                  0x02    /* HISR Status Q Overflow      */
128     #define IPS_BIT_SCE                  0x01    /* HISR Status Channel Enqueue */
129     #define IPS_BIT_SEM                  0x08    /* CCCR Semaphore Bit          */
130     #define IPS_BIT_ILE                  0x10    /* CCCR ILE Bit                */
131     #define IPS_BIT_START_CMD            0x101A  /* CCCR Start Command Channel  */
132     #define IPS_BIT_START_STOP           0x0002  /* CCCR Start/Stop Bit         */
133     #define IPS_BIT_RST                  0x80    /* SCPR Reset Bit              */
134     #define IPS_BIT_EBM                  0x02    /* SCPR Enable Bus Master      */
135     #define IPS_BIT_EI                   0x80    /* HISR Enable Interrupts      */
136     #define IPS_BIT_OP                   0x01    /* OP bit in CBSP              */
137     #define IPS_BIT_I2O_OPQI             0x08    /* General Host Interrupt      */
138     #define IPS_BIT_I960_MSG0I           0x01    /* Message Register 0 Interrupt*/
139     #define IPS_BIT_I960_MSG1I           0x02    /* Message Register 1 Interrupt*/
140  
141     /*
142      * Adapter Command ID Equates
143      */
144     #define IPS_CMD_GET_LD_INFO          0x19
145     #define IPS_CMD_GET_SUBSYS           0x40
146     #define IPS_CMD_READ_CONF            0x38
147     #define IPS_CMD_RW_NVRAM_PAGE        0xBC
148     #define IPS_CMD_READ                 0x02
149     #define IPS_CMD_WRITE                0x03
150     #define IPS_CMD_FFDC                 0xD7
151     #define IPS_CMD_ENQUIRY              0x05
152     #define IPS_CMD_FLUSH                0x0A
153     #define IPS_CMD_READ_SG              0x82
154     #define IPS_CMD_WRITE_SG             0x83
155     #define IPS_CMD_DCDB                 0x04
156     #define IPS_CMD_DCDB_SG              0x84
157     #define IPS_CMD_EXTENDED_DCDB 	    0x95
158     #define IPS_CMD_EXTENDED_DCDB_SG	    0x96
159     #define IPS_CMD_CONFIG_SYNC          0x58
160     #define IPS_CMD_ERROR_TABLE          0x17
161     #define IPS_CMD_DOWNLOAD             0x20
162     #define IPS_CMD_RW_BIOSFW            0x22
163     #define IPS_CMD_GET_VERSION_INFO     0xC6
164     #define IPS_CMD_RESET_CHANNEL        0x1A
165  
166     /*
167      * Adapter Equates
168      */
169     #define IPS_CSL                      0xFF
170     #define IPS_POCL                     0x30
171     #define IPS_NORM_STATE               0x00
172     #define IPS_MAX_ADAPTER_TYPES        3
173     #define IPS_MAX_ADAPTERS             16
174     #define IPS_MAX_IOCTL                1
175     #define IPS_MAX_IOCTL_QUEUE          8
176     #define IPS_MAX_QUEUE                128
177     #define IPS_BLKSIZE                  512
178     #define IPS_MAX_SG                   17
179     #define IPS_MAX_LD                   8
180     #define IPS_MAX_CHANNELS             4
181     #define IPS_MAX_TARGETS              15
182     #define IPS_MAX_CHUNKS               16
183     #define IPS_MAX_CMDS                 128
184     #define IPS_MAX_XFER                 0x10000
185     #define IPS_NVRAM_P5_SIG             0xFFDDBB99
186     #define IPS_MAX_POST_BYTES           0x02
187     #define IPS_MAX_CONFIG_BYTES         0x02
188     #define IPS_GOOD_POST_STATUS         0x80
189     #define IPS_SEM_TIMEOUT              2000
190     #define IPS_IOCTL_COMMAND            0x0D
191     #define IPS_INTR_ON                  0
192     #define IPS_INTR_IORL                1
193     #define IPS_FFDC                     99
194     #define IPS_ADAPTER_ID               0xF
195     #define IPS_VENDORID_IBM             0x1014
196     #define IPS_VENDORID_ADAPTEC         0x9005
197     #define IPS_DEVICEID_COPPERHEAD      0x002E
198     #define IPS_DEVICEID_MORPHEUS        0x01BD
199     #define IPS_DEVICEID_MARCO           0x0250
200     #define IPS_SUBDEVICEID_4M           0x01BE
201     #define IPS_SUBDEVICEID_4L           0x01BF
202     #define IPS_SUBDEVICEID_4MX          0x0208
203     #define IPS_SUBDEVICEID_4LX          0x020E
204     #define IPS_SUBDEVICEID_5I2          0x0259
205     #define IPS_SUBDEVICEID_5I1          0x0258
206     #define IPS_SUBDEVICEID_6M           0x0279
207     #define IPS_SUBDEVICEID_6I           0x028C
208     #define IPS_SUBDEVICEID_7k           0x028E
209     #define IPS_SUBDEVICEID_7M           0x028F
210     #define IPS_IOCTL_SIZE               8192
211     #define IPS_STATUS_SIZE              4
212     #define IPS_STATUS_Q_SIZE            (IPS_MAX_CMDS+1) * IPS_STATUS_SIZE
213     #define IPS_IMAGE_SIZE               500 * 1024
214     #define IPS_MEMMAP_SIZE              128
215     #define IPS_ONE_MSEC                 1
216     #define IPS_ONE_SEC                  1000
217  
218     /*
219      * Geometry Settings
220      */
221     #define IPS_COMP_HEADS               128
222     #define IPS_COMP_SECTORS             32
223     #define IPS_NORM_HEADS               254
224     #define IPS_NORM_SECTORS             63
225  
226     /*
227      * Adapter Basic Status Codes
228      */
229     #define IPS_BASIC_STATUS_MASK        0xFF
230     #define IPS_GSC_STATUS_MASK          0x0F
231     #define IPS_CMD_SUCCESS              0x00
232     #define IPS_CMD_RECOVERED_ERROR      0x01
233     #define IPS_INVAL_OPCO               0x03
234     #define IPS_INVAL_CMD_BLK            0x04
235     #define IPS_INVAL_PARM_BLK           0x05
236     #define IPS_BUSY                     0x08
237     #define IPS_CMD_CMPLT_WERROR         0x0C
238     #define IPS_LD_ERROR                 0x0D
239     #define IPS_CMD_TIMEOUT              0x0E
240     #define IPS_PHYS_DRV_ERROR           0x0F
241  
242     /*
243      * Adapter Extended Status Equates
244      */
245     #define IPS_ERR_SEL_TO               0xF0
246     #define IPS_ERR_OU_RUN               0xF2
247     #define IPS_ERR_HOST_RESET           0xF7
248     #define IPS_ERR_DEV_RESET            0xF8
249     #define IPS_ERR_RECOVERY             0xFC
250     #define IPS_ERR_CKCOND               0xFF
251  
252     /*
253      * Operating System Defines
254      */
255     #define IPS_OS_WINDOWS_NT            0x01
256     #define IPS_OS_NETWARE               0x02
257     #define IPS_OS_OPENSERVER            0x03
258     #define IPS_OS_UNIXWARE              0x04
259     #define IPS_OS_SOLARIS               0x05
260     #define IPS_OS_OS2                   0x06
261     #define IPS_OS_LINUX                 0x07
262     #define IPS_OS_FREEBSD               0x08
263  
264     /*
265      * Adapter Revision ID's
266      */
267     #define IPS_REVID_SERVERAID          0x02
268     #define IPS_REVID_NAVAJO             0x03
269     #define IPS_REVID_SERVERAID2         0x04
270     #define IPS_REVID_CLARINETP1         0x05
271     #define IPS_REVID_CLARINETP2         0x07
272     #define IPS_REVID_CLARINETP3         0x0D
273     #define IPS_REVID_TROMBONE32         0x0F
274     #define IPS_REVID_TROMBONE64         0x10
275  
276     /*
277      * NVRAM Page 5 Adapter Defines
278      */
279     #define IPS_ADTYPE_SERVERAID         0x01
280     #define IPS_ADTYPE_SERVERAID2        0x02
281     #define IPS_ADTYPE_NAVAJO            0x03
282     #define IPS_ADTYPE_KIOWA             0x04
283     #define IPS_ADTYPE_SERVERAID3        0x05
284     #define IPS_ADTYPE_SERVERAID3L       0x06
285     #define IPS_ADTYPE_SERVERAID4H       0x07
286     #define IPS_ADTYPE_SERVERAID4M       0x08
287     #define IPS_ADTYPE_SERVERAID4L       0x09
288     #define IPS_ADTYPE_SERVERAID4MX      0x0A
289     #define IPS_ADTYPE_SERVERAID4LX      0x0B
290     #define IPS_ADTYPE_SERVERAID5I2      0x0C
291     #define IPS_ADTYPE_SERVERAID5I1      0x0D
292     #define IPS_ADTYPE_SERVERAID6M       0x0E
293     #define IPS_ADTYPE_SERVERAID6I       0x0F
294     #define IPS_ADTYPE_SERVERAID7t       0x10
295     #define IPS_ADTYPE_SERVERAID7k       0x11
296     #define IPS_ADTYPE_SERVERAID7M       0x12
297  
298     /*
299      * Adapter Command/Status Packet Definitions
300      */
301     #define IPS_SUCCESS                  0x01 /* Successfully completed       */
302     #define IPS_SUCCESS_IMM              0x02 /* Success - Immediately        */
303     #define IPS_FAILURE                  0x04 /* Completed with Error         */
304  
305     /*
306      * Logical Drive Equates
307      */
308     #define IPS_LD_OFFLINE               0x02
309     #define IPS_LD_OKAY                  0x03
310     #define IPS_LD_FREE                  0x00
311     #define IPS_LD_SYS                   0x06
312     #define IPS_LD_CRS                   0x24
313  
314     /*
315      * DCDB Table Equates
316      */
317     #define IPS_NO_DISCONNECT            0x00
318     #define IPS_DISCONNECT_ALLOWED       0x80
319     #define IPS_NO_AUTO_REQSEN           0x40
320     #define IPS_DATA_NONE                0x00
321     #define IPS_DATA_UNK                 0x00
322     #define IPS_DATA_IN                  0x01
323     #define IPS_DATA_OUT                 0x02
324     #define IPS_TRANSFER64K              0x08
325     #define IPS_NOTIMEOUT                0x00
326     #define IPS_TIMEOUT10                0x10
327     #define IPS_TIMEOUT60                0x20
328     #define IPS_TIMEOUT20M               0x30
329  
330     /*
331      * SCSI Inquiry Data Flags
332      */
333     #define IPS_SCSI_INQ_TYPE_DASD       0x00
334     #define IPS_SCSI_INQ_TYPE_PROCESSOR  0x03
335     #define IPS_SCSI_INQ_LU_CONNECTED    0x00
336     #define IPS_SCSI_INQ_RD_REV2         0x02
337     #define IPS_SCSI_INQ_REV2            0x02
338     #define IPS_SCSI_INQ_REV3            0x03
339     #define IPS_SCSI_INQ_Address16       0x01
340     #define IPS_SCSI_INQ_Address32       0x02
341     #define IPS_SCSI_INQ_MedChanger      0x08
342     #define IPS_SCSI_INQ_MultiPort       0x10
343     #define IPS_SCSI_INQ_EncServ         0x40
344     #define IPS_SCSI_INQ_SoftReset       0x01
345     #define IPS_SCSI_INQ_CmdQue          0x02
346     #define IPS_SCSI_INQ_Linked          0x08
347     #define IPS_SCSI_INQ_Sync            0x10
348     #define IPS_SCSI_INQ_WBus16          0x20
349     #define IPS_SCSI_INQ_WBus32          0x40
350     #define IPS_SCSI_INQ_RelAdr          0x80
351  
352     /*
353      * SCSI Request Sense Data Flags
354      */
355     #define IPS_SCSI_REQSEN_VALID        0x80
356     #define IPS_SCSI_REQSEN_CURRENT_ERR  0x70
357     #define IPS_SCSI_REQSEN_NO_SENSE     0x00
358  
359     /*
360      * SCSI Mode Page Equates
361      */
362     #define IPS_SCSI_MP3_SoftSector      0x01
363     #define IPS_SCSI_MP3_HardSector      0x02
364     #define IPS_SCSI_MP3_Removeable      0x04
365     #define IPS_SCSI_MP3_AllocateSurface 0x08
366  
367     /*
368      * HA Flags
369      */
370  
371     #define IPS_HA_ENH_SG                0x1
372  
373     /*
374      * SCB Flags
375      */
376     #define IPS_SCB_MAP_SG               0x00008
377     #define IPS_SCB_MAP_SINGLE           0X00010
378  
379     /*
380      * Passthru stuff
381      */
382     #define IPS_COPPUSRCMD              (('C'<<8) | 65)
383     #define IPS_COPPIOCCMD              (('C'<<8) | 66)
384     #define IPS_NUMCTRLS                (('C'<<8) | 68)
385     #define IPS_CTRLINFO                (('C'<<8) | 69)
386  
387     /* flashing defines */
388     #define IPS_FW_IMAGE                0x00
389     #define IPS_BIOS_IMAGE              0x01
390     #define IPS_WRITE_FW                0x01
391     #define IPS_WRITE_BIOS              0x02
392     #define IPS_ERASE_BIOS              0x03
393     #define IPS_BIOS_HEADER             0xC0
394  
395     /* time oriented stuff */
396     #define IPS_SECS_8HOURS              28800
397  
398     /*
399      * Scsi_Host Template
400      */
401     static int ips_biosparam(struct scsi_device *sdev, struct block_device *bdev,
402  		sector_t capacity, int geom[]);
403     static int ips_slave_configure(struct scsi_device *SDptr);
404  
405  /*
406   * Raid Command Formats
407   */
408  typedef struct {
409     uint8_t  op_code;
410     uint8_t  command_id;
411     uint8_t  log_drv;
412     uint8_t  sg_count;
413     uint32_t lba;
414     uint32_t sg_addr;
415     uint16_t sector_count;
416     uint8_t  segment_4G;
417     uint8_t  enhanced_sg;
418     uint32_t ccsar;
419     uint32_t cccr;
420  } IPS_IO_CMD, *PIPS_IO_CMD;
421  
422  typedef struct {
423     uint8_t  op_code;
424     uint8_t  command_id;
425     uint16_t reserved;
426     uint32_t reserved2;
427     uint32_t buffer_addr;
428     uint32_t reserved3;
429     uint32_t ccsar;
430     uint32_t cccr;
431  } IPS_LD_CMD, *PIPS_LD_CMD;
432  
433  typedef struct {
434     uint8_t  op_code;
435     uint8_t  command_id;
436     uint8_t  reserved;
437     uint8_t  reserved2;
438     uint32_t reserved3;
439     uint32_t buffer_addr;
440     uint32_t reserved4;
441  } IPS_IOCTL_CMD, *PIPS_IOCTL_CMD;
442  
443  typedef struct {
444     uint8_t  op_code;
445     uint8_t  command_id;
446     uint8_t  channel;
447     uint8_t  reserved3;
448     uint8_t  reserved4;
449     uint8_t  reserved5;
450     uint8_t  reserved6;
451     uint8_t  reserved7;
452     uint8_t  reserved8;
453     uint8_t  reserved9;
454     uint8_t  reserved10;
455     uint8_t  reserved11;
456     uint8_t  reserved12;
457     uint8_t  reserved13;
458     uint8_t  reserved14;
459     uint8_t  adapter_flag;
460  } IPS_RESET_CMD, *PIPS_RESET_CMD;
461  
462  typedef struct {
463     uint8_t  op_code;
464     uint8_t  command_id;
465     uint16_t reserved;
466     uint32_t reserved2;
467     uint32_t dcdb_address;
468     uint16_t reserved3;
469     uint8_t  segment_4G;
470     uint8_t  enhanced_sg;
471     uint32_t ccsar;
472     uint32_t cccr;
473  } IPS_DCDB_CMD, *PIPS_DCDB_CMD;
474  
475  typedef struct {
476     uint8_t  op_code;
477     uint8_t  command_id;
478     uint8_t  channel;
479     uint8_t  source_target;
480     uint32_t reserved;
481     uint32_t reserved2;
482     uint32_t reserved3;
483     uint32_t ccsar;
484     uint32_t cccr;
485  } IPS_CS_CMD, *PIPS_CS_CMD;
486  
487  typedef struct {
488     uint8_t  op_code;
489     uint8_t  command_id;
490     uint8_t  log_drv;
491     uint8_t  control;
492     uint32_t reserved;
493     uint32_t reserved2;
494     uint32_t reserved3;
495     uint32_t ccsar;
496     uint32_t cccr;
497  } IPS_US_CMD, *PIPS_US_CMD;
498  
499  typedef struct {
500     uint8_t  op_code;
501     uint8_t  command_id;
502     uint8_t  reserved;
503     uint8_t  state;
504     uint32_t reserved2;
505     uint32_t reserved3;
506     uint32_t reserved4;
507     uint32_t ccsar;
508     uint32_t cccr;
509  } IPS_FC_CMD, *PIPS_FC_CMD;
510  
511  typedef struct {
512     uint8_t  op_code;
513     uint8_t  command_id;
514     uint8_t  reserved;
515     uint8_t  desc;
516     uint32_t reserved2;
517     uint32_t buffer_addr;
518     uint32_t reserved3;
519     uint32_t ccsar;
520     uint32_t cccr;
521  } IPS_STATUS_CMD, *PIPS_STATUS_CMD;
522  
523  typedef struct {
524     uint8_t  op_code;
525     uint8_t  command_id;
526     uint8_t  page;
527     uint8_t  write;
528     uint32_t reserved;
529     uint32_t buffer_addr;
530     uint32_t reserved2;
531     uint32_t ccsar;
532     uint32_t cccr;
533  } IPS_NVRAM_CMD, *PIPS_NVRAM_CMD;
534  
535  typedef struct
536  {
537      uint8_t  op_code;
538      uint8_t  command_id;
539      uint16_t reserved;
540      uint32_t count;
541      uint32_t buffer_addr;
542      uint32_t reserved2;
543  } IPS_VERSION_INFO, *PIPS_VERSION_INFO;
544  
545  typedef struct {
546     uint8_t  op_code;
547     uint8_t  command_id;
548     uint8_t  reset_count;
549     uint8_t  reset_type;
550     uint8_t  second;
551     uint8_t  minute;
552     uint8_t  hour;
553     uint8_t  day;
554     uint8_t  reserved1[4];
555     uint8_t  month;
556     uint8_t  yearH;
557     uint8_t  yearL;
558     uint8_t  reserved2;
559  } IPS_FFDC_CMD, *PIPS_FFDC_CMD;
560  
561  typedef struct {
562     uint8_t  op_code;
563     uint8_t  command_id;
564     uint8_t  type;
565     uint8_t  direction;
566     uint32_t count;
567     uint32_t buffer_addr;
568     uint8_t  total_packets;
569     uint8_t  packet_num;
570     uint16_t reserved;
571  } IPS_FLASHFW_CMD, *PIPS_FLASHFW_CMD;
572  
573  typedef struct {
574     uint8_t  op_code;
575     uint8_t  command_id;
576     uint8_t  type;
577     uint8_t  direction;
578     uint32_t count;
579     uint32_t buffer_addr;
580     uint32_t offset;
581  } IPS_FLASHBIOS_CMD, *PIPS_FLASHBIOS_CMD;
582  
583  typedef union {
584     IPS_IO_CMD         basic_io;
585     IPS_LD_CMD         logical_info;
586     IPS_IOCTL_CMD      ioctl_info;
587     IPS_DCDB_CMD       dcdb;
588     IPS_CS_CMD         config_sync;
589     IPS_US_CMD         unlock_stripe;
590     IPS_FC_CMD         flush_cache;
591     IPS_STATUS_CMD     status;
592     IPS_NVRAM_CMD      nvram;
593     IPS_FFDC_CMD       ffdc;
594     IPS_FLASHFW_CMD    flashfw;
595     IPS_FLASHBIOS_CMD  flashbios;
596     IPS_VERSION_INFO   version_info;
597     IPS_RESET_CMD      reset;
598  } IPS_HOST_COMMAND, *PIPS_HOST_COMMAND;
599  
600  typedef struct {
601     uint8_t  logical_id;
602     uint8_t  reserved;
603     uint8_t  raid_level;
604     uint8_t  state;
605     uint32_t sector_count;
606  } IPS_DRIVE_INFO, *PIPS_DRIVE_INFO;
607  
608  typedef struct {
609     uint8_t       no_of_log_drive;
610     uint8_t       reserved[3];
611     IPS_DRIVE_INFO drive_info[IPS_MAX_LD];
612  } IPS_LD_INFO, *PIPS_LD_INFO;
613  
614  typedef struct {
615     uint8_t   device_address;
616     uint8_t   cmd_attribute;
617     uint16_t  transfer_length;
618     uint32_t  buffer_pointer;
619     uint8_t   cdb_length;
620     uint8_t   sense_length;
621     uint8_t   sg_count;
622     uint8_t   reserved;
623     uint8_t   scsi_cdb[12];
624     uint8_t   sense_info[64];
625     uint8_t   scsi_status;
626     uint8_t   reserved2[3];
627  } IPS_DCDB_TABLE, *PIPS_DCDB_TABLE;
628  
629  typedef struct {
630     uint8_t   device_address;
631     uint8_t   cmd_attribute;
632     uint8_t   cdb_length;
633     uint8_t   reserved_for_LUN;
634     uint32_t  transfer_length;
635     uint32_t  buffer_pointer;
636     uint16_t  sg_count;
637     uint8_t   sense_length;
638     uint8_t   scsi_status;
639     uint32_t  reserved;
640     uint8_t   scsi_cdb[16];
641     uint8_t   sense_info[56];
642  } IPS_DCDB_TABLE_TAPE, *PIPS_DCDB_TABLE_TAPE;
643  
644  typedef union {
645     struct {
646        volatile uint8_t  reserved;
647        volatile uint8_t  command_id;
648        volatile uint8_t  basic_status;
649        volatile uint8_t  extended_status;
650     } fields;
651  
652     volatile uint32_t    value;
653  } IPS_STATUS, *PIPS_STATUS;
654  
655  typedef struct {
656     IPS_STATUS           status[IPS_MAX_CMDS + 1];
657     volatile PIPS_STATUS p_status_start;
658     volatile PIPS_STATUS p_status_end;
659     volatile PIPS_STATUS p_status_tail;
660     volatile uint32_t    hw_status_start;
661     volatile uint32_t    hw_status_tail;
662  } IPS_ADAPTER, *PIPS_ADAPTER;
663  
664  typedef struct {
665     uint8_t  ucLogDriveCount;
666     uint8_t  ucMiscFlag;
667     uint8_t  ucSLTFlag;
668     uint8_t  ucBSTFlag;
669     uint8_t  ucPwrChgCnt;
670     uint8_t  ucWrongAdrCnt;
671     uint8_t  ucUnidentCnt;
672     uint8_t  ucNVramDevChgCnt;
673     uint8_t  CodeBlkVersion[8];
674     uint8_t  BootBlkVersion[8];
675     uint32_t ulDriveSize[IPS_MAX_LD];
676     uint8_t  ucConcurrentCmdCount;
677     uint8_t  ucMaxPhysicalDevices;
678     uint16_t usFlashRepgmCount;
679     uint8_t  ucDefunctDiskCount;
680     uint8_t  ucRebuildFlag;
681     uint8_t  ucOfflineLogDrvCount;
682     uint8_t  ucCriticalDrvCount;
683     uint16_t usConfigUpdateCount;
684     uint8_t  ucBlkFlag;
685     uint8_t  reserved;
686     uint16_t usAddrDeadDisk[IPS_MAX_CHANNELS * (IPS_MAX_TARGETS + 1)];
687  } IPS_ENQ, *PIPS_ENQ;
688  
689  typedef struct {
690     uint8_t  ucInitiator;
691     uint8_t  ucParameters;
692     uint8_t  ucMiscFlag;
693     uint8_t  ucState;
694     uint32_t ulBlockCount;
695     uint8_t  ucDeviceId[28];
696  } IPS_DEVSTATE, *PIPS_DEVSTATE;
697  
698  typedef struct {
699     uint8_t  ucChn;
700     uint8_t  ucTgt;
701     uint16_t ucReserved;
702     uint32_t ulStartSect;
703     uint32_t ulNoOfSects;
704  } IPS_CHUNK, *PIPS_CHUNK;
705  
706  typedef struct {
707     uint16_t ucUserField;
708     uint8_t  ucState;
709     uint8_t  ucRaidCacheParam;
710     uint8_t  ucNoOfChunkUnits;
711     uint8_t  ucStripeSize;
712     uint8_t  ucParams;
713     uint8_t  ucReserved;
714     uint32_t ulLogDrvSize;
715     IPS_CHUNK chunk[IPS_MAX_CHUNKS];
716  } IPS_LD, *PIPS_LD;
717  
718  typedef struct {
719     uint8_t  board_disc[8];
720     uint8_t  processor[8];
721     uint8_t  ucNoChanType;
722     uint8_t  ucNoHostIntType;
723     uint8_t  ucCompression;
724     uint8_t  ucNvramType;
725     uint32_t ulNvramSize;
726  } IPS_HARDWARE, *PIPS_HARDWARE;
727  
728  typedef struct {
729     uint8_t        ucLogDriveCount;
730     uint8_t        ucDateD;
731     uint8_t        ucDateM;
732     uint8_t        ucDateY;
733     uint8_t        init_id[4];
734     uint8_t        host_id[12];
735     uint8_t        time_sign[8];
736     uint32_t       UserOpt;
737     uint16_t       user_field;
738     uint8_t        ucRebuildRate;
739     uint8_t        ucReserve;
740     IPS_HARDWARE   hardware_disc;
741     IPS_LD         logical_drive[IPS_MAX_LD];
742     IPS_DEVSTATE   dev[IPS_MAX_CHANNELS][IPS_MAX_TARGETS+1];
743     uint8_t        reserved[512];
744  } IPS_CONF, *PIPS_CONF;
745  
746  typedef struct {
747     uint32_t  signature;
748     uint8_t   reserved1;
749     uint8_t   adapter_slot;
750     uint16_t  adapter_type;
751     uint8_t   ctrl_bios[8];
752     uint8_t   versioning;                   /* 1 = Versioning Supported, else 0 */
753     uint8_t   version_mismatch;             /* 1 = Versioning MisMatch,  else 0 */
754     uint8_t   reserved2;
755     uint8_t   operating_system;
756     uint8_t   driver_high[4];
757     uint8_t   driver_low[4];
758     uint8_t   BiosCompatibilityID[8];
759     uint8_t   ReservedForOS2[8];
760     uint8_t   bios_high[4];                 /* Adapter's Flashed BIOS Version   */
761     uint8_t   bios_low[4];
762     uint8_t   adapter_order[16];            /* BIOS Telling us the Sort Order   */
763     uint8_t   Filler[60];
764  } IPS_NVRAM_P5, *PIPS_NVRAM_P5;
765  
766  /*--------------------------------------------------------------------------*/
767  /* Data returned from a GetVersion Command                                  */
768  /*--------------------------------------------------------------------------*/
769  
770                                               /* SubSystem Parameter[4]      */
771  #define  IPS_GET_VERSION_SUPPORT 0x00018000  /* Mask for Versioning Support */
772  
773  typedef struct
774  {
775     uint32_t  revision;
776     uint8_t   bootBlkVersion[32];
777     uint8_t   bootBlkAttributes[4];
778     uint8_t   codeBlkVersion[32];
779     uint8_t   biosVersion[32];
780     uint8_t   biosAttributes[4];
781     uint8_t   compatibilityId[32];
782     uint8_t   reserved[4];
783  } IPS_VERSION_DATA;
784  
785  
786  typedef struct _IPS_SUBSYS {
787     uint32_t  param[128];
788  } IPS_SUBSYS, *PIPS_SUBSYS;
789  
790  /**
791   ** SCSI Structures
792   **/
793  
794  /*
795   * Inquiry Data Format
796   */
797  typedef struct {
798     uint8_t   DeviceType;
799     uint8_t   DeviceTypeQualifier;
800     uint8_t   Version;
801     uint8_t   ResponseDataFormat;
802     uint8_t   AdditionalLength;
803     uint8_t   Reserved;
804     uint8_t   Flags[2];
805     uint8_t   VendorId[8];
806     uint8_t   ProductId[16];
807     uint8_t   ProductRevisionLevel[4];
808     uint8_t   Reserved2;                                  /* Provides NULL terminator to name */
809  } IPS_SCSI_INQ_DATA, *PIPS_SCSI_INQ_DATA;
810  
811  /*
812   * Read Capacity Data Format
813   */
814  typedef struct {
815     uint32_t lba;
816     uint32_t len;
817  } IPS_SCSI_CAPACITY;
818  
819  /*
820   * Request Sense Data Format
821   */
822  typedef struct {
823     uint8_t  ResponseCode;
824     uint8_t  SegmentNumber;
825     uint8_t  Flags;
826     uint8_t  Information[4];
827     uint8_t  AdditionalLength;
828     uint8_t  CommandSpecific[4];
829     uint8_t  AdditionalSenseCode;
830     uint8_t  AdditionalSenseCodeQual;
831     uint8_t  FRUCode;
832     uint8_t  SenseKeySpecific[3];
833  } IPS_SCSI_REQSEN;
834  
835  /*
836   * Sense Data Format - Page 3
837   */
838  typedef struct {
839     uint8_t  PageCode;
840     uint8_t  PageLength;
841     uint16_t TracksPerZone;
842     uint16_t AltSectorsPerZone;
843     uint16_t AltTracksPerZone;
844     uint16_t AltTracksPerVolume;
845     uint16_t SectorsPerTrack;
846     uint16_t BytesPerSector;
847     uint16_t Interleave;
848     uint16_t TrackSkew;
849     uint16_t CylinderSkew;
850     uint8_t  flags;
851     uint8_t  reserved[3];
852  } IPS_SCSI_MODE_PAGE3;
853  
854  /*
855   * Sense Data Format - Page 4
856   */
857  typedef struct {
858     uint8_t  PageCode;
859     uint8_t  PageLength;
860     uint16_t CylindersHigh;
861     uint8_t  CylindersLow;
862     uint8_t  Heads;
863     uint16_t WritePrecompHigh;
864     uint8_t  WritePrecompLow;
865     uint16_t ReducedWriteCurrentHigh;
866     uint8_t  ReducedWriteCurrentLow;
867     uint16_t StepRate;
868     uint16_t LandingZoneHigh;
869     uint8_t  LandingZoneLow;
870     uint8_t  flags;
871     uint8_t  RotationalOffset;
872     uint8_t  Reserved;
873     uint16_t MediumRotationRate;
874     uint8_t  Reserved2[2];
875  } IPS_SCSI_MODE_PAGE4;
876  
877  /*
878   * Sense Data Format - Page 8
879   */
880  typedef struct {
881     uint8_t  PageCode;
882     uint8_t  PageLength;
883     uint8_t  flags;
884     uint8_t  RetentPrio;
885     uint16_t DisPrefetchLen;
886     uint16_t MinPrefetchLen;
887     uint16_t MaxPrefetchLen;
888     uint16_t MaxPrefetchCeiling;
889  } IPS_SCSI_MODE_PAGE8;
890  
891  /*
892   * Sense Data Format - Block Descriptor (DASD)
893   */
894  typedef struct {
895     uint32_t NumberOfBlocks;
896     uint8_t  DensityCode;
897     uint16_t BlockLengthHigh;
898     uint8_t  BlockLengthLow;
899  } IPS_SCSI_MODE_PAGE_BLKDESC;
900  
901  /*
902   * Sense Data Format - Mode Page Header
903   */
904  typedef struct {
905     uint8_t  DataLength;
906     uint8_t  MediumType;
907     uint8_t  Reserved;
908     uint8_t  BlockDescLength;
909  } IPS_SCSI_MODE_PAGE_HEADER;
910  
911  typedef struct {
912     IPS_SCSI_MODE_PAGE_HEADER  hdr;
913     IPS_SCSI_MODE_PAGE_BLKDESC blkdesc;
914  
915     union {
916        IPS_SCSI_MODE_PAGE3 pg3;
917        IPS_SCSI_MODE_PAGE4 pg4;
918        IPS_SCSI_MODE_PAGE8 pg8;
919     } pdata;
920  } IPS_SCSI_MODE_PAGE_DATA;
921  
922  /*
923   * Scatter Gather list format
924   */
925  typedef struct ips_sglist {
926     uint32_t address;
927     uint32_t length;
928  } IPS_STD_SG_LIST;
929  
930  typedef struct ips_enh_sglist {
931     uint32_t address_lo;
932     uint32_t address_hi;
933     uint32_t length;
934     uint32_t reserved;
935  } IPS_ENH_SG_LIST;
936  
937  typedef union {
938     void             *list;
939     IPS_STD_SG_LIST  *std_list;
940     IPS_ENH_SG_LIST  *enh_list;
941  } IPS_SG_LIST;
942  
943  typedef struct {
944     char *option_name;
945     int  *option_flag;
946     int   option_value;
947  } IPS_OPTION;
948  
949  /*
950   * Status Info
951   */
952  typedef struct ips_stat {
953     uint32_t residue_len;
954     void     *scb_addr;
955     uint8_t  padding[12 - sizeof(void *)];
956  } ips_stat_t;
957  
958  /*
959   * SCB Queue Format
960   */
961  typedef struct ips_scb_queue {
962     struct ips_scb *head;
963     struct ips_scb *tail;
964     int             count;
965  } ips_scb_queue_t;
966  
967  /*
968   * Wait queue_format
969   */
970  typedef struct ips_wait_queue {
971  	struct scsi_cmnd *head;
972  	struct scsi_cmnd *tail;
973  	int count;
974  } ips_wait_queue_entry_t;
975  
976  typedef struct ips_copp_wait_item {
977  	struct scsi_cmnd *scsi_cmd;
978  	struct ips_copp_wait_item *next;
979  } ips_copp_wait_item_t;
980  
981  typedef struct ips_copp_queue {
982     struct ips_copp_wait_item *head;
983     struct ips_copp_wait_item *tail;
984     int                        count;
985  } ips_copp_queue_t;
986  
987  /* forward decl for host structure */
988  struct ips_ha;
989  
990  typedef struct {
991     int       (*reset)(struct ips_ha *);
992     int       (*issue)(struct ips_ha *, struct ips_scb *);
993     int       (*isinit)(struct ips_ha *);
994     int       (*isintr)(struct ips_ha *);
995     int       (*init)(struct ips_ha *);
996     int       (*erasebios)(struct ips_ha *);
997     int       (*programbios)(struct ips_ha *, char *, uint32_t, uint32_t);
998     int       (*verifybios)(struct ips_ha *, char *, uint32_t, uint32_t);
999     void      (*statinit)(struct ips_ha *);
1000     int       (*intr)(struct ips_ha *);
1001     void      (*enableint)(struct ips_ha *);
1002     uint32_t (*statupd)(struct ips_ha *);
1003  } ips_hw_func_t;
1004  
1005  typedef struct ips_ha {
1006     uint8_t            ha_id[IPS_MAX_CHANNELS+1];
1007     uint32_t           dcdb_active[IPS_MAX_CHANNELS];
1008     uint32_t           io_addr;            /* Base I/O address           */
1009     uint8_t            ntargets;           /* Number of targets          */
1010     uint8_t            nbus;               /* Number of buses            */
1011     uint8_t            nlun;               /* Number of Luns             */
1012     uint16_t           ad_type;            /* Adapter type               */
1013     uint16_t           host_num;           /* Adapter number             */
1014     uint32_t           max_xfer;           /* Maximum Xfer size          */
1015     uint32_t           max_cmds;           /* Max concurrent commands    */
1016     uint32_t           num_ioctl;          /* Number of Ioctls           */
1017     ips_stat_t         sp;                 /* Status packer pointer      */
1018     struct ips_scb    *scbs;               /* Array of all CCBS          */
1019     struct ips_scb    *scb_freelist;       /* SCB free list              */
1020     ips_wait_queue_entry_t   scb_waitlist;       /* Pending SCB list           */
1021     ips_copp_queue_t   copp_waitlist;      /* Pending PT list            */
1022     ips_scb_queue_t    scb_activelist;     /* Active SCB list            */
1023     IPS_IO_CMD        *dummy;              /* dummy command              */
1024     IPS_ADAPTER       *adapt;              /* Adapter status area        */
1025     IPS_LD_INFO       *logical_drive_info; /* Adapter Logical Drive Info */
1026     dma_addr_t         logical_drive_info_dma_addr; /* Logical Drive Info DMA Address */
1027     IPS_ENQ           *enq;                /* Adapter Enquiry data       */
1028     IPS_CONF          *conf;               /* Adapter config data        */
1029     IPS_NVRAM_P5      *nvram;              /* NVRAM page 5 data          */
1030     IPS_SUBSYS        *subsys;             /* Subsystem parameters       */
1031     char              *ioctl_data;         /* IOCTL data area            */
1032     uint32_t           ioctl_datasize;     /* IOCTL data size            */
1033     uint32_t           cmd_in_progress;    /* Current command in progress*/
1034     int                flags;              /*                            */
1035     uint8_t            waitflag;           /* are we waiting for cmd     */
1036     uint8_t            active;
1037     int                ioctl_reset;        /* IOCTL Requested Reset Flag */
1038     uint16_t           reset_count;        /* number of resets           */
1039     time64_t           last_ffdc;          /* last time we sent ffdc info*/
1040     uint8_t            slot_num;           /* PCI Slot Number            */
1041     int                ioctl_len;          /* size of ioctl buffer       */
1042     dma_addr_t         ioctl_busaddr;      /* dma address of ioctl buffer*/
1043     uint8_t            bios_version[8];    /* BIOS Revision              */
1044     uint32_t           mem_addr;           /* Memory mapped address      */
1045     uint32_t           io_len;             /* Size of IO Address         */
1046     uint32_t           mem_len;            /* Size of memory address     */
1047     char              __iomem *mem_ptr;    /* Memory mapped Ptr          */
1048     char              __iomem *ioremap_ptr;/* ioremapped memory pointer  */
1049     ips_hw_func_t      func;               /* hw function pointers       */
1050     struct pci_dev    *pcidev;             /* PCI device handle          */
1051     char              *flash_data;         /* Save Area for flash data   */
1052     int                flash_len;          /* length of flash buffer     */
1053     u32                flash_datasize;     /* Save Area for flash data size */
1054     dma_addr_t         flash_busaddr;      /* dma address of flash buffer*/
1055     dma_addr_t         enq_busaddr;        /* dma address of enq struct  */
1056     uint8_t            requires_esl;       /* Requires an EraseStripeLock */
1057  } ips_ha_t;
1058  
1059  typedef void (*ips_scb_callback) (ips_ha_t *, struct ips_scb *);
1060  
1061  /*
1062   * SCB Format
1063   */
1064  typedef struct ips_scb {
1065     IPS_HOST_COMMAND  cmd;
1066     IPS_DCDB_TABLE    dcdb;
1067     uint8_t           target_id;
1068     uint8_t           bus;
1069     uint8_t           lun;
1070     uint8_t           cdb[12];
1071     uint32_t          scb_busaddr;
1072     uint32_t          old_data_busaddr;  // Obsolete, but kept for old utility compatibility
1073     uint32_t          timeout;
1074     uint8_t           basic_status;
1075     uint8_t           extended_status;
1076     uint8_t           breakup;
1077     uint8_t           sg_break;
1078     uint32_t          data_len;
1079     uint32_t          sg_len;
1080     uint32_t          flags;
1081     uint32_t          op_code;
1082     IPS_SG_LIST       sg_list;
1083     struct scsi_cmnd *scsi_cmd;
1084     struct ips_scb   *q_next;
1085     ips_scb_callback  callback;
1086     uint32_t          sg_busaddr;
1087     int               sg_count;
1088     dma_addr_t        data_busaddr;
1089  } ips_scb_t;
1090  
1091  typedef struct ips_scb_pt {
1092     IPS_HOST_COMMAND  cmd;
1093     IPS_DCDB_TABLE    dcdb;
1094     uint8_t           target_id;
1095     uint8_t           bus;
1096     uint8_t           lun;
1097     uint8_t           cdb[12];
1098     uint32_t          scb_busaddr;
1099     uint32_t          data_busaddr;
1100     uint32_t          timeout;
1101     uint8_t           basic_status;
1102     uint8_t           extended_status;
1103     uint16_t          breakup;
1104     uint32_t          data_len;
1105     uint32_t          sg_len;
1106     uint32_t          flags;
1107     uint32_t          op_code;
1108     IPS_SG_LIST      *sg_list;
1109     struct scsi_cmnd *scsi_cmd;
1110     struct ips_scb   *q_next;
1111     ips_scb_callback  callback;
1112  } ips_scb_pt_t;
1113  
1114  /*
1115   * Passthru Command Format
1116   */
1117  typedef struct {
1118     uint8_t       CoppID[4];
1119     uint32_t      CoppCmd;
1120     uint32_t      PtBuffer;
1121     uint8_t      *CmdBuffer;
1122     uint32_t      CmdBSize;
1123     ips_scb_pt_t  CoppCP;
1124     uint32_t      TimeOut;
1125     uint8_t       BasicStatus;
1126     uint8_t       ExtendedStatus;
1127     uint8_t       AdapterType;
1128     uint8_t       reserved;
1129  } ips_passthru_t;
1130  
1131  #endif
1132  
1133  /* The Version Information below gets created by SED during the build process. */
1134  /* Do not modify the next line; it's what SED is looking for to do the insert. */
1135  /* Version Info                                                                */
1136  /*************************************************************************
1137  *
1138  * VERSION.H -- version numbers and copyright notices in various formats
1139  *
1140  *************************************************************************/
1141  
1142  #define IPS_VER_MAJOR 7
1143  #define IPS_VER_MAJOR_STRING __stringify(IPS_VER_MAJOR)
1144  #define IPS_VER_MINOR 12
1145  #define IPS_VER_MINOR_STRING __stringify(IPS_VER_MINOR)
1146  #define IPS_VER_BUILD 05
1147  #define IPS_VER_BUILD_STRING __stringify(IPS_VER_BUILD)
1148  #define IPS_VER_STRING IPS_VER_MAJOR_STRING "." \
1149  		IPS_VER_MINOR_STRING "." IPS_VER_BUILD_STRING
1150  #define IPS_RELEASE_ID 0x00020000
1151  #define IPS_BUILD_IDENT 761
1152  #define IPS_LEGALCOPYRIGHT_STRING "(C) Copyright IBM Corp. 1994, 2002. All Rights Reserved."
1153  #define IPS_ADAPTECCOPYRIGHT_STRING "(c) Copyright Adaptec, Inc. 2002 to 2004. All Rights Reserved."
1154  #define IPS_DELLCOPYRIGHT_STRING "(c) Copyright Dell 2004. All Rights Reserved."
1155  #define IPS_NT_LEGALCOPYRIGHT_STRING "(C) Copyright IBM Corp. 1994, 2002."
1156  
1157  /* Version numbers for various adapters */
1158  #define IPS_VER_SERVERAID1 "2.25.01"
1159  #define IPS_VER_SERVERAID2 "2.88.13"
1160  #define IPS_VER_NAVAJO "2.88.13"
1161  #define IPS_VER_SERVERAID3 "6.10.24"
1162  #define IPS_VER_SERVERAID4H "7.12.02"
1163  #define IPS_VER_SERVERAID4MLx "7.12.02"
1164  #define IPS_VER_SARASOTA "7.12.02"
1165  #define IPS_VER_MARCO "7.12.02"
1166  #define IPS_VER_SEBRING "7.12.02"
1167  #define IPS_VER_KEYWEST "7.12.02"
1168  
1169  /* Compatibility IDs for various adapters */
1170  #define IPS_COMPAT_UNKNOWN ""
1171  #define IPS_COMPAT_CURRENT "KW710"
1172  #define IPS_COMPAT_SERVERAID1 "2.25.01"
1173  #define IPS_COMPAT_SERVERAID2 "2.88.13"
1174  #define IPS_COMPAT_NAVAJO  "2.88.13"
1175  #define IPS_COMPAT_KIOWA "2.88.13"
1176  #define IPS_COMPAT_SERVERAID3H  "SB610"
1177  #define IPS_COMPAT_SERVERAID3L  "SB610"
1178  #define IPS_COMPAT_SERVERAID4H  "KW710"
1179  #define IPS_COMPAT_SERVERAID4M  "KW710"
1180  #define IPS_COMPAT_SERVERAID4L  "KW710"
1181  #define IPS_COMPAT_SERVERAID4Mx "KW710"
1182  #define IPS_COMPAT_SERVERAID4Lx "KW710"
1183  #define IPS_COMPAT_SARASOTA     "KW710"
1184  #define IPS_COMPAT_MARCO        "KW710"
1185  #define IPS_COMPAT_SEBRING      "KW710"
1186  #define IPS_COMPAT_TAMPA        "KW710"
1187  #define IPS_COMPAT_KEYWEST      "KW710"
1188  #define IPS_COMPAT_BIOS "KW710"
1189  
1190  #define IPS_COMPAT_MAX_ADAPTER_TYPE 18
1191  #define IPS_COMPAT_ID_LENGTH 8
1192  
1193  #define IPS_DEFINE_COMPAT_TABLE(tablename) \
1194     char tablename[IPS_COMPAT_MAX_ADAPTER_TYPE] [IPS_COMPAT_ID_LENGTH] = { \
1195        IPS_COMPAT_UNKNOWN, \
1196        IPS_COMPAT_SERVERAID1, \
1197        IPS_COMPAT_SERVERAID2, \
1198        IPS_COMPAT_NAVAJO, \
1199        IPS_COMPAT_KIOWA, \
1200        IPS_COMPAT_SERVERAID3H, \
1201        IPS_COMPAT_SERVERAID3L, \
1202        IPS_COMPAT_SERVERAID4H, \
1203        IPS_COMPAT_SERVERAID4M, \
1204        IPS_COMPAT_SERVERAID4L, \
1205        IPS_COMPAT_SERVERAID4Mx, \
1206        IPS_COMPAT_SERVERAID4Lx, \
1207        IPS_COMPAT_SARASOTA,         /* one-channel variety of SARASOTA */  \
1208        IPS_COMPAT_SARASOTA,         /* two-channel variety of SARASOTA */  \
1209        IPS_COMPAT_MARCO, \
1210        IPS_COMPAT_SEBRING, \
1211        IPS_COMPAT_TAMPA, \
1212        IPS_COMPAT_KEYWEST \
1213     }
1214