1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
4 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 /* Disable MMIO tracing to prevent excessive logging of unwanted MMIO traces */
8 #define __DISABLE_TRACE_MMIO__
9
10 #include <linux/clk.h>
11 #include <linux/console.h>
12 #include <linux/io.h>
13 #include <linux/iopoll.h>
14 #include <linux/irq.h>
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/of.h>
18 #include <linux/of_device.h>
19 #include <linux/pm_opp.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/pm_wakeirq.h>
23 #include <linux/qcom-geni-se.h>
24 #include <linux/serial.h>
25 #include <linux/serial_core.h>
26 #include <linux/slab.h>
27 #include <linux/tty.h>
28 #include <linux/tty_flip.h>
29 #include <linux/pinctrl/consumer.h>
30
31 static bool con_enabled = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE_DEFAULT_ENABLED);
32 module_param(con_enabled, bool, 0644);
33
34 /* UART specific GENI registers */
35 #define SE_UART_LOOPBACK_CFG 0x22c
36 #define SE_UART_IO_MACRO_CTRL 0x240
37 #define SE_UART_TX_TRANS_CFG 0x25c
38 #define SE_UART_TX_WORD_LEN 0x268
39 #define SE_UART_TX_STOP_BIT_LEN 0x26c
40 #define SE_UART_TX_TRANS_LEN 0x270
41 #define SE_UART_RX_TRANS_CFG 0x280
42 #define SE_UART_RX_WORD_LEN 0x28c
43 #define SE_UART_RX_STALE_CNT 0x294
44 #define SE_UART_TX_PARITY_CFG 0x2a4
45 #define SE_UART_RX_PARITY_CFG 0x2a8
46 #define SE_UART_MANUAL_RFR 0x2ac
47
48 /* SE_UART_TRANS_CFG */
49 #define UART_TX_PAR_EN BIT(0)
50 #define UART_CTS_MASK BIT(1)
51
52 /* SE_UART_TX_WORD_LEN */
53 #define TX_WORD_LEN_MSK GENMASK(9, 0)
54
55 /* SE_UART_TX_STOP_BIT_LEN */
56 #define TX_STOP_BIT_LEN_MSK GENMASK(23, 0)
57 #define TX_STOP_BIT_LEN_1 0
58 #define TX_STOP_BIT_LEN_1_5 1
59 #define TX_STOP_BIT_LEN_2 2
60
61 /* SE_UART_TX_TRANS_LEN */
62 #define TX_TRANS_LEN_MSK GENMASK(23, 0)
63
64 /* SE_UART_RX_TRANS_CFG */
65 #define UART_RX_INS_STATUS_BIT BIT(2)
66 #define UART_RX_PAR_EN BIT(3)
67
68 /* SE_UART_RX_WORD_LEN */
69 #define RX_WORD_LEN_MASK GENMASK(9, 0)
70
71 /* SE_UART_RX_STALE_CNT */
72 #define RX_STALE_CNT GENMASK(23, 0)
73
74 /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */
75 #define PAR_CALC_EN BIT(0)
76 #define PAR_MODE_MSK GENMASK(2, 1)
77 #define PAR_MODE_SHFT 1
78 #define PAR_EVEN 0x00
79 #define PAR_ODD 0x01
80 #define PAR_SPACE 0x10
81 #define PAR_MARK 0x11
82
83 /* SE_UART_MANUAL_RFR register fields */
84 #define UART_MANUAL_RFR_EN BIT(31)
85 #define UART_RFR_NOT_READY BIT(1)
86 #define UART_RFR_READY BIT(0)
87
88 /* UART M_CMD OP codes */
89 #define UART_START_TX 0x1
90 #define UART_START_BREAK 0x4
91 #define UART_STOP_BREAK 0x5
92 /* UART S_CMD OP codes */
93 #define UART_START_READ 0x1
94 #define UART_PARAM 0x1
95
96 #define UART_OVERSAMPLING 32
97 #define STALE_TIMEOUT 16
98 #define DEFAULT_BITS_PER_CHAR 10
99 #define GENI_UART_CONS_PORTS 1
100 #define GENI_UART_PORTS 3
101 #define DEF_FIFO_DEPTH_WORDS 16
102 #define DEF_TX_WM 2
103 #define DEF_FIFO_WIDTH_BITS 32
104 #define UART_RX_WM 2
105
106 /* SE_UART_LOOPBACK_CFG */
107 #define RX_TX_SORTED BIT(0)
108 #define CTS_RTS_SORTED BIT(1)
109 #define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED)
110
111 /* UART pin swap value */
112 #define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0)
113 #define IO_MACRO_IO0_SEL 0x3
114 #define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4)
115 #define IO_MACRO_IO2_IO3_SWAP 0x4640
116
117 /* We always configure 4 bytes per FIFO word */
118 #define BYTES_PER_FIFO_WORD 4
119
120 struct qcom_geni_private_data {
121 /* NOTE: earlycon port will have NULL here */
122 struct uart_driver *drv;
123
124 u32 poll_cached_bytes;
125 unsigned int poll_cached_bytes_cnt;
126
127 u32 write_cached_bytes;
128 unsigned int write_cached_bytes_cnt;
129 };
130
131 struct qcom_geni_serial_port {
132 struct uart_port uport;
133 struct geni_se se;
134 const char *name;
135 u32 tx_fifo_depth;
136 u32 tx_fifo_width;
137 u32 rx_fifo_depth;
138 bool setup;
139 unsigned long clk_rate;
140 int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop);
141 unsigned int baud;
142 void *rx_fifo;
143 u32 loopback;
144 bool brk;
145
146 unsigned int tx_remaining;
147 int wakeup_irq;
148 bool rx_tx_swap;
149 bool cts_rts_swap;
150 bool is_console;
151
152 struct qcom_geni_private_data private_data;
153 };
154
155 static const struct uart_ops qcom_geni_console_pops;
156 static const struct uart_ops qcom_geni_uart_pops;
157 static struct uart_driver qcom_geni_console_driver;
158 static struct uart_driver qcom_geni_uart_driver;
159 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop);
160 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop);
161 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port);
162 static void qcom_geni_serial_stop_rx(struct uart_port *uport);
163 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop);
164
165 static const unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200,
166 32000000, 48000000, 51200000, 64000000,
167 80000000, 96000000, 100000000,
168 102400000, 112000000, 120000000,
169 128000000};
170
171 #define to_dev_port(ptr, member) \
172 container_of(ptr, struct qcom_geni_serial_port, member)
173
174 static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = {
175 [0] = {
176 .uport = {
177 .iotype = UPIO_MEM,
178 .ops = &qcom_geni_uart_pops,
179 .flags = UPF_BOOT_AUTOCONF,
180 .line = 0,
181 },
182 },
183 [1] = {
184 .uport = {
185 .iotype = UPIO_MEM,
186 .ops = &qcom_geni_uart_pops,
187 .flags = UPF_BOOT_AUTOCONF,
188 .line = 1,
189 },
190 },
191 [2] = {
192 .uport = {
193 .iotype = UPIO_MEM,
194 .ops = &qcom_geni_uart_pops,
195 .flags = UPF_BOOT_AUTOCONF,
196 .line = 2,
197 },
198 },
199 };
200
201 static struct qcom_geni_serial_port qcom_geni_console_port = {
202 .uport = {
203 .iotype = UPIO_MEM,
204 .ops = &qcom_geni_console_pops,
205 .flags = UPF_BOOT_AUTOCONF,
206 .line = 0,
207 },
208 };
209
qcom_geni_serial_request_port(struct uart_port * uport)210 static int qcom_geni_serial_request_port(struct uart_port *uport)
211 {
212 struct platform_device *pdev = to_platform_device(uport->dev);
213 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
214
215 uport->membase = devm_platform_ioremap_resource(pdev, 0);
216 if (IS_ERR(uport->membase))
217 return PTR_ERR(uport->membase);
218 port->se.base = uport->membase;
219 return 0;
220 }
221
qcom_geni_serial_config_port(struct uart_port * uport,int cfg_flags)222 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
223 {
224 if (cfg_flags & UART_CONFIG_TYPE) {
225 uport->type = PORT_MSM;
226 qcom_geni_serial_request_port(uport);
227 }
228 }
229
qcom_geni_serial_get_mctrl(struct uart_port * uport)230 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport)
231 {
232 unsigned int mctrl = TIOCM_DSR | TIOCM_CAR;
233 u32 geni_ios;
234
235 if (uart_console(uport)) {
236 mctrl |= TIOCM_CTS;
237 } else {
238 geni_ios = readl(uport->membase + SE_GENI_IOS);
239 if (!(geni_ios & IO2_DATA_IN))
240 mctrl |= TIOCM_CTS;
241 }
242
243 return mctrl;
244 }
245
qcom_geni_serial_set_mctrl(struct uart_port * uport,unsigned int mctrl)246 static void qcom_geni_serial_set_mctrl(struct uart_port *uport,
247 unsigned int mctrl)
248 {
249 u32 uart_manual_rfr = 0;
250 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
251
252 if (uart_console(uport))
253 return;
254
255 if (mctrl & TIOCM_LOOP)
256 port->loopback = RX_TX_CTS_RTS_SORTED;
257
258 if (!(mctrl & TIOCM_RTS) && !uport->suspended)
259 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY;
260 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);
261 }
262
qcom_geni_serial_get_type(struct uart_port * uport)263 static const char *qcom_geni_serial_get_type(struct uart_port *uport)
264 {
265 return "MSM";
266 }
267
get_port_from_line(int line,bool console)268 static struct qcom_geni_serial_port *get_port_from_line(int line, bool console)
269 {
270 struct qcom_geni_serial_port *port;
271 int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS;
272
273 if (line < 0 || line >= nr_ports)
274 return ERR_PTR(-ENXIO);
275
276 port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line];
277 return port;
278 }
279
qcom_geni_serial_poll_bit(struct uart_port * uport,int offset,int field,bool set)280 static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
281 int offset, int field, bool set)
282 {
283 u32 reg;
284 struct qcom_geni_serial_port *port;
285 unsigned int baud;
286 unsigned int fifo_bits;
287 unsigned long timeout_us = 20000;
288 struct qcom_geni_private_data *private_data = uport->private_data;
289
290 if (private_data->drv) {
291 port = to_dev_port(uport, uport);
292 baud = port->baud;
293 if (!baud)
294 baud = 115200;
295 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
296 /*
297 * Total polling iterations based on FIFO worth of bytes to be
298 * sent at current baud. Add a little fluff to the wait.
299 */
300 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
301 }
302
303 /*
304 * Use custom implementation instead of readl_poll_atomic since ktimer
305 * is not ready at the time of early console.
306 */
307 timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10;
308 while (timeout_us) {
309 reg = readl(uport->membase + offset);
310 if ((bool)(reg & field) == set)
311 return true;
312 udelay(10);
313 timeout_us -= 10;
314 }
315 return false;
316 }
317
qcom_geni_serial_setup_tx(struct uart_port * uport,u32 xmit_size)318 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
319 {
320 u32 m_cmd;
321
322 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
323 m_cmd = UART_START_TX << M_OPCODE_SHFT;
324 writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
325 }
326
qcom_geni_serial_poll_tx_done(struct uart_port * uport)327 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
328 {
329 int done;
330 u32 irq_clear = M_CMD_DONE_EN;
331
332 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
333 M_CMD_DONE_EN, true);
334 if (!done) {
335 writel(M_GENI_CMD_ABORT, uport->membase +
336 SE_GENI_M_CMD_CTRL_REG);
337 irq_clear |= M_CMD_ABORT_EN;
338 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
339 M_CMD_ABORT_EN, true);
340 }
341 writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
342 }
343
qcom_geni_serial_abort_rx(struct uart_port * uport)344 static void qcom_geni_serial_abort_rx(struct uart_port *uport)
345 {
346 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
347
348 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
349 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
350 S_GENI_CMD_ABORT, false);
351 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
352 writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
353 }
354
355 #ifdef CONFIG_CONSOLE_POLL
356
qcom_geni_serial_get_char(struct uart_port * uport)357 static int qcom_geni_serial_get_char(struct uart_port *uport)
358 {
359 struct qcom_geni_private_data *private_data = uport->private_data;
360 u32 status;
361 u32 word_cnt;
362 int ret;
363
364 if (!private_data->poll_cached_bytes_cnt) {
365 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
366 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
367
368 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
369 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
370
371 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
372 word_cnt = status & RX_FIFO_WC_MSK;
373 if (!word_cnt)
374 return NO_POLL_CHAR;
375
376 if (word_cnt == 1 && (status & RX_LAST))
377 /*
378 * NOTE: If RX_LAST_BYTE_VALID is 0 it needs to be
379 * treated as if it was BYTES_PER_FIFO_WORD.
380 */
381 private_data->poll_cached_bytes_cnt =
382 (status & RX_LAST_BYTE_VALID_MSK) >>
383 RX_LAST_BYTE_VALID_SHFT;
384
385 if (private_data->poll_cached_bytes_cnt == 0)
386 private_data->poll_cached_bytes_cnt = BYTES_PER_FIFO_WORD;
387
388 private_data->poll_cached_bytes =
389 readl(uport->membase + SE_GENI_RX_FIFOn);
390 }
391
392 private_data->poll_cached_bytes_cnt--;
393 ret = private_data->poll_cached_bytes & 0xff;
394 private_data->poll_cached_bytes >>= 8;
395
396 return ret;
397 }
398
qcom_geni_serial_poll_put_char(struct uart_port * uport,unsigned char c)399 static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
400 unsigned char c)
401 {
402 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
403 qcom_geni_serial_setup_tx(uport, 1);
404 WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
405 M_TX_FIFO_WATERMARK_EN, true));
406 writel(c, uport->membase + SE_GENI_TX_FIFOn);
407 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
408 qcom_geni_serial_poll_tx_done(uport);
409 }
410 #endif
411
412 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
qcom_geni_serial_wr_char(struct uart_port * uport,int ch)413 static void qcom_geni_serial_wr_char(struct uart_port *uport, int ch)
414 {
415 struct qcom_geni_private_data *private_data = uport->private_data;
416
417 private_data->write_cached_bytes =
418 (private_data->write_cached_bytes >> 8) | (ch << 24);
419 private_data->write_cached_bytes_cnt++;
420
421 if (private_data->write_cached_bytes_cnt == BYTES_PER_FIFO_WORD) {
422 writel(private_data->write_cached_bytes,
423 uport->membase + SE_GENI_TX_FIFOn);
424 private_data->write_cached_bytes_cnt = 0;
425 }
426 }
427
428 static void
__qcom_geni_serial_console_write(struct uart_port * uport,const char * s,unsigned int count)429 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
430 unsigned int count)
431 {
432 struct qcom_geni_private_data *private_data = uport->private_data;
433
434 int i;
435 u32 bytes_to_send = count;
436
437 for (i = 0; i < count; i++) {
438 /*
439 * uart_console_write() adds a carriage return for each newline.
440 * Account for additional bytes to be written.
441 */
442 if (s[i] == '\n')
443 bytes_to_send++;
444 }
445
446 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
447 qcom_geni_serial_setup_tx(uport, bytes_to_send);
448 for (i = 0; i < count; ) {
449 size_t chars_to_write = 0;
450 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM;
451
452 /*
453 * If the WM bit never set, then the Tx state machine is not
454 * in a valid state, so break, cancel/abort any existing
455 * command. Unfortunately the current data being written is
456 * lost.
457 */
458 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
459 M_TX_FIFO_WATERMARK_EN, true))
460 break;
461 chars_to_write = min_t(size_t, count - i, avail / 2);
462 uart_console_write(uport, s + i, chars_to_write,
463 qcom_geni_serial_wr_char);
464 writel(M_TX_FIFO_WATERMARK_EN, uport->membase +
465 SE_GENI_M_IRQ_CLEAR);
466 i += chars_to_write;
467 }
468
469 if (private_data->write_cached_bytes_cnt) {
470 private_data->write_cached_bytes >>= BITS_PER_BYTE *
471 (BYTES_PER_FIFO_WORD - private_data->write_cached_bytes_cnt);
472 writel(private_data->write_cached_bytes,
473 uport->membase + SE_GENI_TX_FIFOn);
474 private_data->write_cached_bytes_cnt = 0;
475 }
476
477 qcom_geni_serial_poll_tx_done(uport);
478 }
479
qcom_geni_serial_console_write(struct console * co,const char * s,unsigned int count)480 static void qcom_geni_serial_console_write(struct console *co, const char *s,
481 unsigned int count)
482 {
483 struct uart_port *uport;
484 struct qcom_geni_serial_port *port;
485 bool locked = true;
486 unsigned long flags;
487 u32 geni_status;
488 u32 irq_en;
489
490 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS);
491
492 port = get_port_from_line(co->index, true);
493 if (IS_ERR(port))
494 return;
495
496 uport = &port->uport;
497 if (oops_in_progress)
498 locked = spin_trylock_irqsave(&uport->lock, flags);
499 else
500 spin_lock_irqsave(&uport->lock, flags);
501
502 geni_status = readl(uport->membase + SE_GENI_STATUS);
503
504 /* Cancel the current write to log the fault */
505 if (!locked) {
506 geni_se_cancel_m_cmd(&port->se);
507 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
508 M_CMD_CANCEL_EN, true)) {
509 geni_se_abort_m_cmd(&port->se);
510 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
511 M_CMD_ABORT_EN, true);
512 writel(M_CMD_ABORT_EN, uport->membase +
513 SE_GENI_M_IRQ_CLEAR);
514 }
515 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
516 } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) {
517 /*
518 * It seems we can't interrupt existing transfers if all data
519 * has been sent, in which case we need to look for done first.
520 */
521 qcom_geni_serial_poll_tx_done(uport);
522
523 if (uart_circ_chars_pending(&uport->state->xmit)) {
524 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
525 writel(irq_en | M_TX_FIFO_WATERMARK_EN,
526 uport->membase + SE_GENI_M_IRQ_EN);
527 }
528 }
529
530 __qcom_geni_serial_console_write(uport, s, count);
531
532 if (port->tx_remaining)
533 qcom_geni_serial_setup_tx(uport, port->tx_remaining);
534
535 if (locked)
536 spin_unlock_irqrestore(&uport->lock, flags);
537 }
538
handle_rx_console(struct uart_port * uport,u32 bytes,bool drop)539 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
540 {
541 u32 i;
542 unsigned char buf[sizeof(u32)];
543 struct tty_port *tport;
544 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
545
546 tport = &uport->state->port;
547 for (i = 0; i < bytes; ) {
548 int c;
549 int chunk = min_t(int, bytes - i, BYTES_PER_FIFO_WORD);
550
551 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
552 i += chunk;
553 if (drop)
554 continue;
555
556 for (c = 0; c < chunk; c++) {
557 int sysrq;
558
559 uport->icount.rx++;
560 if (port->brk && buf[c] == 0) {
561 port->brk = false;
562 if (uart_handle_break(uport))
563 continue;
564 }
565
566 sysrq = uart_prepare_sysrq_char(uport, buf[c]);
567
568 if (!sysrq)
569 tty_insert_flip_char(tport, buf[c], TTY_NORMAL);
570 }
571 }
572 if (!drop)
573 tty_flip_buffer_push(tport);
574 return 0;
575 }
576 #else
handle_rx_console(struct uart_port * uport,u32 bytes,bool drop)577 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
578 {
579 return -EPERM;
580 }
581
582 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
583
handle_rx_uart(struct uart_port * uport,u32 bytes,bool drop)584 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop)
585 {
586 struct tty_port *tport;
587 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
588 u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE;
589 u32 words = ALIGN(bytes, num_bytes_pw) / num_bytes_pw;
590 int ret;
591
592 tport = &uport->state->port;
593 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words);
594 if (drop)
595 return 0;
596
597 ret = tty_insert_flip_string(tport, port->rx_fifo, bytes);
598 if (ret != bytes) {
599 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n",
600 __func__, ret, bytes);
601 WARN_ON_ONCE(1);
602 }
603 uport->icount.rx += ret;
604 tty_flip_buffer_push(tport);
605 return ret;
606 }
607
qcom_geni_serial_start_tx(struct uart_port * uport)608 static void qcom_geni_serial_start_tx(struct uart_port *uport)
609 {
610 u32 irq_en;
611 u32 status;
612
613 status = readl(uport->membase + SE_GENI_STATUS);
614 if (status & M_GENI_CMD_ACTIVE)
615 return;
616
617 if (!qcom_geni_serial_tx_empty(uport))
618 return;
619
620 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
621 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
622
623 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
624 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
625 }
626
qcom_geni_serial_stop_tx(struct uart_port * uport)627 static void qcom_geni_serial_stop_tx(struct uart_port *uport)
628 {
629 u32 irq_en;
630 u32 status;
631 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
632
633 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
634 irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
635 writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG);
636 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
637 status = readl(uport->membase + SE_GENI_STATUS);
638 /* Possible stop tx is called multiple times. */
639 if (!(status & M_GENI_CMD_ACTIVE))
640 return;
641
642 geni_se_cancel_m_cmd(&port->se);
643 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
644 M_CMD_CANCEL_EN, true)) {
645 geni_se_abort_m_cmd(&port->se);
646 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
647 M_CMD_ABORT_EN, true);
648 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
649 }
650 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
651 }
652
qcom_geni_serial_start_rx(struct uart_port * uport)653 static void qcom_geni_serial_start_rx(struct uart_port *uport)
654 {
655 u32 irq_en;
656 u32 status;
657 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
658
659 status = readl(uport->membase + SE_GENI_STATUS);
660 if (status & S_GENI_CMD_ACTIVE)
661 qcom_geni_serial_stop_rx(uport);
662
663 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
664
665 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
666 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN;
667 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
668
669 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
670 irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
671 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
672 }
673
qcom_geni_serial_stop_rx(struct uart_port * uport)674 static void qcom_geni_serial_stop_rx(struct uart_port *uport)
675 {
676 u32 irq_en;
677 u32 status;
678 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
679 u32 s_irq_status;
680
681 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
682 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
683 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
684
685 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
686 irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
687 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
688
689 status = readl(uport->membase + SE_GENI_STATUS);
690 /* Possible stop rx is called multiple times. */
691 if (!(status & S_GENI_CMD_ACTIVE))
692 return;
693
694 geni_se_cancel_s_cmd(&port->se);
695 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS,
696 S_CMD_CANCEL_EN, true);
697 /*
698 * If timeout occurs secondary engine remains active
699 * and Abort sequence is executed.
700 */
701 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
702 /* Flush the Rx buffer */
703 if (s_irq_status & S_RX_FIFO_LAST_EN)
704 qcom_geni_serial_handle_rx(uport, true);
705 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
706
707 status = readl(uport->membase + SE_GENI_STATUS);
708 if (status & S_GENI_CMD_ACTIVE)
709 qcom_geni_serial_abort_rx(uport);
710 }
711
qcom_geni_serial_handle_rx(struct uart_port * uport,bool drop)712 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop)
713 {
714 u32 status;
715 u32 word_cnt;
716 u32 last_word_byte_cnt;
717 u32 last_word_partial;
718 u32 total_bytes;
719 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
720
721 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
722 word_cnt = status & RX_FIFO_WC_MSK;
723 last_word_partial = status & RX_LAST;
724 last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >>
725 RX_LAST_BYTE_VALID_SHFT;
726
727 if (!word_cnt)
728 return;
729 total_bytes = BYTES_PER_FIFO_WORD * (word_cnt - 1);
730 if (last_word_partial && last_word_byte_cnt)
731 total_bytes += last_word_byte_cnt;
732 else
733 total_bytes += BYTES_PER_FIFO_WORD;
734 port->handle_rx(uport, total_bytes, drop);
735 }
736
qcom_geni_serial_handle_tx(struct uart_port * uport,bool done,bool active)737 static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done,
738 bool active)
739 {
740 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
741 struct circ_buf *xmit = &uport->state->xmit;
742 size_t avail;
743 size_t remaining;
744 size_t pending;
745 int i;
746 u32 status;
747 u32 irq_en;
748 unsigned int chunk;
749 int tail;
750
751 status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
752
753 /* Complete the current tx command before taking newly added data */
754 if (active)
755 pending = port->tx_remaining;
756 else
757 pending = uart_circ_chars_pending(xmit);
758
759 /* All data has been transmitted and acknowledged as received */
760 if (!pending && !status && done) {
761 qcom_geni_serial_stop_tx(uport);
762 goto out_write_wakeup;
763 }
764
765 avail = port->tx_fifo_depth - (status & TX_FIFO_WC);
766 avail *= BYTES_PER_FIFO_WORD;
767
768 tail = xmit->tail;
769 chunk = min(avail, pending);
770 if (!chunk)
771 goto out_write_wakeup;
772
773 if (!port->tx_remaining) {
774 qcom_geni_serial_setup_tx(uport, pending);
775 port->tx_remaining = pending;
776
777 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
778 if (!(irq_en & M_TX_FIFO_WATERMARK_EN))
779 writel(irq_en | M_TX_FIFO_WATERMARK_EN,
780 uport->membase + SE_GENI_M_IRQ_EN);
781 }
782
783 remaining = chunk;
784 for (i = 0; i < chunk; ) {
785 unsigned int tx_bytes;
786 u8 buf[sizeof(u32)];
787 int c;
788
789 memset(buf, 0, sizeof(buf));
790 tx_bytes = min_t(size_t, remaining, BYTES_PER_FIFO_WORD);
791
792 for (c = 0; c < tx_bytes ; c++) {
793 buf[c] = xmit->buf[tail++];
794 tail &= UART_XMIT_SIZE - 1;
795 }
796
797 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
798
799 i += tx_bytes;
800 uport->icount.tx += tx_bytes;
801 remaining -= tx_bytes;
802 port->tx_remaining -= tx_bytes;
803 }
804
805 xmit->tail = tail;
806
807 /*
808 * The tx fifo watermark is level triggered and latched. Though we had
809 * cleared it in qcom_geni_serial_isr it will have already reasserted
810 * so we must clear it again here after our writes.
811 */
812 writel(M_TX_FIFO_WATERMARK_EN,
813 uport->membase + SE_GENI_M_IRQ_CLEAR);
814
815 out_write_wakeup:
816 if (!port->tx_remaining) {
817 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
818 if (irq_en & M_TX_FIFO_WATERMARK_EN)
819 writel(irq_en & ~M_TX_FIFO_WATERMARK_EN,
820 uport->membase + SE_GENI_M_IRQ_EN);
821 }
822
823 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
824 uart_write_wakeup(uport);
825 }
826
qcom_geni_serial_isr(int isr,void * dev)827 static irqreturn_t qcom_geni_serial_isr(int isr, void *dev)
828 {
829 u32 m_irq_en;
830 u32 m_irq_status;
831 u32 s_irq_status;
832 u32 geni_status;
833 struct uart_port *uport = dev;
834 bool drop_rx = false;
835 struct tty_port *tport = &uport->state->port;
836 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
837
838 if (uport->suspended)
839 return IRQ_NONE;
840
841 spin_lock(&uport->lock);
842
843 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
844 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
845 geni_status = readl(uport->membase + SE_GENI_STATUS);
846 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
847 writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
848 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
849
850 if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN))
851 goto out_unlock;
852
853 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) {
854 uport->icount.overrun++;
855 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
856 }
857
858 if (m_irq_status & m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN))
859 qcom_geni_serial_handle_tx(uport, m_irq_status & M_CMD_DONE_EN,
860 geni_status & M_GENI_CMD_ACTIVE);
861
862 if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) {
863 if (s_irq_status & S_GP_IRQ_0_EN)
864 uport->icount.parity++;
865 drop_rx = true;
866 } else if (s_irq_status & S_GP_IRQ_2_EN ||
867 s_irq_status & S_GP_IRQ_3_EN) {
868 uport->icount.brk++;
869 port->brk = true;
870 }
871
872 if (s_irq_status & S_RX_FIFO_WATERMARK_EN ||
873 s_irq_status & S_RX_FIFO_LAST_EN)
874 qcom_geni_serial_handle_rx(uport, drop_rx);
875
876 out_unlock:
877 uart_unlock_and_check_sysrq(uport);
878
879 return IRQ_HANDLED;
880 }
881
setup_fifos(struct qcom_geni_serial_port * port)882 static int setup_fifos(struct qcom_geni_serial_port *port)
883 {
884 struct uart_port *uport;
885 u32 old_rx_fifo_depth = port->rx_fifo_depth;
886
887 uport = &port->uport;
888 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
889 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
890 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
891 uport->fifosize =
892 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE;
893
894 if (port->rx_fifo && (old_rx_fifo_depth != port->rx_fifo_depth) && port->rx_fifo_depth) {
895 port->rx_fifo = devm_krealloc(uport->dev, port->rx_fifo,
896 port->rx_fifo_depth * sizeof(u32),
897 GFP_KERNEL);
898 if (!port->rx_fifo)
899 return -ENOMEM;
900 }
901
902 return 0;
903 }
904
905
qcom_geni_serial_shutdown(struct uart_port * uport)906 static void qcom_geni_serial_shutdown(struct uart_port *uport)
907 {
908 disable_irq(uport->irq);
909 }
910
qcom_geni_serial_port_setup(struct uart_port * uport)911 static int qcom_geni_serial_port_setup(struct uart_port *uport)
912 {
913 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
914 u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
915 u32 proto;
916 u32 pin_swap;
917 int ret;
918
919 proto = geni_se_read_proto(&port->se);
920 if (proto != GENI_SE_UART) {
921 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
922 return -ENXIO;
923 }
924
925 qcom_geni_serial_stop_rx(uport);
926
927 ret = setup_fifos(port);
928 if (ret)
929 return ret;
930
931 writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
932
933 pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL);
934 if (port->rx_tx_swap) {
935 pin_swap &= ~DEFAULT_IO_MACRO_IO2_IO3_MASK;
936 pin_swap |= IO_MACRO_IO2_IO3_SWAP;
937 }
938 if (port->cts_rts_swap) {
939 pin_swap &= ~DEFAULT_IO_MACRO_IO0_IO1_MASK;
940 pin_swap |= IO_MACRO_IO0_SEL;
941 }
942 /* Configure this register if RX-TX, CTS-RTS pins are swapped */
943 if (port->rx_tx_swap || port->cts_rts_swap)
944 writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL);
945
946 /*
947 * Make an unconditional cancel on the main sequencer to reset
948 * it else we could end up in data loss scenarios.
949 */
950 if (uart_console(uport))
951 qcom_geni_serial_poll_tx_done(uport);
952 geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,
953 false, true, true);
954 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2);
955 geni_se_select_mode(&port->se, GENI_SE_FIFO);
956 port->setup = true;
957
958 return 0;
959 }
960
qcom_geni_serial_startup(struct uart_port * uport)961 static int qcom_geni_serial_startup(struct uart_port *uport)
962 {
963 int ret;
964 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
965
966 if (!port->setup) {
967 ret = qcom_geni_serial_port_setup(uport);
968 if (ret)
969 return ret;
970 }
971 enable_irq(uport->irq);
972
973 return 0;
974 }
975
get_clk_cfg(unsigned long clk_freq)976 static unsigned long get_clk_cfg(unsigned long clk_freq)
977 {
978 int i;
979
980 for (i = 0; i < ARRAY_SIZE(root_freq); i++) {
981 if (!(root_freq[i] % clk_freq))
982 return root_freq[i];
983 }
984 return 0;
985 }
986
get_clk_div_rate(unsigned int baud,unsigned int sampling_rate,unsigned int * clk_div)987 static unsigned long get_clk_div_rate(unsigned int baud,
988 unsigned int sampling_rate, unsigned int *clk_div)
989 {
990 unsigned long ser_clk;
991 unsigned long desired_clk;
992
993 desired_clk = baud * sampling_rate;
994 ser_clk = get_clk_cfg(desired_clk);
995 if (!ser_clk) {
996 pr_err("%s: Can't find matching DFS entry for baud %d\n",
997 __func__, baud);
998 return ser_clk;
999 }
1000
1001 *clk_div = ser_clk / desired_clk;
1002 return ser_clk;
1003 }
1004
qcom_geni_serial_set_termios(struct uart_port * uport,struct ktermios * termios,struct ktermios * old)1005 static void qcom_geni_serial_set_termios(struct uart_port *uport,
1006 struct ktermios *termios, struct ktermios *old)
1007 {
1008 unsigned int baud;
1009 u32 bits_per_char;
1010 u32 tx_trans_cfg;
1011 u32 tx_parity_cfg;
1012 u32 rx_trans_cfg;
1013 u32 rx_parity_cfg;
1014 u32 stop_bit_len;
1015 unsigned int clk_div;
1016 u32 ser_clk_cfg;
1017 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1018 unsigned long clk_rate;
1019 u32 ver, sampling_rate;
1020 unsigned int avg_bw_core;
1021
1022 qcom_geni_serial_stop_rx(uport);
1023 /* baud rate */
1024 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
1025 port->baud = baud;
1026
1027 sampling_rate = UART_OVERSAMPLING;
1028 /* Sampling rate is halved for IP versions >= 2.5 */
1029 ver = geni_se_get_qup_hw_version(&port->se);
1030 if (ver >= QUP_SE_VERSION_2_5)
1031 sampling_rate /= 2;
1032
1033 clk_rate = get_clk_div_rate(baud, sampling_rate, &clk_div);
1034 if (!clk_rate)
1035 goto out_restart_rx;
1036
1037 uport->uartclk = clk_rate;
1038 port->clk_rate = clk_rate;
1039 dev_pm_opp_set_rate(uport->dev, clk_rate);
1040 ser_clk_cfg = SER_CLK_EN;
1041 ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
1042
1043 /*
1044 * Bump up BW vote on CPU and CORE path as driver supports FIFO mode
1045 * only.
1046 */
1047 avg_bw_core = (baud > 115200) ? Bps_to_icc(CORE_2X_50_MHZ)
1048 : GENI_DEFAULT_BW;
1049 port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core;
1050 port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud);
1051 geni_icc_set_bw(&port->se);
1052
1053 /* parity */
1054 tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
1055 tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
1056 rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG);
1057 rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG);
1058 if (termios->c_cflag & PARENB) {
1059 tx_trans_cfg |= UART_TX_PAR_EN;
1060 rx_trans_cfg |= UART_RX_PAR_EN;
1061 tx_parity_cfg |= PAR_CALC_EN;
1062 rx_parity_cfg |= PAR_CALC_EN;
1063 if (termios->c_cflag & PARODD) {
1064 tx_parity_cfg |= PAR_ODD;
1065 rx_parity_cfg |= PAR_ODD;
1066 } else if (termios->c_cflag & CMSPAR) {
1067 tx_parity_cfg |= PAR_SPACE;
1068 rx_parity_cfg |= PAR_SPACE;
1069 } else {
1070 tx_parity_cfg |= PAR_EVEN;
1071 rx_parity_cfg |= PAR_EVEN;
1072 }
1073 } else {
1074 tx_trans_cfg &= ~UART_TX_PAR_EN;
1075 rx_trans_cfg &= ~UART_RX_PAR_EN;
1076 tx_parity_cfg &= ~PAR_CALC_EN;
1077 rx_parity_cfg &= ~PAR_CALC_EN;
1078 }
1079
1080 /* bits per char */
1081 bits_per_char = tty_get_char_size(termios->c_cflag);
1082
1083 /* stop bits */
1084 if (termios->c_cflag & CSTOPB)
1085 stop_bit_len = TX_STOP_BIT_LEN_2;
1086 else
1087 stop_bit_len = TX_STOP_BIT_LEN_1;
1088
1089 /* flow control, clear the CTS_MASK bit if using flow control. */
1090 if (termios->c_cflag & CRTSCTS)
1091 tx_trans_cfg &= ~UART_CTS_MASK;
1092 else
1093 tx_trans_cfg |= UART_CTS_MASK;
1094
1095 if (baud)
1096 uart_update_timeout(uport, termios->c_cflag, baud);
1097
1098 if (!uart_console(uport))
1099 writel(port->loopback,
1100 uport->membase + SE_UART_LOOPBACK_CFG);
1101 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1102 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1103 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1104 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1105 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1106 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1107 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1108 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
1109 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
1110 out_restart_rx:
1111 qcom_geni_serial_start_rx(uport);
1112 }
1113
qcom_geni_serial_tx_empty(struct uart_port * uport)1114 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
1115 {
1116 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
1117 }
1118
1119 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
qcom_geni_console_setup(struct console * co,char * options)1120 static int qcom_geni_console_setup(struct console *co, char *options)
1121 {
1122 struct uart_port *uport;
1123 struct qcom_geni_serial_port *port;
1124 int baud = 115200;
1125 int bits = 8;
1126 int parity = 'n';
1127 int flow = 'n';
1128 int ret;
1129
1130 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0)
1131 return -ENXIO;
1132
1133 port = get_port_from_line(co->index, true);
1134 if (IS_ERR(port)) {
1135 pr_err("Invalid line %d\n", co->index);
1136 return PTR_ERR(port);
1137 }
1138
1139 uport = &port->uport;
1140
1141 if (unlikely(!uport->membase))
1142 return -ENXIO;
1143
1144 if (!port->setup) {
1145 ret = qcom_geni_serial_port_setup(uport);
1146 if (ret)
1147 return ret;
1148 }
1149
1150 if (options)
1151 uart_parse_options(options, &baud, &parity, &bits, &flow);
1152
1153 return uart_set_options(uport, co, baud, parity, bits, flow);
1154 }
1155
qcom_geni_serial_earlycon_write(struct console * con,const char * s,unsigned int n)1156 static void qcom_geni_serial_earlycon_write(struct console *con,
1157 const char *s, unsigned int n)
1158 {
1159 struct earlycon_device *dev = con->data;
1160
1161 __qcom_geni_serial_console_write(&dev->port, s, n);
1162 }
1163
1164 #ifdef CONFIG_CONSOLE_POLL
qcom_geni_serial_earlycon_read(struct console * con,char * s,unsigned int n)1165 static int qcom_geni_serial_earlycon_read(struct console *con,
1166 char *s, unsigned int n)
1167 {
1168 struct earlycon_device *dev = con->data;
1169 struct uart_port *uport = &dev->port;
1170 int num_read = 0;
1171 int ch;
1172
1173 while (num_read < n) {
1174 ch = qcom_geni_serial_get_char(uport);
1175 if (ch == NO_POLL_CHAR)
1176 break;
1177 s[num_read++] = ch;
1178 }
1179
1180 return num_read;
1181 }
1182
qcom_geni_serial_enable_early_read(struct geni_se * se,struct console * con)1183 static void __init qcom_geni_serial_enable_early_read(struct geni_se *se,
1184 struct console *con)
1185 {
1186 geni_se_setup_s_cmd(se, UART_START_READ, 0);
1187 con->read = qcom_geni_serial_earlycon_read;
1188 }
1189 #else
qcom_geni_serial_enable_early_read(struct geni_se * se,struct console * con)1190 static inline void qcom_geni_serial_enable_early_read(struct geni_se *se,
1191 struct console *con) { }
1192 #endif
1193
1194 static struct qcom_geni_private_data earlycon_private_data;
1195
qcom_geni_serial_earlycon_setup(struct earlycon_device * dev,const char * opt)1196 static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev,
1197 const char *opt)
1198 {
1199 struct uart_port *uport = &dev->port;
1200 u32 tx_trans_cfg;
1201 u32 tx_parity_cfg = 0; /* Disable Tx Parity */
1202 u32 rx_trans_cfg = 0;
1203 u32 rx_parity_cfg = 0; /* Disable Rx Parity */
1204 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */
1205 u32 bits_per_char;
1206 struct geni_se se;
1207
1208 if (!uport->membase)
1209 return -EINVAL;
1210
1211 uport->private_data = &earlycon_private_data;
1212
1213 memset(&se, 0, sizeof(se));
1214 se.base = uport->membase;
1215 if (geni_se_read_proto(&se) != GENI_SE_UART)
1216 return -ENXIO;
1217 /*
1218 * Ignore Flow control.
1219 * n = 8.
1220 */
1221 tx_trans_cfg = UART_CTS_MASK;
1222 bits_per_char = BITS_PER_BYTE;
1223
1224 /*
1225 * Make an unconditional cancel on the main sequencer to reset
1226 * it else we could end up in data loss scenarios.
1227 */
1228 qcom_geni_serial_poll_tx_done(uport);
1229 qcom_geni_serial_abort_rx(uport);
1230 geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,
1231 false, true, true);
1232 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);
1233 geni_se_select_mode(&se, GENI_SE_FIFO);
1234
1235 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1236 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1237 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1238 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1239 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1240 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1241 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1242
1243 dev->con->write = qcom_geni_serial_earlycon_write;
1244 dev->con->setup = NULL;
1245 qcom_geni_serial_enable_early_read(&se, dev->con);
1246
1247 return 0;
1248 }
1249 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart",
1250 qcom_geni_serial_earlycon_setup);
1251
console_register(struct uart_driver * drv)1252 static int __init console_register(struct uart_driver *drv)
1253 {
1254 return uart_register_driver(drv);
1255 }
1256
console_unregister(struct uart_driver * drv)1257 static void console_unregister(struct uart_driver *drv)
1258 {
1259 uart_unregister_driver(drv);
1260 }
1261
1262 static struct console cons_ops = {
1263 .name = "ttyMSM",
1264 .write = qcom_geni_serial_console_write,
1265 .device = uart_console_device,
1266 .setup = qcom_geni_console_setup,
1267 .flags = CON_PRINTBUFFER,
1268 .index = -1,
1269 .data = &qcom_geni_console_driver,
1270 };
1271
1272 static struct uart_driver qcom_geni_console_driver = {
1273 .owner = THIS_MODULE,
1274 .driver_name = "qcom_geni_console",
1275 .dev_name = "ttyMSM",
1276 .nr = GENI_UART_CONS_PORTS,
1277 .cons = &cons_ops,
1278 };
1279 #else
console_register(struct uart_driver * drv)1280 static int console_register(struct uart_driver *drv)
1281 {
1282 return 0;
1283 }
1284
console_unregister(struct uart_driver * drv)1285 static void console_unregister(struct uart_driver *drv)
1286 {
1287 }
1288 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
1289
1290 static struct uart_driver qcom_geni_uart_driver = {
1291 .owner = THIS_MODULE,
1292 .driver_name = "qcom_geni_uart",
1293 .dev_name = "ttyHS",
1294 .nr = GENI_UART_PORTS,
1295 };
1296
qcom_geni_serial_pm(struct uart_port * uport,unsigned int new_state,unsigned int old_state)1297 static void qcom_geni_serial_pm(struct uart_port *uport,
1298 unsigned int new_state, unsigned int old_state)
1299 {
1300 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1301
1302 /* If we've never been called, treat it as off */
1303 if (old_state == UART_PM_STATE_UNDEFINED)
1304 old_state = UART_PM_STATE_OFF;
1305
1306 if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) {
1307 geni_icc_enable(&port->se);
1308 if (port->clk_rate)
1309 dev_pm_opp_set_rate(uport->dev, port->clk_rate);
1310 geni_se_resources_on(&port->se);
1311 } else if (new_state == UART_PM_STATE_OFF &&
1312 old_state == UART_PM_STATE_ON) {
1313 geni_se_resources_off(&port->se);
1314 dev_pm_opp_set_rate(uport->dev, 0);
1315 geni_icc_disable(&port->se);
1316 }
1317 }
1318
1319 static const struct uart_ops qcom_geni_console_pops = {
1320 .tx_empty = qcom_geni_serial_tx_empty,
1321 .stop_tx = qcom_geni_serial_stop_tx,
1322 .start_tx = qcom_geni_serial_start_tx,
1323 .stop_rx = qcom_geni_serial_stop_rx,
1324 .set_termios = qcom_geni_serial_set_termios,
1325 .startup = qcom_geni_serial_startup,
1326 .request_port = qcom_geni_serial_request_port,
1327 .config_port = qcom_geni_serial_config_port,
1328 .shutdown = qcom_geni_serial_shutdown,
1329 .type = qcom_geni_serial_get_type,
1330 .set_mctrl = qcom_geni_serial_set_mctrl,
1331 .get_mctrl = qcom_geni_serial_get_mctrl,
1332 #ifdef CONFIG_CONSOLE_POLL
1333 .poll_get_char = qcom_geni_serial_get_char,
1334 .poll_put_char = qcom_geni_serial_poll_put_char,
1335 #endif
1336 .pm = qcom_geni_serial_pm,
1337 };
1338
1339 static const struct uart_ops qcom_geni_uart_pops = {
1340 .tx_empty = qcom_geni_serial_tx_empty,
1341 .stop_tx = qcom_geni_serial_stop_tx,
1342 .start_tx = qcom_geni_serial_start_tx,
1343 .stop_rx = qcom_geni_serial_stop_rx,
1344 .set_termios = qcom_geni_serial_set_termios,
1345 .startup = qcom_geni_serial_startup,
1346 .request_port = qcom_geni_serial_request_port,
1347 .config_port = qcom_geni_serial_config_port,
1348 .shutdown = qcom_geni_serial_shutdown,
1349 .type = qcom_geni_serial_get_type,
1350 .set_mctrl = qcom_geni_serial_set_mctrl,
1351 .get_mctrl = qcom_geni_serial_get_mctrl,
1352 .pm = qcom_geni_serial_pm,
1353 };
1354
qcom_geni_serial_probe(struct platform_device * pdev)1355 static int qcom_geni_serial_probe(struct platform_device *pdev)
1356 {
1357 int ret = 0;
1358 int line;
1359 struct qcom_geni_serial_port *port;
1360 struct uart_port *uport;
1361 struct resource *res;
1362 int irq;
1363 bool console = false;
1364 struct uart_driver *drv;
1365
1366 if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart"))
1367 console = true;
1368
1369 if (console) {
1370 drv = &qcom_geni_console_driver;
1371 line = of_alias_get_id(pdev->dev.of_node, "serial");
1372 } else {
1373 drv = &qcom_geni_uart_driver;
1374 line = of_alias_get_id(pdev->dev.of_node, "serial");
1375 if (line == -ENODEV) /* compat with non-standard aliases */
1376 line = of_alias_get_id(pdev->dev.of_node, "hsuart");
1377 }
1378
1379 port = get_port_from_line(line, console);
1380 if (IS_ERR(port)) {
1381 dev_err(&pdev->dev, "Invalid line %d\n", line);
1382 return PTR_ERR(port);
1383 }
1384
1385 port->is_console = console;
1386
1387 if (console && !con_enabled) {
1388 dev_err(&pdev->dev, "%s, Console Disabled\n", __func__);
1389 ret = pinctrl_pm_select_sleep_state(&pdev->dev);
1390 if (ret)
1391 dev_err(&pdev->dev,
1392 "failed to set pinctrl state to sleep %d\n", ret);
1393 platform_set_drvdata(pdev, port);
1394 return ret;
1395 }
1396
1397 uport = &port->uport;
1398 /* Don't allow 2 drivers to access the same port */
1399 if (uport->private_data)
1400 return -ENODEV;
1401
1402 uport->dev = &pdev->dev;
1403 port->se.dev = &pdev->dev;
1404 port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1405 port->se.clk = devm_clk_get(&pdev->dev, "se");
1406 if (IS_ERR(port->se.clk)) {
1407 ret = PTR_ERR(port->se.clk);
1408 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
1409 return ret;
1410 }
1411
1412 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1413 if (!res)
1414 return -EINVAL;
1415 uport->mapbase = res->start;
1416
1417 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1418 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1419 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
1420
1421 if (!console) {
1422 port->rx_fifo = devm_kcalloc(uport->dev,
1423 port->rx_fifo_depth, sizeof(u32), GFP_KERNEL);
1424 if (!port->rx_fifo)
1425 return -ENOMEM;
1426 }
1427
1428 ret = geni_icc_get(&port->se, NULL);
1429 if (ret)
1430 return ret;
1431 port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
1432 port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
1433
1434 /* Set BW for register access */
1435 ret = geni_icc_set_bw(&port->se);
1436 if (ret)
1437 return ret;
1438
1439 port->name = devm_kasprintf(uport->dev, GFP_KERNEL,
1440 "qcom_geni_serial_%s%d",
1441 uart_console(uport) ? "console" : "uart", uport->line);
1442 if (!port->name)
1443 return -ENOMEM;
1444
1445 irq = platform_get_irq(pdev, 0);
1446 if (irq < 0)
1447 return irq;
1448 uport->irq = irq;
1449 uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE);
1450
1451 if (!console)
1452 port->wakeup_irq = platform_get_irq_optional(pdev, 1);
1453
1454 if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap"))
1455 port->rx_tx_swap = true;
1456
1457 if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap"))
1458 port->cts_rts_swap = true;
1459
1460 ret = devm_pm_opp_set_clkname(&pdev->dev, "se");
1461 if (ret)
1462 return ret;
1463 /* OPP table is optional */
1464 ret = devm_pm_opp_of_add_table(&pdev->dev);
1465 if (ret && ret != -ENODEV) {
1466 dev_err(&pdev->dev, "invalid OPP table in device tree\n");
1467 return ret;
1468 }
1469
1470 port->private_data.drv = drv;
1471 uport->private_data = &port->private_data;
1472 platform_set_drvdata(pdev, port);
1473 port->handle_rx = console ? handle_rx_console : handle_rx_uart;
1474
1475 irq_set_status_flags(uport->irq, IRQ_NOAUTOEN);
1476 ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr,
1477 IRQF_TRIGGER_HIGH, port->name, uport);
1478 if (ret) {
1479 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
1480 return ret;
1481 }
1482
1483 ret = uart_add_one_port(drv, uport);
1484 if (ret)
1485 return ret;
1486
1487 if (port->wakeup_irq > 0) {
1488 device_init_wakeup(&pdev->dev, true);
1489 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
1490 port->wakeup_irq);
1491 if (ret) {
1492 device_init_wakeup(&pdev->dev, false);
1493 uart_remove_one_port(drv, uport);
1494 return ret;
1495 }
1496 }
1497
1498 return 0;
1499 }
1500
qcom_geni_serial_remove(struct platform_device * pdev)1501 static int qcom_geni_serial_remove(struct platform_device *pdev)
1502 {
1503 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1504 struct uart_driver *drv = port->private_data.drv;
1505
1506 /* Platform driver is registered for console and when console
1507 * is disabled from cmdline simply return success.
1508 */
1509 if (port->is_console && !con_enabled)
1510 return 0;
1511
1512 dev_pm_clear_wake_irq(&pdev->dev);
1513 device_init_wakeup(&pdev->dev, false);
1514 uart_remove_one_port(drv, &port->uport);
1515
1516 return 0;
1517 }
1518
qcom_geni_serial_sys_suspend(struct device * dev)1519 static int __maybe_unused qcom_geni_serial_sys_suspend(struct device *dev)
1520 {
1521 struct uart_port *uport;
1522 struct qcom_geni_private_data *private_data;
1523 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1524
1525 /* Platform driver is registered for console and when console
1526 * is disabled from cmdline simply return success.
1527 */
1528 if (port->is_console && !con_enabled)
1529 return 0;
1530
1531 uport = &port->uport;
1532 private_data = uport->private_data;
1533
1534 /*
1535 * This is done so we can hit the lowest possible state in suspend
1536 * even with no_console_suspend
1537 */
1538 if (uart_console(uport)) {
1539 geni_icc_set_tag(&port->se, 0x3);
1540 geni_icc_set_bw(&port->se);
1541 }
1542 return uart_suspend_port(private_data->drv, uport);
1543 }
1544
qcom_geni_serial_sys_resume(struct device * dev)1545 static int __maybe_unused qcom_geni_serial_sys_resume(struct device *dev)
1546 {
1547 int ret;
1548 struct uart_port *uport;
1549 struct qcom_geni_private_data *private_data;
1550 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1551
1552 /* Platform driver is registered for console and when console
1553 * is disabled from cmdline simply return success.
1554 */
1555 if (port->is_console && !con_enabled)
1556 return 0;
1557
1558 uport = &port->uport;
1559 private_data = uport->private_data;
1560
1561 ret = uart_resume_port(private_data->drv, uport);
1562 if (uart_console(uport)) {
1563 geni_icc_set_tag(&port->se, 0x7);
1564 geni_icc_set_bw(&port->se);
1565 }
1566 return ret;
1567 }
1568
1569 static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
1570 SET_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend,
1571 qcom_geni_serial_sys_resume)
1572 };
1573
1574 static const struct of_device_id qcom_geni_serial_match_table[] = {
1575 { .compatible = "qcom,geni-debug-uart", },
1576 { .compatible = "qcom,geni-uart", },
1577 {}
1578 };
1579 MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);
1580
1581 static struct platform_driver qcom_geni_serial_platform_driver = {
1582 .remove = qcom_geni_serial_remove,
1583 .probe = qcom_geni_serial_probe,
1584 .driver = {
1585 .name = "qcom_geni_serial",
1586 .of_match_table = qcom_geni_serial_match_table,
1587 .pm = &qcom_geni_serial_pm_ops,
1588 },
1589 };
1590
qcom_geni_serial_init(void)1591 static int __init qcom_geni_serial_init(void)
1592 {
1593 int ret;
1594
1595 ret = uart_register_driver(&qcom_geni_uart_driver);
1596 if (ret)
1597 return ret;
1598
1599 if (con_enabled) {
1600 ret = console_register(&qcom_geni_console_driver);
1601 if (ret) {
1602 uart_unregister_driver(&qcom_geni_uart_driver);
1603 return ret;
1604 }
1605 }
1606
1607 ret = platform_driver_register(&qcom_geni_serial_platform_driver);
1608 if (ret) {
1609 if (con_enabled)
1610 console_unregister(&qcom_geni_console_driver);
1611 uart_unregister_driver(&qcom_geni_uart_driver);
1612 }
1613 return ret;
1614 }
1615 module_init(qcom_geni_serial_init);
1616
qcom_geni_serial_exit(void)1617 static void __exit qcom_geni_serial_exit(void)
1618 {
1619 platform_driver_unregister(&qcom_geni_serial_platform_driver);
1620 if (con_enabled)
1621 console_unregister(&qcom_geni_console_driver);
1622 uart_unregister_driver(&qcom_geni_uart_driver);
1623 }
1624 module_exit(qcom_geni_serial_exit);
1625
1626 MODULE_DESCRIPTION("Serial driver for GENI based QUP cores");
1627 MODULE_LICENSE("GPL v2");
1628