1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 *
4 * hda_intel.c - Implementation of primary alsa driver code base
5 * for Intel HD Audio.
6 *
7 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 *
9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
10 * PeiSen Hou <pshou@realtek.com.tw>
11 *
12 * CONTACTS:
13 *
14 * Matt Jared matt.jared@intel.com
15 * Andy Kopp andy.kopp@intel.com
16 * Dan Kogan dan.d.kogan@intel.com
17 *
18 * CHANGES:
19 *
20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
21 */
22
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/moduleparam.h>
29 #include <linux/init.h>
30 #include <linux/slab.h>
31 #include <linux/pci.h>
32 #include <linux/mutex.h>
33 #include <linux/io.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/clocksource.h>
36 #include <linux/time.h>
37 #include <linux/completion.h>
38 #include <linux/acpi.h>
39 #include <linux/pgtable.h>
40
41 #ifdef CONFIG_X86
42 /* for snoop control */
43 #include <asm/set_memory.h>
44 #include <asm/cpufeature.h>
45 #endif
46 #include <sound/core.h>
47 #include <sound/initval.h>
48 #include <sound/hdaudio.h>
49 #include <sound/hda_i915.h>
50 #include <sound/intel-dsp-config.h>
51 #include <linux/vgaarb.h>
52 #include <linux/vga_switcheroo.h>
53 #include <linux/firmware.h>
54 #include <sound/hda_codec.h>
55 #include "hda_controller.h"
56 #include "hda_intel.h"
57
58 #define CREATE_TRACE_POINTS
59 #include "hda_intel_trace.h"
60
61 /* position fix mode */
62 enum {
63 POS_FIX_AUTO,
64 POS_FIX_LPIB,
65 POS_FIX_POSBUF,
66 POS_FIX_VIACOMBO,
67 POS_FIX_COMBO,
68 POS_FIX_SKL,
69 POS_FIX_FIFO,
70 };
71
72 /* Defines for ATI HD Audio support in SB450 south bridge */
73 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
74 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
75
76 /* Defines for Nvidia HDA support */
77 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
78 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
79 #define NVIDIA_HDA_ISTRM_COH 0x4d
80 #define NVIDIA_HDA_OSTRM_COH 0x4c
81 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
82
83 /* Defines for Intel SCH HDA snoop control */
84 #define INTEL_HDA_CGCTL 0x48
85 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
86 #define INTEL_SCH_HDA_DEVC 0x78
87 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
88
89 /* Define VIA HD Audio Device ID*/
90 #define VIA_HDAC_DEVICE_ID 0x3288
91
92 /* max number of SDs */
93 /* ICH, ATI and VIA have 4 playback and 4 capture */
94 #define ICH6_NUM_CAPTURE 4
95 #define ICH6_NUM_PLAYBACK 4
96
97 /* ULI has 6 playback and 5 capture */
98 #define ULI_NUM_CAPTURE 5
99 #define ULI_NUM_PLAYBACK 6
100
101 /* ATI HDMI may have up to 8 playbacks and 0 capture */
102 #define ATIHDMI_NUM_CAPTURE 0
103 #define ATIHDMI_NUM_PLAYBACK 8
104
105 /* TERA has 4 playback and 3 capture */
106 #define TERA_NUM_CAPTURE 3
107 #define TERA_NUM_PLAYBACK 4
108
109
110 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
111 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
112 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
113 static char *model[SNDRV_CARDS];
114 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
115 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
116 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
117 static int probe_only[SNDRV_CARDS];
118 static int jackpoll_ms[SNDRV_CARDS];
119 static int single_cmd = -1;
120 static int enable_msi = -1;
121 #ifdef CONFIG_SND_HDA_PATCH_LOADER
122 static char *patch[SNDRV_CARDS];
123 #endif
124 #ifdef CONFIG_SND_HDA_INPUT_BEEP
125 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
126 CONFIG_SND_HDA_INPUT_BEEP_MODE};
127 #endif
128 static bool dmic_detect = 1;
129
130 module_param_array(index, int, NULL, 0444);
131 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
132 module_param_array(id, charp, NULL, 0444);
133 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
134 module_param_array(enable, bool, NULL, 0444);
135 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
136 module_param_array(model, charp, NULL, 0444);
137 MODULE_PARM_DESC(model, "Use the given board model.");
138 module_param_array(position_fix, int, NULL, 0444);
139 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
140 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
141 module_param_array(bdl_pos_adj, int, NULL, 0644);
142 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
143 module_param_array(probe_mask, int, NULL, 0444);
144 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
145 module_param_array(probe_only, int, NULL, 0444);
146 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
147 module_param_array(jackpoll_ms, int, NULL, 0444);
148 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
149 module_param(single_cmd, bint, 0444);
150 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
151 "(for debugging only).");
152 module_param(enable_msi, bint, 0444);
153 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
154 #ifdef CONFIG_SND_HDA_PATCH_LOADER
155 module_param_array(patch, charp, NULL, 0444);
156 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
157 #endif
158 #ifdef CONFIG_SND_HDA_INPUT_BEEP
159 module_param_array(beep_mode, bool, NULL, 0444);
160 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
161 "(0=off, 1=on) (default=1).");
162 #endif
163 module_param(dmic_detect, bool, 0444);
164 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) "
165 "(0=off, 1=on) (default=1); "
166 "deprecated, use snd-intel-dspcfg.dsp_driver option instead");
167
168 #ifdef CONFIG_PM
169 static int param_set_xint(const char *val, const struct kernel_param *kp);
170 static const struct kernel_param_ops param_ops_xint = {
171 .set = param_set_xint,
172 .get = param_get_int,
173 };
174 #define param_check_xint param_check_int
175
176 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
177 module_param(power_save, xint, 0644);
178 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
179 "(in second, 0 = disable).");
180
181 static bool pm_blacklist = true;
182 module_param(pm_blacklist, bool, 0644);
183 MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist");
184
185 /* reset the HD-audio controller in power save mode.
186 * this may give more power-saving, but will take longer time to
187 * wake up.
188 */
189 static bool power_save_controller = 1;
190 module_param(power_save_controller, bool, 0644);
191 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
192 #else
193 #define power_save 0
194 #endif /* CONFIG_PM */
195
196 static int align_buffer_size = -1;
197 module_param(align_buffer_size, bint, 0644);
198 MODULE_PARM_DESC(align_buffer_size,
199 "Force buffer and period sizes to be multiple of 128 bytes.");
200
201 #ifdef CONFIG_X86
202 static int hda_snoop = -1;
203 module_param_named(snoop, hda_snoop, bint, 0444);
204 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
205 #else
206 #define hda_snoop true
207 #endif
208
209
210 MODULE_LICENSE("GPL");
211 MODULE_DESCRIPTION("Intel HDA driver");
212
213 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
214 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
215 #define SUPPORT_VGA_SWITCHEROO
216 #endif
217 #endif
218
219
220 /*
221 */
222
223 /* driver types */
224 enum {
225 AZX_DRIVER_ICH,
226 AZX_DRIVER_PCH,
227 AZX_DRIVER_SCH,
228 AZX_DRIVER_SKL,
229 AZX_DRIVER_HDMI,
230 AZX_DRIVER_ATI,
231 AZX_DRIVER_ATIHDMI,
232 AZX_DRIVER_ATIHDMI_NS,
233 AZX_DRIVER_GFHDMI,
234 AZX_DRIVER_VIA,
235 AZX_DRIVER_SIS,
236 AZX_DRIVER_ULI,
237 AZX_DRIVER_NVIDIA,
238 AZX_DRIVER_TERA,
239 AZX_DRIVER_CTX,
240 AZX_DRIVER_CTHDA,
241 AZX_DRIVER_CMEDIA,
242 AZX_DRIVER_ZHAOXIN,
243 AZX_DRIVER_GENERIC,
244 AZX_NUM_DRIVERS, /* keep this as last entry */
245 };
246
247 #define azx_get_snoop_type(chip) \
248 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
249 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
250
251 /* quirks for old Intel chipsets */
252 #define AZX_DCAPS_INTEL_ICH \
253 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
254
255 /* quirks for Intel PCH */
256 #define AZX_DCAPS_INTEL_PCH_BASE \
257 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
258 AZX_DCAPS_SNOOP_TYPE(SCH))
259
260 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
261 #define AZX_DCAPS_INTEL_PCH_NOPM \
262 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
263
264 /* PCH for HSW/BDW; with runtime PM */
265 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
266 #define AZX_DCAPS_INTEL_PCH \
267 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
268
269 /* HSW HDMI */
270 #define AZX_DCAPS_INTEL_HASWELL \
271 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
272 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
273 AZX_DCAPS_SNOOP_TYPE(SCH))
274
275 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
276 #define AZX_DCAPS_INTEL_BROADWELL \
277 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
278 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
279 AZX_DCAPS_SNOOP_TYPE(SCH))
280
281 #define AZX_DCAPS_INTEL_BAYTRAIL \
282 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
283
284 #define AZX_DCAPS_INTEL_BRASWELL \
285 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
286 AZX_DCAPS_I915_COMPONENT)
287
288 #define AZX_DCAPS_INTEL_SKYLAKE \
289 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
290 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
291
292 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE
293
294 /* quirks for ATI SB / AMD Hudson */
295 #define AZX_DCAPS_PRESET_ATI_SB \
296 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\
297 AZX_DCAPS_SNOOP_TYPE(ATI))
298
299 /* quirks for ATI/AMD HDMI */
300 #define AZX_DCAPS_PRESET_ATI_HDMI \
301 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\
302 AZX_DCAPS_NO_MSI64)
303
304 /* quirks for ATI HDMI with snoop off */
305 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
306 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
307
308 /* quirks for AMD SB */
309 #define AZX_DCAPS_PRESET_AMD_SB \
310 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\
311 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME |\
312 AZX_DCAPS_RETRY_PROBE)
313
314 /* quirks for Nvidia */
315 #define AZX_DCAPS_PRESET_NVIDIA \
316 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
317 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
318
319 #define AZX_DCAPS_PRESET_CTHDA \
320 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
321 AZX_DCAPS_NO_64BIT |\
322 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
323
324 /*
325 * vga_switcheroo support
326 */
327 #ifdef SUPPORT_VGA_SWITCHEROO
328 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
329 #define needs_eld_notify_link(chip) ((chip)->bus.keep_power)
330 #else
331 #define use_vga_switcheroo(chip) 0
332 #define needs_eld_notify_link(chip) false
333 #endif
334
335 #define CONTROLLER_IN_GPU(pci) (((pci)->vendor == 0x8086) && \
336 (((pci)->device == 0x0a0c) || \
337 ((pci)->device == 0x0c0c) || \
338 ((pci)->device == 0x0d0c) || \
339 ((pci)->device == 0x160c) || \
340 ((pci)->device == 0x490d) || \
341 ((pci)->device == 0x4f90) || \
342 ((pci)->device == 0x4f91) || \
343 ((pci)->device == 0x4f92)))
344
345 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
346
347 static const char * const driver_short_names[] = {
348 [AZX_DRIVER_ICH] = "HDA Intel",
349 [AZX_DRIVER_PCH] = "HDA Intel PCH",
350 [AZX_DRIVER_SCH] = "HDA Intel MID",
351 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
352 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
353 [AZX_DRIVER_ATI] = "HDA ATI SB",
354 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
355 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
356 [AZX_DRIVER_GFHDMI] = "HDA GF HDMI",
357 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
358 [AZX_DRIVER_SIS] = "HDA SIS966",
359 [AZX_DRIVER_ULI] = "HDA ULI M5461",
360 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
361 [AZX_DRIVER_TERA] = "HDA Teradici",
362 [AZX_DRIVER_CTX] = "HDA Creative",
363 [AZX_DRIVER_CTHDA] = "HDA Creative",
364 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
365 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
366 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
367 };
368
369 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
370 static void set_default_power_save(struct azx *chip);
371
372 /*
373 * initialize the PCI registers
374 */
375 /* update bits in a PCI register byte */
update_pci_byte(struct pci_dev * pci,unsigned int reg,unsigned char mask,unsigned char val)376 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
377 unsigned char mask, unsigned char val)
378 {
379 unsigned char data;
380
381 pci_read_config_byte(pci, reg, &data);
382 data &= ~mask;
383 data |= (val & mask);
384 pci_write_config_byte(pci, reg, data);
385 }
386
azx_init_pci(struct azx * chip)387 static void azx_init_pci(struct azx *chip)
388 {
389 int snoop_type = azx_get_snoop_type(chip);
390
391 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
392 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
393 * Ensuring these bits are 0 clears playback static on some HD Audio
394 * codecs.
395 * The PCI register TCSEL is defined in the Intel manuals.
396 */
397 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
398 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
399 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
400 }
401
402 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
403 * we need to enable snoop.
404 */
405 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
406 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
407 azx_snoop(chip));
408 update_pci_byte(chip->pci,
409 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
410 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
411 }
412
413 /* For NVIDIA HDA, enable snoop */
414 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
415 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
416 azx_snoop(chip));
417 update_pci_byte(chip->pci,
418 NVIDIA_HDA_TRANSREG_ADDR,
419 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
420 update_pci_byte(chip->pci,
421 NVIDIA_HDA_ISTRM_COH,
422 0x01, NVIDIA_HDA_ENABLE_COHBIT);
423 update_pci_byte(chip->pci,
424 NVIDIA_HDA_OSTRM_COH,
425 0x01, NVIDIA_HDA_ENABLE_COHBIT);
426 }
427
428 /* Enable SCH/PCH snoop if needed */
429 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
430 unsigned short snoop;
431 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
432 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
433 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
434 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
435 if (!azx_snoop(chip))
436 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
437 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
438 pci_read_config_word(chip->pci,
439 INTEL_SCH_HDA_DEVC, &snoop);
440 }
441 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
442 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
443 "Disabled" : "Enabled");
444 }
445 }
446
447 /*
448 * In BXT-P A0, HD-Audio DMA requests is later than expected,
449 * and makes an audio stream sensitive to system latencies when
450 * 24/32 bits are playing.
451 * Adjusting threshold of DMA fifo to force the DMA request
452 * sooner to improve latency tolerance at the expense of power.
453 */
bxt_reduce_dma_latency(struct azx * chip)454 static void bxt_reduce_dma_latency(struct azx *chip)
455 {
456 u32 val;
457
458 val = azx_readl(chip, VS_EM4L);
459 val &= (0x3 << 20);
460 azx_writel(chip, VS_EM4L, val);
461 }
462
463 /*
464 * ML_LCAP bits:
465 * bit 0: 6 MHz Supported
466 * bit 1: 12 MHz Supported
467 * bit 2: 24 MHz Supported
468 * bit 3: 48 MHz Supported
469 * bit 4: 96 MHz Supported
470 * bit 5: 192 MHz Supported
471 */
intel_get_lctl_scf(struct azx * chip)472 static int intel_get_lctl_scf(struct azx *chip)
473 {
474 struct hdac_bus *bus = azx_bus(chip);
475 static const int preferred_bits[] = { 2, 3, 1, 4, 5 };
476 u32 val, t;
477 int i;
478
479 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
480
481 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
482 t = preferred_bits[i];
483 if (val & (1 << t))
484 return t;
485 }
486
487 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
488 return 0;
489 }
490
intel_ml_lctl_set_power(struct azx * chip,int state)491 static int intel_ml_lctl_set_power(struct azx *chip, int state)
492 {
493 struct hdac_bus *bus = azx_bus(chip);
494 u32 val;
495 int timeout;
496
497 /*
498 * the codecs are sharing the first link setting by default
499 * If other links are enabled for stream, they need similar fix
500 */
501 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
502 val &= ~AZX_MLCTL_SPA;
503 val |= state << AZX_MLCTL_SPA_SHIFT;
504 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
505 /* wait for CPA */
506 timeout = 50;
507 while (timeout) {
508 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
509 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
510 return 0;
511 timeout--;
512 udelay(10);
513 }
514
515 return -1;
516 }
517
intel_init_lctl(struct azx * chip)518 static void intel_init_lctl(struct azx *chip)
519 {
520 struct hdac_bus *bus = azx_bus(chip);
521 u32 val;
522 int ret;
523
524 /* 0. check lctl register value is correct or not */
525 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
526 /* if SCF is already set, let's use it */
527 if ((val & ML_LCTL_SCF_MASK) != 0)
528 return;
529
530 /*
531 * Before operating on SPA, CPA must match SPA.
532 * Any deviation may result in undefined behavior.
533 */
534 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
535 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
536 return;
537
538 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
539 ret = intel_ml_lctl_set_power(chip, 0);
540 udelay(100);
541 if (ret)
542 goto set_spa;
543
544 /* 2. update SCF to select a properly audio clock*/
545 val &= ~ML_LCTL_SCF_MASK;
546 val |= intel_get_lctl_scf(chip);
547 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
548
549 set_spa:
550 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
551 intel_ml_lctl_set_power(chip, 1);
552 udelay(100);
553 }
554
hda_intel_init_chip(struct azx * chip,bool full_reset)555 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
556 {
557 struct hdac_bus *bus = azx_bus(chip);
558 struct pci_dev *pci = chip->pci;
559 u32 val;
560
561 snd_hdac_set_codec_wakeup(bus, true);
562 if (chip->driver_type == AZX_DRIVER_SKL) {
563 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
564 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
565 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
566 }
567 azx_init_chip(chip, full_reset);
568 if (chip->driver_type == AZX_DRIVER_SKL) {
569 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
570 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
571 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
572 }
573
574 snd_hdac_set_codec_wakeup(bus, false);
575
576 /* reduce dma latency to avoid noise */
577 if (IS_BXT(pci))
578 bxt_reduce_dma_latency(chip);
579
580 if (bus->mlcap != NULL)
581 intel_init_lctl(chip);
582 }
583
584 /* calculate runtime delay from LPIB */
azx_get_delay_from_lpib(struct azx * chip,struct azx_dev * azx_dev,unsigned int pos)585 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
586 unsigned int pos)
587 {
588 struct snd_pcm_substream *substream = azx_dev->core.substream;
589 int stream = substream->stream;
590 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
591 int delay;
592
593 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
594 delay = pos - lpib_pos;
595 else
596 delay = lpib_pos - pos;
597 if (delay < 0) {
598 if (delay >= azx_dev->core.delay_negative_threshold)
599 delay = 0;
600 else
601 delay += azx_dev->core.bufsize;
602 }
603
604 if (delay >= azx_dev->core.period_bytes) {
605 dev_info(chip->card->dev,
606 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
607 delay, azx_dev->core.period_bytes);
608 delay = 0;
609 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
610 chip->get_delay[stream] = NULL;
611 }
612
613 return bytes_to_frames(substream->runtime, delay);
614 }
615
616 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
617
618 /* called from IRQ */
azx_position_check(struct azx * chip,struct azx_dev * azx_dev)619 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
620 {
621 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
622 int ok;
623
624 ok = azx_position_ok(chip, azx_dev);
625 if (ok == 1) {
626 azx_dev->irq_pending = 0;
627 return ok;
628 } else if (ok == 0) {
629 /* bogus IRQ, process it later */
630 azx_dev->irq_pending = 1;
631 schedule_work(&hda->irq_pending_work);
632 }
633 return 0;
634 }
635
636 #define display_power(chip, enable) \
637 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
638
639 /*
640 * Check whether the current DMA position is acceptable for updating
641 * periods. Returns non-zero if it's OK.
642 *
643 * Many HD-audio controllers appear pretty inaccurate about
644 * the update-IRQ timing. The IRQ is issued before actually the
645 * data is processed. So, we need to process it afterwords in a
646 * workqueue.
647 *
648 * Returns 1 if OK to proceed, 0 for delay handling, -1 for skipping update
649 */
azx_position_ok(struct azx * chip,struct azx_dev * azx_dev)650 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
651 {
652 struct snd_pcm_substream *substream = azx_dev->core.substream;
653 struct snd_pcm_runtime *runtime = substream->runtime;
654 int stream = substream->stream;
655 u32 wallclk;
656 unsigned int pos;
657 snd_pcm_uframes_t hwptr, target;
658
659 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
660 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
661 return -1; /* bogus (too early) interrupt */
662
663 if (chip->get_position[stream])
664 pos = chip->get_position[stream](chip, azx_dev);
665 else { /* use the position buffer as default */
666 pos = azx_get_pos_posbuf(chip, azx_dev);
667 if (!pos || pos == (u32)-1) {
668 dev_info(chip->card->dev,
669 "Invalid position buffer, using LPIB read method instead.\n");
670 chip->get_position[stream] = azx_get_pos_lpib;
671 if (chip->get_position[0] == azx_get_pos_lpib &&
672 chip->get_position[1] == azx_get_pos_lpib)
673 azx_bus(chip)->use_posbuf = false;
674 pos = azx_get_pos_lpib(chip, azx_dev);
675 chip->get_delay[stream] = NULL;
676 } else {
677 chip->get_position[stream] = azx_get_pos_posbuf;
678 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
679 chip->get_delay[stream] = azx_get_delay_from_lpib;
680 }
681 }
682
683 if (pos >= azx_dev->core.bufsize)
684 pos = 0;
685
686 if (WARN_ONCE(!azx_dev->core.period_bytes,
687 "hda-intel: zero azx_dev->period_bytes"))
688 return -1; /* this shouldn't happen! */
689 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
690 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
691 /* NG - it's below the first next period boundary */
692 return chip->bdl_pos_adj ? 0 : -1;
693 azx_dev->core.start_wallclk += wallclk;
694
695 if (azx_dev->core.no_period_wakeup)
696 return 1; /* OK, no need to check period boundary */
697
698 if (runtime->hw_ptr_base != runtime->hw_ptr_interrupt)
699 return 1; /* OK, already in hwptr updating process */
700
701 /* check whether the period gets really elapsed */
702 pos = bytes_to_frames(runtime, pos);
703 hwptr = runtime->hw_ptr_base + pos;
704 if (hwptr < runtime->status->hw_ptr)
705 hwptr += runtime->buffer_size;
706 target = runtime->hw_ptr_interrupt + runtime->period_size;
707 if (hwptr < target) {
708 /* too early wakeup, process it later */
709 return chip->bdl_pos_adj ? 0 : -1;
710 }
711
712 return 1; /* OK, it's fine */
713 }
714
715 /*
716 * The work for pending PCM period updates.
717 */
azx_irq_pending_work(struct work_struct * work)718 static void azx_irq_pending_work(struct work_struct *work)
719 {
720 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
721 struct azx *chip = &hda->chip;
722 struct hdac_bus *bus = azx_bus(chip);
723 struct hdac_stream *s;
724 int pending, ok;
725
726 if (!hda->irq_pending_warned) {
727 dev_info(chip->card->dev,
728 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
729 chip->card->number);
730 hda->irq_pending_warned = 1;
731 }
732
733 for (;;) {
734 pending = 0;
735 spin_lock_irq(&bus->reg_lock);
736 list_for_each_entry(s, &bus->stream_list, list) {
737 struct azx_dev *azx_dev = stream_to_azx_dev(s);
738 if (!azx_dev->irq_pending ||
739 !s->substream ||
740 !s->running)
741 continue;
742 ok = azx_position_ok(chip, azx_dev);
743 if (ok > 0) {
744 azx_dev->irq_pending = 0;
745 spin_unlock(&bus->reg_lock);
746 snd_pcm_period_elapsed(s->substream);
747 spin_lock(&bus->reg_lock);
748 } else if (ok < 0) {
749 pending = 0; /* too early */
750 } else
751 pending++;
752 }
753 spin_unlock_irq(&bus->reg_lock);
754 if (!pending)
755 return;
756 msleep(1);
757 }
758 }
759
760 /* clear irq_pending flags and assure no on-going workq */
azx_clear_irq_pending(struct azx * chip)761 static void azx_clear_irq_pending(struct azx *chip)
762 {
763 struct hdac_bus *bus = azx_bus(chip);
764 struct hdac_stream *s;
765
766 spin_lock_irq(&bus->reg_lock);
767 list_for_each_entry(s, &bus->stream_list, list) {
768 struct azx_dev *azx_dev = stream_to_azx_dev(s);
769 azx_dev->irq_pending = 0;
770 }
771 spin_unlock_irq(&bus->reg_lock);
772 }
773
azx_acquire_irq(struct azx * chip,int do_disconnect)774 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
775 {
776 struct hdac_bus *bus = azx_bus(chip);
777
778 if (request_irq(chip->pci->irq, azx_interrupt,
779 chip->msi ? 0 : IRQF_SHARED,
780 chip->card->irq_descr, chip)) {
781 dev_err(chip->card->dev,
782 "unable to grab IRQ %d, disabling device\n",
783 chip->pci->irq);
784 if (do_disconnect)
785 snd_card_disconnect(chip->card);
786 return -1;
787 }
788 bus->irq = chip->pci->irq;
789 chip->card->sync_irq = bus->irq;
790 pci_intx(chip->pci, !chip->msi);
791 return 0;
792 }
793
794 /* get the current DMA position with correction on VIA chips */
azx_via_get_position(struct azx * chip,struct azx_dev * azx_dev)795 static unsigned int azx_via_get_position(struct azx *chip,
796 struct azx_dev *azx_dev)
797 {
798 unsigned int link_pos, mini_pos, bound_pos;
799 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
800 unsigned int fifo_size;
801
802 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
803 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
804 /* Playback, no problem using link position */
805 return link_pos;
806 }
807
808 /* Capture */
809 /* For new chipset,
810 * use mod to get the DMA position just like old chipset
811 */
812 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
813 mod_dma_pos %= azx_dev->core.period_bytes;
814
815 fifo_size = azx_stream(azx_dev)->fifo_size - 1;
816
817 if (azx_dev->insufficient) {
818 /* Link position never gather than FIFO size */
819 if (link_pos <= fifo_size)
820 return 0;
821
822 azx_dev->insufficient = 0;
823 }
824
825 if (link_pos <= fifo_size)
826 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
827 else
828 mini_pos = link_pos - fifo_size;
829
830 /* Find nearest previous boudary */
831 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
832 mod_link_pos = link_pos % azx_dev->core.period_bytes;
833 if (mod_link_pos >= fifo_size)
834 bound_pos = link_pos - mod_link_pos;
835 else if (mod_dma_pos >= mod_mini_pos)
836 bound_pos = mini_pos - mod_mini_pos;
837 else {
838 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
839 if (bound_pos >= azx_dev->core.bufsize)
840 bound_pos = 0;
841 }
842
843 /* Calculate real DMA position we want */
844 return bound_pos + mod_dma_pos;
845 }
846
847 #define AMD_FIFO_SIZE 32
848
849 /* get the current DMA position with FIFO size correction */
azx_get_pos_fifo(struct azx * chip,struct azx_dev * azx_dev)850 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
851 {
852 struct snd_pcm_substream *substream = azx_dev->core.substream;
853 struct snd_pcm_runtime *runtime = substream->runtime;
854 unsigned int pos, delay;
855
856 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
857 if (!runtime)
858 return pos;
859
860 runtime->delay = AMD_FIFO_SIZE;
861 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
862 if (azx_dev->insufficient) {
863 if (pos < delay) {
864 delay = pos;
865 runtime->delay = bytes_to_frames(runtime, pos);
866 } else {
867 azx_dev->insufficient = 0;
868 }
869 }
870
871 /* correct the DMA position for capture stream */
872 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
873 if (pos < delay)
874 pos += azx_dev->core.bufsize;
875 pos -= delay;
876 }
877
878 return pos;
879 }
880
azx_get_delay_from_fifo(struct azx * chip,struct azx_dev * azx_dev,unsigned int pos)881 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
882 unsigned int pos)
883 {
884 struct snd_pcm_substream *substream = azx_dev->core.substream;
885
886 /* just read back the calculated value in the above */
887 return substream->runtime->delay;
888 }
889
__azx_shutdown_chip(struct azx * chip,bool skip_link_reset)890 static void __azx_shutdown_chip(struct azx *chip, bool skip_link_reset)
891 {
892 azx_stop_chip(chip);
893 if (!skip_link_reset)
894 azx_enter_link_reset(chip);
895 azx_clear_irq_pending(chip);
896 display_power(chip, false);
897 }
898
899 #ifdef CONFIG_PM
900 static DEFINE_MUTEX(card_list_lock);
901 static LIST_HEAD(card_list);
902
azx_shutdown_chip(struct azx * chip)903 static void azx_shutdown_chip(struct azx *chip)
904 {
905 __azx_shutdown_chip(chip, false);
906 }
907
azx_add_card_list(struct azx * chip)908 static void azx_add_card_list(struct azx *chip)
909 {
910 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
911 mutex_lock(&card_list_lock);
912 list_add(&hda->list, &card_list);
913 mutex_unlock(&card_list_lock);
914 }
915
azx_del_card_list(struct azx * chip)916 static void azx_del_card_list(struct azx *chip)
917 {
918 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
919 mutex_lock(&card_list_lock);
920 list_del_init(&hda->list);
921 mutex_unlock(&card_list_lock);
922 }
923
924 /* trigger power-save check at writing parameter */
param_set_xint(const char * val,const struct kernel_param * kp)925 static int param_set_xint(const char *val, const struct kernel_param *kp)
926 {
927 struct hda_intel *hda;
928 struct azx *chip;
929 int prev = power_save;
930 int ret = param_set_int(val, kp);
931
932 if (ret || prev == power_save)
933 return ret;
934
935 mutex_lock(&card_list_lock);
936 list_for_each_entry(hda, &card_list, list) {
937 chip = &hda->chip;
938 if (!hda->probe_continued || chip->disabled)
939 continue;
940 snd_hda_set_power_save(&chip->bus, power_save * 1000);
941 }
942 mutex_unlock(&card_list_lock);
943 return 0;
944 }
945
946 /*
947 * power management
948 */
azx_is_pm_ready(struct snd_card * card)949 static bool azx_is_pm_ready(struct snd_card *card)
950 {
951 struct azx *chip;
952 struct hda_intel *hda;
953
954 if (!card)
955 return false;
956 chip = card->private_data;
957 hda = container_of(chip, struct hda_intel, chip);
958 if (chip->disabled || hda->init_failed || !chip->running)
959 return false;
960 return true;
961 }
962
__azx_runtime_resume(struct azx * chip)963 static void __azx_runtime_resume(struct azx *chip)
964 {
965 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
966 struct hdac_bus *bus = azx_bus(chip);
967 struct hda_codec *codec;
968 int status;
969
970 display_power(chip, true);
971 if (hda->need_i915_power)
972 snd_hdac_i915_set_bclk(bus);
973
974 /* Read STATESTS before controller reset */
975 status = azx_readw(chip, STATESTS);
976
977 azx_init_pci(chip);
978 hda_intel_init_chip(chip, true);
979
980 /* Avoid codec resume if runtime resume is for system suspend */
981 if (!chip->pm_prepared) {
982 list_for_each_codec(codec, &chip->bus) {
983 if (codec->relaxed_resume)
984 continue;
985
986 if (codec->forced_resume || (status & (1 << codec->addr)))
987 pm_request_resume(hda_codec_dev(codec));
988 }
989 }
990
991 /* power down again for link-controlled chips */
992 if (!hda->need_i915_power)
993 display_power(chip, false);
994 }
995
996 #ifdef CONFIG_PM_SLEEP
azx_prepare(struct device * dev)997 static int azx_prepare(struct device *dev)
998 {
999 struct snd_card *card = dev_get_drvdata(dev);
1000 struct azx *chip;
1001
1002 if (!azx_is_pm_ready(card))
1003 return 0;
1004
1005 chip = card->private_data;
1006 chip->pm_prepared = 1;
1007 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1008
1009 flush_work(&azx_bus(chip)->unsol_work);
1010
1011 /* HDA controller always requires different WAKEEN for runtime suspend
1012 * and system suspend, so don't use direct-complete here.
1013 */
1014 return 0;
1015 }
1016
azx_complete(struct device * dev)1017 static void azx_complete(struct device *dev)
1018 {
1019 struct snd_card *card = dev_get_drvdata(dev);
1020 struct azx *chip;
1021
1022 if (!azx_is_pm_ready(card))
1023 return;
1024
1025 chip = card->private_data;
1026 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1027 chip->pm_prepared = 0;
1028 }
1029
azx_suspend(struct device * dev)1030 static int azx_suspend(struct device *dev)
1031 {
1032 struct snd_card *card = dev_get_drvdata(dev);
1033 struct azx *chip;
1034 struct hdac_bus *bus;
1035
1036 if (!azx_is_pm_ready(card))
1037 return 0;
1038
1039 chip = card->private_data;
1040 bus = azx_bus(chip);
1041 azx_shutdown_chip(chip);
1042 if (bus->irq >= 0) {
1043 free_irq(bus->irq, chip);
1044 bus->irq = -1;
1045 chip->card->sync_irq = -1;
1046 }
1047
1048 if (chip->msi)
1049 pci_disable_msi(chip->pci);
1050
1051 trace_azx_suspend(chip);
1052 return 0;
1053 }
1054
azx_resume(struct device * dev)1055 static int azx_resume(struct device *dev)
1056 {
1057 struct snd_card *card = dev_get_drvdata(dev);
1058 struct azx *chip;
1059
1060 if (!azx_is_pm_ready(card))
1061 return 0;
1062
1063 chip = card->private_data;
1064 if (chip->msi)
1065 if (pci_enable_msi(chip->pci) < 0)
1066 chip->msi = 0;
1067 if (azx_acquire_irq(chip, 1) < 0)
1068 return -EIO;
1069
1070 __azx_runtime_resume(chip);
1071
1072 trace_azx_resume(chip);
1073 return 0;
1074 }
1075
1076 /* put codec down to D3 at hibernation for Intel SKL+;
1077 * otherwise BIOS may still access the codec and screw up the driver
1078 */
azx_freeze_noirq(struct device * dev)1079 static int azx_freeze_noirq(struct device *dev)
1080 {
1081 struct snd_card *card = dev_get_drvdata(dev);
1082 struct azx *chip = card->private_data;
1083 struct pci_dev *pci = to_pci_dev(dev);
1084
1085 if (!azx_is_pm_ready(card))
1086 return 0;
1087 if (chip->driver_type == AZX_DRIVER_SKL)
1088 pci_set_power_state(pci, PCI_D3hot);
1089
1090 return 0;
1091 }
1092
azx_thaw_noirq(struct device * dev)1093 static int azx_thaw_noirq(struct device *dev)
1094 {
1095 struct snd_card *card = dev_get_drvdata(dev);
1096 struct azx *chip = card->private_data;
1097 struct pci_dev *pci = to_pci_dev(dev);
1098
1099 if (!azx_is_pm_ready(card))
1100 return 0;
1101 if (chip->driver_type == AZX_DRIVER_SKL)
1102 pci_set_power_state(pci, PCI_D0);
1103
1104 return 0;
1105 }
1106 #endif /* CONFIG_PM_SLEEP */
1107
azx_runtime_suspend(struct device * dev)1108 static int azx_runtime_suspend(struct device *dev)
1109 {
1110 struct snd_card *card = dev_get_drvdata(dev);
1111 struct azx *chip;
1112
1113 if (!azx_is_pm_ready(card))
1114 return 0;
1115 chip = card->private_data;
1116
1117 /* enable controller wake up event */
1118 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK);
1119
1120 azx_shutdown_chip(chip);
1121 trace_azx_runtime_suspend(chip);
1122 return 0;
1123 }
1124
azx_runtime_resume(struct device * dev)1125 static int azx_runtime_resume(struct device *dev)
1126 {
1127 struct snd_card *card = dev_get_drvdata(dev);
1128 struct azx *chip;
1129
1130 if (!azx_is_pm_ready(card))
1131 return 0;
1132 chip = card->private_data;
1133 __azx_runtime_resume(chip);
1134
1135 /* disable controller Wake Up event*/
1136 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK);
1137
1138 trace_azx_runtime_resume(chip);
1139 return 0;
1140 }
1141
azx_runtime_idle(struct device * dev)1142 static int azx_runtime_idle(struct device *dev)
1143 {
1144 struct snd_card *card = dev_get_drvdata(dev);
1145 struct azx *chip;
1146 struct hda_intel *hda;
1147
1148 if (!card)
1149 return 0;
1150
1151 chip = card->private_data;
1152 hda = container_of(chip, struct hda_intel, chip);
1153 if (chip->disabled || hda->init_failed)
1154 return 0;
1155
1156 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1157 azx_bus(chip)->codec_powered || !chip->running)
1158 return -EBUSY;
1159
1160 /* ELD notification gets broken when HD-audio bus is off */
1161 if (needs_eld_notify_link(chip))
1162 return -EBUSY;
1163
1164 return 0;
1165 }
1166
1167 static const struct dev_pm_ops azx_pm = {
1168 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1169 #ifdef CONFIG_PM_SLEEP
1170 .prepare = azx_prepare,
1171 .complete = azx_complete,
1172 .freeze_noirq = azx_freeze_noirq,
1173 .thaw_noirq = azx_thaw_noirq,
1174 #endif
1175 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1176 };
1177
1178 #define AZX_PM_OPS &azx_pm
1179 #else
1180 #define azx_add_card_list(chip) /* NOP */
1181 #define azx_del_card_list(chip) /* NOP */
1182 #define AZX_PM_OPS NULL
1183 #endif /* CONFIG_PM */
1184
1185
1186 static int azx_probe_continue(struct azx *chip);
1187
1188 #ifdef SUPPORT_VGA_SWITCHEROO
1189 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1190
azx_vs_set_state(struct pci_dev * pci,enum vga_switcheroo_state state)1191 static void azx_vs_set_state(struct pci_dev *pci,
1192 enum vga_switcheroo_state state)
1193 {
1194 struct snd_card *card = pci_get_drvdata(pci);
1195 struct azx *chip = card->private_data;
1196 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1197 struct hda_codec *codec;
1198 bool disabled;
1199
1200 wait_for_completion(&hda->probe_wait);
1201 if (hda->init_failed)
1202 return;
1203
1204 disabled = (state == VGA_SWITCHEROO_OFF);
1205 if (chip->disabled == disabled)
1206 return;
1207
1208 if (!hda->probe_continued) {
1209 chip->disabled = disabled;
1210 if (!disabled) {
1211 dev_info(chip->card->dev,
1212 "Start delayed initialization\n");
1213 if (azx_probe_continue(chip) < 0)
1214 dev_err(chip->card->dev, "initialization error\n");
1215 }
1216 } else {
1217 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1218 disabled ? "Disabling" : "Enabling");
1219 if (disabled) {
1220 list_for_each_codec(codec, &chip->bus) {
1221 pm_runtime_suspend(hda_codec_dev(codec));
1222 pm_runtime_disable(hda_codec_dev(codec));
1223 }
1224 pm_runtime_suspend(card->dev);
1225 pm_runtime_disable(card->dev);
1226 /* when we get suspended by vga_switcheroo we end up in D3cold,
1227 * however we have no ACPI handle, so pci/acpi can't put us there,
1228 * put ourselves there */
1229 pci->current_state = PCI_D3cold;
1230 chip->disabled = true;
1231 if (snd_hda_lock_devices(&chip->bus))
1232 dev_warn(chip->card->dev,
1233 "Cannot lock devices!\n");
1234 } else {
1235 snd_hda_unlock_devices(&chip->bus);
1236 chip->disabled = false;
1237 pm_runtime_enable(card->dev);
1238 list_for_each_codec(codec, &chip->bus) {
1239 pm_runtime_enable(hda_codec_dev(codec));
1240 pm_runtime_resume(hda_codec_dev(codec));
1241 }
1242 }
1243 }
1244 }
1245
azx_vs_can_switch(struct pci_dev * pci)1246 static bool azx_vs_can_switch(struct pci_dev *pci)
1247 {
1248 struct snd_card *card = pci_get_drvdata(pci);
1249 struct azx *chip = card->private_data;
1250 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1251
1252 wait_for_completion(&hda->probe_wait);
1253 if (hda->init_failed)
1254 return false;
1255 if (chip->disabled || !hda->probe_continued)
1256 return true;
1257 if (snd_hda_lock_devices(&chip->bus))
1258 return false;
1259 snd_hda_unlock_devices(&chip->bus);
1260 return true;
1261 }
1262
1263 /*
1264 * The discrete GPU cannot power down unless the HDA controller runtime
1265 * suspends, so activate runtime PM on codecs even if power_save == 0.
1266 */
setup_vga_switcheroo_runtime_pm(struct azx * chip)1267 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1268 {
1269 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1270 struct hda_codec *codec;
1271
1272 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
1273 list_for_each_codec(codec, &chip->bus)
1274 codec->auto_runtime_pm = 1;
1275 /* reset the power save setup */
1276 if (chip->running)
1277 set_default_power_save(chip);
1278 }
1279 }
1280
azx_vs_gpu_bound(struct pci_dev * pci,enum vga_switcheroo_client_id client_id)1281 static void azx_vs_gpu_bound(struct pci_dev *pci,
1282 enum vga_switcheroo_client_id client_id)
1283 {
1284 struct snd_card *card = pci_get_drvdata(pci);
1285 struct azx *chip = card->private_data;
1286
1287 if (client_id == VGA_SWITCHEROO_DIS)
1288 chip->bus.keep_power = 0;
1289 setup_vga_switcheroo_runtime_pm(chip);
1290 }
1291
init_vga_switcheroo(struct azx * chip)1292 static void init_vga_switcheroo(struct azx *chip)
1293 {
1294 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1295 struct pci_dev *p = get_bound_vga(chip->pci);
1296 struct pci_dev *parent;
1297 if (p) {
1298 dev_info(chip->card->dev,
1299 "Handle vga_switcheroo audio client\n");
1300 hda->use_vga_switcheroo = 1;
1301
1302 /* cleared in either gpu_bound op or codec probe, or when its
1303 * upstream port has _PR3 (i.e. dGPU).
1304 */
1305 parent = pci_upstream_bridge(p);
1306 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
1307 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1308 pci_dev_put(p);
1309 }
1310 }
1311
1312 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1313 .set_gpu_state = azx_vs_set_state,
1314 .can_switch = azx_vs_can_switch,
1315 .gpu_bound = azx_vs_gpu_bound,
1316 };
1317
register_vga_switcheroo(struct azx * chip)1318 static int register_vga_switcheroo(struct azx *chip)
1319 {
1320 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1321 struct pci_dev *p;
1322 int err;
1323
1324 if (!hda->use_vga_switcheroo)
1325 return 0;
1326
1327 p = get_bound_vga(chip->pci);
1328 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1329 pci_dev_put(p);
1330
1331 if (err < 0)
1332 return err;
1333 hda->vga_switcheroo_registered = 1;
1334
1335 return 0;
1336 }
1337 #else
1338 #define init_vga_switcheroo(chip) /* NOP */
1339 #define register_vga_switcheroo(chip) 0
1340 #define check_hdmi_disabled(pci) false
1341 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */
1342 #endif /* SUPPORT_VGA_SWITCHER */
1343
1344 /*
1345 * destructor
1346 */
azx_free(struct azx * chip)1347 static void azx_free(struct azx *chip)
1348 {
1349 struct pci_dev *pci = chip->pci;
1350 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1351 struct hdac_bus *bus = azx_bus(chip);
1352
1353 if (hda->freed)
1354 return;
1355
1356 if (azx_has_pm_runtime(chip) && chip->running)
1357 pm_runtime_get_noresume(&pci->dev);
1358 chip->running = 0;
1359
1360 azx_del_card_list(chip);
1361
1362 hda->init_failed = 1; /* to be sure */
1363 complete_all(&hda->probe_wait);
1364
1365 if (use_vga_switcheroo(hda)) {
1366 if (chip->disabled && hda->probe_continued)
1367 snd_hda_unlock_devices(&chip->bus);
1368 if (hda->vga_switcheroo_registered)
1369 vga_switcheroo_unregister_client(chip->pci);
1370 }
1371
1372 if (bus->chip_init) {
1373 azx_clear_irq_pending(chip);
1374 azx_stop_all_streams(chip);
1375 azx_stop_chip(chip);
1376 }
1377
1378 if (bus->irq >= 0)
1379 free_irq(bus->irq, (void*)chip);
1380
1381 azx_free_stream_pages(chip);
1382 azx_free_streams(chip);
1383 snd_hdac_bus_exit(bus);
1384
1385 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1386 release_firmware(chip->fw);
1387 #endif
1388 display_power(chip, false);
1389
1390 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1391 snd_hdac_i915_exit(bus);
1392
1393 hda->freed = 1;
1394 }
1395
azx_dev_disconnect(struct snd_device * device)1396 static int azx_dev_disconnect(struct snd_device *device)
1397 {
1398 struct azx *chip = device->device_data;
1399 struct hdac_bus *bus = azx_bus(chip);
1400
1401 chip->bus.shutdown = 1;
1402 cancel_work_sync(&bus->unsol_work);
1403
1404 return 0;
1405 }
1406
azx_dev_free(struct snd_device * device)1407 static int azx_dev_free(struct snd_device *device)
1408 {
1409 azx_free(device->device_data);
1410 return 0;
1411 }
1412
1413 #ifdef SUPPORT_VGA_SWITCHEROO
1414 #ifdef CONFIG_ACPI
1415 /* ATPX is in the integrated GPU's namespace */
atpx_present(void)1416 static bool atpx_present(void)
1417 {
1418 struct pci_dev *pdev = NULL;
1419 acpi_handle dhandle, atpx_handle;
1420 acpi_status status;
1421
1422 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
1423 dhandle = ACPI_HANDLE(&pdev->dev);
1424 if (dhandle) {
1425 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1426 if (ACPI_SUCCESS(status)) {
1427 pci_dev_put(pdev);
1428 return true;
1429 }
1430 }
1431 }
1432 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
1433 dhandle = ACPI_HANDLE(&pdev->dev);
1434 if (dhandle) {
1435 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1436 if (ACPI_SUCCESS(status)) {
1437 pci_dev_put(pdev);
1438 return true;
1439 }
1440 }
1441 }
1442 return false;
1443 }
1444 #else
atpx_present(void)1445 static bool atpx_present(void)
1446 {
1447 return false;
1448 }
1449 #endif
1450
1451 /*
1452 * Check of disabled HDMI controller by vga_switcheroo
1453 */
get_bound_vga(struct pci_dev * pci)1454 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1455 {
1456 struct pci_dev *p;
1457
1458 /* check only discrete GPU */
1459 switch (pci->vendor) {
1460 case PCI_VENDOR_ID_ATI:
1461 case PCI_VENDOR_ID_AMD:
1462 if (pci->devfn == 1) {
1463 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1464 pci->bus->number, 0);
1465 if (p) {
1466 /* ATPX is in the integrated GPU's ACPI namespace
1467 * rather than the dGPU's namespace. However,
1468 * the dGPU is the one who is involved in
1469 * vgaswitcheroo.
1470 */
1471 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
1472 atpx_present())
1473 return p;
1474 pci_dev_put(p);
1475 }
1476 }
1477 break;
1478 case PCI_VENDOR_ID_NVIDIA:
1479 if (pci->devfn == 1) {
1480 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1481 pci->bus->number, 0);
1482 if (p) {
1483 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1484 return p;
1485 pci_dev_put(p);
1486 }
1487 }
1488 break;
1489 }
1490 return NULL;
1491 }
1492
check_hdmi_disabled(struct pci_dev * pci)1493 static bool check_hdmi_disabled(struct pci_dev *pci)
1494 {
1495 bool vga_inactive = false;
1496 struct pci_dev *p = get_bound_vga(pci);
1497
1498 if (p) {
1499 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1500 vga_inactive = true;
1501 pci_dev_put(p);
1502 }
1503 return vga_inactive;
1504 }
1505 #endif /* SUPPORT_VGA_SWITCHEROO */
1506
1507 /*
1508 * allow/deny-listing for position_fix
1509 */
1510 static const struct snd_pci_quirk position_fix_list[] = {
1511 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1512 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1513 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1514 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1515 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1516 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1517 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1518 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1519 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1520 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1521 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1522 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1523 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1524 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1525 {}
1526 };
1527
check_position_fix(struct azx * chip,int fix)1528 static int check_position_fix(struct azx *chip, int fix)
1529 {
1530 const struct snd_pci_quirk *q;
1531
1532 switch (fix) {
1533 case POS_FIX_AUTO:
1534 case POS_FIX_LPIB:
1535 case POS_FIX_POSBUF:
1536 case POS_FIX_VIACOMBO:
1537 case POS_FIX_COMBO:
1538 case POS_FIX_SKL:
1539 case POS_FIX_FIFO:
1540 return fix;
1541 }
1542
1543 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1544 if (q) {
1545 dev_info(chip->card->dev,
1546 "position_fix set to %d for device %04x:%04x\n",
1547 q->value, q->subvendor, q->subdevice);
1548 return q->value;
1549 }
1550
1551 /* Check VIA/ATI HD Audio Controller exist */
1552 if (chip->driver_type == AZX_DRIVER_VIA) {
1553 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1554 return POS_FIX_VIACOMBO;
1555 }
1556 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1557 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1558 return POS_FIX_FIFO;
1559 }
1560 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1561 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1562 return POS_FIX_LPIB;
1563 }
1564 if (chip->driver_type == AZX_DRIVER_SKL) {
1565 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1566 return POS_FIX_SKL;
1567 }
1568 return POS_FIX_AUTO;
1569 }
1570
assign_position_fix(struct azx * chip,int fix)1571 static void assign_position_fix(struct azx *chip, int fix)
1572 {
1573 static const azx_get_pos_callback_t callbacks[] = {
1574 [POS_FIX_AUTO] = NULL,
1575 [POS_FIX_LPIB] = azx_get_pos_lpib,
1576 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1577 [POS_FIX_VIACOMBO] = azx_via_get_position,
1578 [POS_FIX_COMBO] = azx_get_pos_lpib,
1579 [POS_FIX_SKL] = azx_get_pos_posbuf,
1580 [POS_FIX_FIFO] = azx_get_pos_fifo,
1581 };
1582
1583 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1584
1585 /* combo mode uses LPIB only for playback */
1586 if (fix == POS_FIX_COMBO)
1587 chip->get_position[1] = NULL;
1588
1589 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1590 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1591 chip->get_delay[0] = chip->get_delay[1] =
1592 azx_get_delay_from_lpib;
1593 }
1594
1595 if (fix == POS_FIX_FIFO)
1596 chip->get_delay[0] = chip->get_delay[1] =
1597 azx_get_delay_from_fifo;
1598 }
1599
1600 /*
1601 * deny-lists for probe_mask
1602 */
1603 static const struct snd_pci_quirk probe_mask_list[] = {
1604 /* Thinkpad often breaks the controller communication when accessing
1605 * to the non-working (or non-existing) modem codec slot.
1606 */
1607 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1608 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1609 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1610 /* broken BIOS */
1611 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1612 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1613 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1614 /* forced codec slots */
1615 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1616 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1617 SND_PCI_QUIRK(0x1558, 0x0351, "Schenker Dock 15", 0x105),
1618 /* WinFast VP200 H (Teradici) user reported broken communication */
1619 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1620 {}
1621 };
1622
1623 #define AZX_FORCE_CODEC_MASK 0x100
1624
check_probe_mask(struct azx * chip,int dev)1625 static void check_probe_mask(struct azx *chip, int dev)
1626 {
1627 const struct snd_pci_quirk *q;
1628
1629 chip->codec_probe_mask = probe_mask[dev];
1630 if (chip->codec_probe_mask == -1) {
1631 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1632 if (q) {
1633 dev_info(chip->card->dev,
1634 "probe_mask set to 0x%x for device %04x:%04x\n",
1635 q->value, q->subvendor, q->subdevice);
1636 chip->codec_probe_mask = q->value;
1637 }
1638 }
1639
1640 /* check forced option */
1641 if (chip->codec_probe_mask != -1 &&
1642 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1643 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1644 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1645 (int)azx_bus(chip)->codec_mask);
1646 }
1647 }
1648
1649 /*
1650 * allow/deny-list for enable_msi
1651 */
1652 static const struct snd_pci_quirk msi_deny_list[] = {
1653 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1654 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1655 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1656 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1657 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1658 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1659 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1660 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1661 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1662 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1663 {}
1664 };
1665
check_msi(struct azx * chip)1666 static void check_msi(struct azx *chip)
1667 {
1668 const struct snd_pci_quirk *q;
1669
1670 if (enable_msi >= 0) {
1671 chip->msi = !!enable_msi;
1672 return;
1673 }
1674 chip->msi = 1; /* enable MSI as default */
1675 q = snd_pci_quirk_lookup(chip->pci, msi_deny_list);
1676 if (q) {
1677 dev_info(chip->card->dev,
1678 "msi for device %04x:%04x set to %d\n",
1679 q->subvendor, q->subdevice, q->value);
1680 chip->msi = q->value;
1681 return;
1682 }
1683
1684 /* NVidia chipsets seem to cause troubles with MSI */
1685 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1686 dev_info(chip->card->dev, "Disabling MSI\n");
1687 chip->msi = 0;
1688 }
1689 }
1690
1691 /* check the snoop mode availability */
azx_check_snoop_available(struct azx * chip)1692 static void azx_check_snoop_available(struct azx *chip)
1693 {
1694 int snoop = hda_snoop;
1695
1696 if (snoop >= 0) {
1697 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1698 snoop ? "snoop" : "non-snoop");
1699 chip->snoop = snoop;
1700 chip->uc_buffer = !snoop;
1701 return;
1702 }
1703
1704 snoop = true;
1705 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1706 chip->driver_type == AZX_DRIVER_VIA) {
1707 /* force to non-snoop mode for a new VIA controller
1708 * when BIOS is set
1709 */
1710 u8 val;
1711 pci_read_config_byte(chip->pci, 0x42, &val);
1712 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1713 chip->pci->revision == 0x20))
1714 snoop = false;
1715 }
1716
1717 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1718 snoop = false;
1719
1720 chip->snoop = snoop;
1721 if (!snoop) {
1722 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1723 /* C-Media requires non-cached pages only for CORB/RIRB */
1724 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1725 chip->uc_buffer = true;
1726 }
1727 }
1728
azx_probe_work(struct work_struct * work)1729 static void azx_probe_work(struct work_struct *work)
1730 {
1731 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work.work);
1732 azx_probe_continue(&hda->chip);
1733 }
1734
default_bdl_pos_adj(struct azx * chip)1735 static int default_bdl_pos_adj(struct azx *chip)
1736 {
1737 /* some exceptions: Atoms seem problematic with value 1 */
1738 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1739 switch (chip->pci->device) {
1740 case 0x0f04: /* Baytrail */
1741 case 0x2284: /* Braswell */
1742 return 32;
1743 }
1744 }
1745
1746 switch (chip->driver_type) {
1747 /*
1748 * increase the bdl size for Glenfly Gpus for hardware
1749 * limitation on hdac interrupt interval
1750 */
1751 case AZX_DRIVER_GFHDMI:
1752 return 128;
1753 case AZX_DRIVER_ICH:
1754 case AZX_DRIVER_PCH:
1755 return 1;
1756 default:
1757 return 32;
1758 }
1759 }
1760
1761 /*
1762 * constructor
1763 */
1764 static const struct hda_controller_ops pci_hda_ops;
1765
azx_create(struct snd_card * card,struct pci_dev * pci,int dev,unsigned int driver_caps,struct azx ** rchip)1766 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1767 int dev, unsigned int driver_caps,
1768 struct azx **rchip)
1769 {
1770 static const struct snd_device_ops ops = {
1771 .dev_disconnect = azx_dev_disconnect,
1772 .dev_free = azx_dev_free,
1773 };
1774 struct hda_intel *hda;
1775 struct azx *chip;
1776 int err;
1777
1778 *rchip = NULL;
1779
1780 err = pcim_enable_device(pci);
1781 if (err < 0)
1782 return err;
1783
1784 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL);
1785 if (!hda)
1786 return -ENOMEM;
1787
1788 chip = &hda->chip;
1789 mutex_init(&chip->open_mutex);
1790 chip->card = card;
1791 chip->pci = pci;
1792 chip->ops = &pci_hda_ops;
1793 chip->driver_caps = driver_caps;
1794 chip->driver_type = driver_caps & 0xff;
1795 check_msi(chip);
1796 chip->dev_index = dev;
1797 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1798 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1799 INIT_LIST_HEAD(&chip->pcm_list);
1800 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1801 INIT_LIST_HEAD(&hda->list);
1802 init_vga_switcheroo(chip);
1803 init_completion(&hda->probe_wait);
1804
1805 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1806
1807 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1808 chip->fallback_to_single_cmd = 1;
1809 else /* explicitly set to single_cmd or not */
1810 chip->single_cmd = single_cmd;
1811
1812 azx_check_snoop_available(chip);
1813
1814 if (bdl_pos_adj[dev] < 0)
1815 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1816 else
1817 chip->bdl_pos_adj = bdl_pos_adj[dev];
1818
1819 err = azx_bus_init(chip, model[dev]);
1820 if (err < 0)
1821 return err;
1822
1823 /* use the non-cached pages in non-snoop mode */
1824 if (!azx_snoop(chip))
1825 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_WC;
1826
1827 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1828 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1829 chip->bus.core.needs_damn_long_delay = 1;
1830 }
1831
1832 check_probe_mask(chip, dev);
1833
1834 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1835 if (err < 0) {
1836 dev_err(card->dev, "Error creating device [card]!\n");
1837 azx_free(chip);
1838 return err;
1839 }
1840
1841 /* continue probing in work context as may trigger request module */
1842 INIT_DELAYED_WORK(&hda->probe_work, azx_probe_work);
1843
1844 *rchip = chip;
1845
1846 return 0;
1847 }
1848
azx_first_init(struct azx * chip)1849 static int azx_first_init(struct azx *chip)
1850 {
1851 int dev = chip->dev_index;
1852 struct pci_dev *pci = chip->pci;
1853 struct snd_card *card = chip->card;
1854 struct hdac_bus *bus = azx_bus(chip);
1855 int err;
1856 unsigned short gcap;
1857 unsigned int dma_bits = 64;
1858
1859 #if BITS_PER_LONG != 64
1860 /* Fix up base address on ULI M5461 */
1861 if (chip->driver_type == AZX_DRIVER_ULI) {
1862 u16 tmp3;
1863 pci_read_config_word(pci, 0x40, &tmp3);
1864 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1865 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1866 }
1867 #endif
1868 /*
1869 * Fix response write request not synced to memory when handle
1870 * hdac interrupt on Glenfly Gpus
1871 */
1872 if (chip->driver_type == AZX_DRIVER_GFHDMI)
1873 bus->polling_mode = 1;
1874
1875 err = pcim_iomap_regions(pci, 1 << 0, "ICH HD audio");
1876 if (err < 0)
1877 return err;
1878
1879 bus->addr = pci_resource_start(pci, 0);
1880 bus->remap_addr = pcim_iomap_table(pci)[0];
1881
1882 if (chip->driver_type == AZX_DRIVER_SKL)
1883 snd_hdac_bus_parse_capabilities(bus);
1884
1885 /*
1886 * Some Intel CPUs has always running timer (ART) feature and
1887 * controller may have Global time sync reporting capability, so
1888 * check both of these before declaring synchronized time reporting
1889 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1890 */
1891 chip->gts_present = false;
1892
1893 #ifdef CONFIG_X86
1894 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1895 chip->gts_present = true;
1896 #endif
1897
1898 if (chip->msi) {
1899 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1900 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1901 pci->no_64bit_msi = true;
1902 }
1903 if (pci_enable_msi(pci) < 0)
1904 chip->msi = 0;
1905 }
1906
1907 pci_set_master(pci);
1908
1909 gcap = azx_readw(chip, GCAP);
1910 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1911
1912 /* AMD devices support 40 or 48bit DMA, take the safe one */
1913 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1914 dma_bits = 40;
1915
1916 /* disable SB600 64bit support for safety */
1917 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1918 struct pci_dev *p_smbus;
1919 dma_bits = 40;
1920 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1921 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1922 NULL);
1923 if (p_smbus) {
1924 if (p_smbus->revision < 0x30)
1925 gcap &= ~AZX_GCAP_64OK;
1926 pci_dev_put(p_smbus);
1927 }
1928 }
1929
1930 /* NVidia hardware normally only supports up to 40 bits of DMA */
1931 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1932 dma_bits = 40;
1933
1934 /* disable 64bit DMA address on some devices */
1935 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1936 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1937 gcap &= ~AZX_GCAP_64OK;
1938 }
1939
1940 /* disable buffer size rounding to 128-byte multiples if supported */
1941 if (align_buffer_size >= 0)
1942 chip->align_buffer_size = !!align_buffer_size;
1943 else {
1944 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1945 chip->align_buffer_size = 0;
1946 else
1947 chip->align_buffer_size = 1;
1948 }
1949
1950 /* allow 64bit DMA address if supported by H/W */
1951 if (!(gcap & AZX_GCAP_64OK))
1952 dma_bits = 32;
1953 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits)))
1954 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32));
1955
1956 /* read number of streams from GCAP register instead of using
1957 * hardcoded value
1958 */
1959 chip->capture_streams = (gcap >> 8) & 0x0f;
1960 chip->playback_streams = (gcap >> 12) & 0x0f;
1961 if (!chip->playback_streams && !chip->capture_streams) {
1962 /* gcap didn't give any info, switching to old method */
1963
1964 switch (chip->driver_type) {
1965 case AZX_DRIVER_ULI:
1966 chip->playback_streams = ULI_NUM_PLAYBACK;
1967 chip->capture_streams = ULI_NUM_CAPTURE;
1968 break;
1969 case AZX_DRIVER_ATIHDMI:
1970 case AZX_DRIVER_ATIHDMI_NS:
1971 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1972 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1973 break;
1974 case AZX_DRIVER_GFHDMI:
1975 case AZX_DRIVER_GENERIC:
1976 default:
1977 chip->playback_streams = ICH6_NUM_PLAYBACK;
1978 chip->capture_streams = ICH6_NUM_CAPTURE;
1979 break;
1980 }
1981 }
1982 chip->capture_index_offset = 0;
1983 chip->playback_index_offset = chip->capture_streams;
1984 chip->num_streams = chip->playback_streams + chip->capture_streams;
1985
1986 /* sanity check for the SDxCTL.STRM field overflow */
1987 if (chip->num_streams > 15 &&
1988 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1989 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1990 "forcing separate stream tags", chip->num_streams);
1991 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1992 }
1993
1994 /* initialize streams */
1995 err = azx_init_streams(chip);
1996 if (err < 0)
1997 return err;
1998
1999 err = azx_alloc_stream_pages(chip);
2000 if (err < 0)
2001 return err;
2002
2003 /* initialize chip */
2004 azx_init_pci(chip);
2005
2006 snd_hdac_i915_set_bclk(bus);
2007
2008 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
2009
2010 /* codec detection */
2011 if (!azx_bus(chip)->codec_mask) {
2012 dev_err(card->dev, "no codecs found!\n");
2013 /* keep running the rest for the runtime PM */
2014 }
2015
2016 if (azx_acquire_irq(chip, 0) < 0)
2017 return -EBUSY;
2018
2019 strcpy(card->driver, "HDA-Intel");
2020 strscpy(card->shortname, driver_short_names[chip->driver_type],
2021 sizeof(card->shortname));
2022 snprintf(card->longname, sizeof(card->longname),
2023 "%s at 0x%lx irq %i",
2024 card->shortname, bus->addr, bus->irq);
2025
2026 return 0;
2027 }
2028
2029 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2030 /* callback from request_firmware_nowait() */
azx_firmware_cb(const struct firmware * fw,void * context)2031 static void azx_firmware_cb(const struct firmware *fw, void *context)
2032 {
2033 struct snd_card *card = context;
2034 struct azx *chip = card->private_data;
2035
2036 if (fw)
2037 chip->fw = fw;
2038 else
2039 dev_err(card->dev, "Cannot load firmware, continue without patching\n");
2040 if (!chip->disabled) {
2041 /* continue probing */
2042 azx_probe_continue(chip);
2043 }
2044 }
2045 #endif
2046
disable_msi_reset_irq(struct azx * chip)2047 static int disable_msi_reset_irq(struct azx *chip)
2048 {
2049 struct hdac_bus *bus = azx_bus(chip);
2050 int err;
2051
2052 free_irq(bus->irq, chip);
2053 bus->irq = -1;
2054 chip->card->sync_irq = -1;
2055 pci_disable_msi(chip->pci);
2056 chip->msi = 0;
2057 err = azx_acquire_irq(chip, 1);
2058 if (err < 0)
2059 return err;
2060
2061 return 0;
2062 }
2063
2064 /* Denylist for skipping the whole probe:
2065 * some HD-audio PCI entries are exposed without any codecs, and such devices
2066 * should be ignored from the beginning.
2067 */
2068 static const struct pci_device_id driver_denylist[] = {
2069 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */
2070 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */
2071 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */
2072 {}
2073 };
2074
2075 static const struct hda_controller_ops pci_hda_ops = {
2076 .disable_msi_reset_irq = disable_msi_reset_irq,
2077 .position_check = azx_position_check,
2078 };
2079
azx_probe(struct pci_dev * pci,const struct pci_device_id * pci_id)2080 static int azx_probe(struct pci_dev *pci,
2081 const struct pci_device_id *pci_id)
2082 {
2083 static int dev;
2084 struct snd_card *card;
2085 struct hda_intel *hda;
2086 struct azx *chip;
2087 bool schedule_probe;
2088 int err;
2089
2090 if (pci_match_id(driver_denylist, pci)) {
2091 dev_info(&pci->dev, "Skipping the device on the denylist\n");
2092 return -ENODEV;
2093 }
2094
2095 if (dev >= SNDRV_CARDS)
2096 return -ENODEV;
2097 if (!enable[dev]) {
2098 dev++;
2099 return -ENOENT;
2100 }
2101
2102 /*
2103 * stop probe if another Intel's DSP driver should be activated
2104 */
2105 if (dmic_detect) {
2106 err = snd_intel_dsp_driver_probe(pci);
2107 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) {
2108 dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n");
2109 return -ENODEV;
2110 }
2111 } else {
2112 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n");
2113 }
2114
2115 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2116 0, &card);
2117 if (err < 0) {
2118 dev_err(&pci->dev, "Error creating card!\n");
2119 return err;
2120 }
2121
2122 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2123 if (err < 0)
2124 goto out_free;
2125 card->private_data = chip;
2126 hda = container_of(chip, struct hda_intel, chip);
2127
2128 pci_set_drvdata(pci, card);
2129
2130 err = register_vga_switcheroo(chip);
2131 if (err < 0) {
2132 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2133 goto out_free;
2134 }
2135
2136 if (check_hdmi_disabled(pci)) {
2137 dev_info(card->dev, "VGA controller is disabled\n");
2138 dev_info(card->dev, "Delaying initialization\n");
2139 chip->disabled = true;
2140 }
2141
2142 schedule_probe = !chip->disabled;
2143
2144 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2145 if (patch[dev] && *patch[dev]) {
2146 dev_info(card->dev, "Applying patch firmware '%s'\n",
2147 patch[dev]);
2148 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2149 &pci->dev, GFP_KERNEL, card,
2150 azx_firmware_cb);
2151 if (err < 0)
2152 goto out_free;
2153 schedule_probe = false; /* continued in azx_firmware_cb() */
2154 }
2155 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2156
2157 #ifndef CONFIG_SND_HDA_I915
2158 if (CONTROLLER_IN_GPU(pci))
2159 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2160 #endif
2161
2162 if (schedule_probe)
2163 schedule_delayed_work(&hda->probe_work, 0);
2164
2165 dev++;
2166 if (chip->disabled)
2167 complete_all(&hda->probe_wait);
2168 return 0;
2169
2170 out_free:
2171 snd_card_free(card);
2172 return err;
2173 }
2174
2175 #ifdef CONFIG_PM
2176 /* On some boards setting power_save to a non 0 value leads to clicking /
2177 * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2178 * figure out how to avoid these sounds, but that is not always feasible.
2179 * So we keep a list of devices where we disable powersaving as its known
2180 * to causes problems on these devices.
2181 */
2182 static const struct snd_pci_quirk power_save_denylist[] = {
2183 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2184 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2185 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2186 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2187 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2188 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2189 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2190 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2191 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2192 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2193 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2194 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2195 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2196 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2197 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2198 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2199 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2200 /* https://bugs.launchpad.net/bugs/1821663 */
2201 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2202 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2203 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2204 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2205 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2206 SND_PCI_QUIRK(0x17aa, 0x316e, "Lenovo ThinkCentre M70q", 0),
2207 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2208 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2209 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2210 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2211 /* https://bugs.launchpad.net/bugs/1821663 */
2212 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2213 /* KONTRON SinglePC may cause a stall at runtime resume */
2214 SND_PCI_QUIRK(0x1734, 0x1232, "KONTRON SinglePC", 0),
2215 {}
2216 };
2217 #endif /* CONFIG_PM */
2218
set_default_power_save(struct azx * chip)2219 static void set_default_power_save(struct azx *chip)
2220 {
2221 int val = power_save;
2222
2223 #ifdef CONFIG_PM
2224 if (pm_blacklist) {
2225 const struct snd_pci_quirk *q;
2226
2227 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist);
2228 if (q && val) {
2229 dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n",
2230 q->subvendor, q->subdevice);
2231 val = 0;
2232 }
2233 }
2234 #endif /* CONFIG_PM */
2235 snd_hda_set_power_save(&chip->bus, val * 1000);
2236 }
2237
2238 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2239 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2240 [AZX_DRIVER_NVIDIA] = 8,
2241 [AZX_DRIVER_TERA] = 1,
2242 };
2243
azx_probe_continue(struct azx * chip)2244 static int azx_probe_continue(struct azx *chip)
2245 {
2246 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2247 struct hdac_bus *bus = azx_bus(chip);
2248 struct pci_dev *pci = chip->pci;
2249 int dev = chip->dev_index;
2250 int err;
2251
2252 if (chip->disabled || hda->init_failed)
2253 return -EIO;
2254 if (hda->probe_retry)
2255 goto probe_retry;
2256
2257 to_hda_bus(bus)->bus_probing = 1;
2258 hda->probe_continued = 1;
2259
2260 /* bind with i915 if needed */
2261 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2262 err = snd_hdac_i915_init(bus);
2263 if (err < 0) {
2264 /* if the controller is bound only with HDMI/DP
2265 * (for HSW and BDW), we need to abort the probe;
2266 * for other chips, still continue probing as other
2267 * codecs can be on the same link.
2268 */
2269 if (CONTROLLER_IN_GPU(pci)) {
2270 dev_err(chip->card->dev,
2271 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2272 goto out_free;
2273 } else {
2274 /* don't bother any longer */
2275 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2276 }
2277 }
2278
2279 /* HSW/BDW controllers need this power */
2280 if (CONTROLLER_IN_GPU(pci))
2281 hda->need_i915_power = true;
2282 }
2283
2284 /* Request display power well for the HDA controller or codec. For
2285 * Haswell/Broadwell, both the display HDA controller and codec need
2286 * this power. For other platforms, like Baytrail/Braswell, only the
2287 * display codec needs the power and it can be released after probe.
2288 */
2289 display_power(chip, true);
2290
2291 err = azx_first_init(chip);
2292 if (err < 0)
2293 goto out_free;
2294
2295 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2296 chip->beep_mode = beep_mode[dev];
2297 #endif
2298
2299 /* create codec instances */
2300 if (bus->codec_mask) {
2301 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2302 if (err < 0)
2303 goto out_free;
2304 }
2305
2306 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2307 if (chip->fw) {
2308 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2309 chip->fw->data);
2310 if (err < 0)
2311 goto out_free;
2312 #ifndef CONFIG_PM
2313 release_firmware(chip->fw); /* no longer needed */
2314 chip->fw = NULL;
2315 #endif
2316 }
2317 #endif
2318
2319 probe_retry:
2320 if (bus->codec_mask && !(probe_only[dev] & 1)) {
2321 err = azx_codec_configure(chip);
2322 if (err) {
2323 if ((chip->driver_caps & AZX_DCAPS_RETRY_PROBE) &&
2324 ++hda->probe_retry < 60) {
2325 schedule_delayed_work(&hda->probe_work,
2326 msecs_to_jiffies(1000));
2327 return 0; /* keep things up */
2328 }
2329 dev_err(chip->card->dev, "Cannot probe codecs, giving up\n");
2330 goto out_free;
2331 }
2332 }
2333
2334 err = snd_card_register(chip->card);
2335 if (err < 0)
2336 goto out_free;
2337
2338 setup_vga_switcheroo_runtime_pm(chip);
2339
2340 chip->running = 1;
2341 azx_add_card_list(chip);
2342
2343 set_default_power_save(chip);
2344
2345 if (azx_has_pm_runtime(chip)) {
2346 pm_runtime_use_autosuspend(&pci->dev);
2347 pm_runtime_allow(&pci->dev);
2348 pm_runtime_put_autosuspend(&pci->dev);
2349 }
2350
2351 out_free:
2352 if (err < 0) {
2353 pci_set_drvdata(pci, NULL);
2354 snd_card_free(chip->card);
2355 return err;
2356 }
2357
2358 if (!hda->need_i915_power)
2359 display_power(chip, false);
2360 complete_all(&hda->probe_wait);
2361 to_hda_bus(bus)->bus_probing = 0;
2362 hda->probe_retry = 0;
2363 return 0;
2364 }
2365
azx_remove(struct pci_dev * pci)2366 static void azx_remove(struct pci_dev *pci)
2367 {
2368 struct snd_card *card = pci_get_drvdata(pci);
2369 struct azx *chip;
2370 struct hda_intel *hda;
2371
2372 if (card) {
2373 /* cancel the pending probing work */
2374 chip = card->private_data;
2375 hda = container_of(chip, struct hda_intel, chip);
2376 /* FIXME: below is an ugly workaround.
2377 * Both device_release_driver() and driver_probe_device()
2378 * take *both* the device's and its parent's lock before
2379 * calling the remove() and probe() callbacks. The codec
2380 * probe takes the locks of both the codec itself and its
2381 * parent, i.e. the PCI controller dev. Meanwhile, when
2382 * the PCI controller is unbound, it takes its lock, too
2383 * ==> ouch, a deadlock!
2384 * As a workaround, we unlock temporarily here the controller
2385 * device during cancel_work_sync() call.
2386 */
2387 device_unlock(&pci->dev);
2388 cancel_delayed_work_sync(&hda->probe_work);
2389 device_lock(&pci->dev);
2390
2391 snd_card_free(card);
2392 }
2393 }
2394
azx_shutdown(struct pci_dev * pci)2395 static void azx_shutdown(struct pci_dev *pci)
2396 {
2397 struct snd_card *card = pci_get_drvdata(pci);
2398 struct azx *chip;
2399
2400 if (!card)
2401 return;
2402 chip = card->private_data;
2403 if (chip && chip->running)
2404 __azx_shutdown_chip(chip, true);
2405 }
2406
2407 /* PCI IDs */
2408 static const struct pci_device_id azx_ids[] = {
2409 /* CPT */
2410 { PCI_DEVICE(0x8086, 0x1c20),
2411 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2412 /* PBG */
2413 { PCI_DEVICE(0x8086, 0x1d20),
2414 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2415 /* Panther Point */
2416 { PCI_DEVICE(0x8086, 0x1e20),
2417 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2418 /* Lynx Point */
2419 { PCI_DEVICE(0x8086, 0x8c20),
2420 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2421 /* 9 Series */
2422 { PCI_DEVICE(0x8086, 0x8ca0),
2423 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2424 /* Wellsburg */
2425 { PCI_DEVICE(0x8086, 0x8d20),
2426 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2427 { PCI_DEVICE(0x8086, 0x8d21),
2428 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2429 /* Lewisburg */
2430 { PCI_DEVICE(0x8086, 0xa1f0),
2431 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2432 { PCI_DEVICE(0x8086, 0xa270),
2433 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2434 /* Lynx Point-LP */
2435 { PCI_DEVICE(0x8086, 0x9c20),
2436 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2437 /* Lynx Point-LP */
2438 { PCI_DEVICE(0x8086, 0x9c21),
2439 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2440 /* Wildcat Point-LP */
2441 { PCI_DEVICE(0x8086, 0x9ca0),
2442 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2443 /* Sunrise Point */
2444 { PCI_DEVICE(0x8086, 0xa170),
2445 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2446 /* Sunrise Point-LP */
2447 { PCI_DEVICE(0x8086, 0x9d70),
2448 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2449 /* Kabylake */
2450 { PCI_DEVICE(0x8086, 0xa171),
2451 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2452 /* Kabylake-LP */
2453 { PCI_DEVICE(0x8086, 0x9d71),
2454 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2455 /* Kabylake-H */
2456 { PCI_DEVICE(0x8086, 0xa2f0),
2457 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2458 /* Coffelake */
2459 { PCI_DEVICE(0x8086, 0xa348),
2460 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2461 /* Cannonlake */
2462 { PCI_DEVICE(0x8086, 0x9dc8),
2463 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2464 /* CometLake-LP */
2465 { PCI_DEVICE(0x8086, 0x02C8),
2466 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2467 /* CometLake-H */
2468 { PCI_DEVICE(0x8086, 0x06C8),
2469 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2470 { PCI_DEVICE(0x8086, 0xf1c8),
2471 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2472 /* CometLake-S */
2473 { PCI_DEVICE(0x8086, 0xa3f0),
2474 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2475 /* CometLake-R */
2476 { PCI_DEVICE(0x8086, 0xf0c8),
2477 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2478 /* Icelake */
2479 { PCI_DEVICE(0x8086, 0x34c8),
2480 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2481 /* Icelake-H */
2482 { PCI_DEVICE(0x8086, 0x3dc8),
2483 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2484 /* Jasperlake */
2485 { PCI_DEVICE(0x8086, 0x38c8),
2486 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2487 { PCI_DEVICE(0x8086, 0x4dc8),
2488 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2489 /* Tigerlake */
2490 { PCI_DEVICE(0x8086, 0xa0c8),
2491 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2492 /* Tigerlake-H */
2493 { PCI_DEVICE(0x8086, 0x43c8),
2494 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2495 /* DG1 */
2496 { PCI_DEVICE(0x8086, 0x490d),
2497 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2498 /* DG2 */
2499 { PCI_DEVICE(0x8086, 0x4f90),
2500 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2501 { PCI_DEVICE(0x8086, 0x4f91),
2502 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2503 { PCI_DEVICE(0x8086, 0x4f92),
2504 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2505 /* Alderlake-S */
2506 { PCI_DEVICE(0x8086, 0x7ad0),
2507 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2508 /* Alderlake-P */
2509 { PCI_DEVICE(0x8086, 0x51c8),
2510 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2511 /* Alderlake-M */
2512 { PCI_DEVICE(0x8086, 0x51cc),
2513 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2514 /* Elkhart Lake */
2515 { PCI_DEVICE(0x8086, 0x4b55),
2516 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2517 { PCI_DEVICE(0x8086, 0x4b58),
2518 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2519 /* Arrow Lake */
2520 { PCI_DEVICE_DATA(INTEL, HDA_ARL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2521 /* Broxton-P(Apollolake) */
2522 { PCI_DEVICE(0x8086, 0x5a98),
2523 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2524 /* Broxton-T */
2525 { PCI_DEVICE(0x8086, 0x1a98),
2526 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2527 /* Gemini-Lake */
2528 { PCI_DEVICE(0x8086, 0x3198),
2529 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2530 /* Haswell */
2531 { PCI_DEVICE(0x8086, 0x0a0c),
2532 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2533 { PCI_DEVICE(0x8086, 0x0c0c),
2534 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2535 { PCI_DEVICE(0x8086, 0x0d0c),
2536 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2537 /* Broadwell */
2538 { PCI_DEVICE(0x8086, 0x160c),
2539 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2540 /* 5 Series/3400 */
2541 { PCI_DEVICE(0x8086, 0x3b56),
2542 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2543 { PCI_DEVICE(0x8086, 0x3b57),
2544 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2545 /* Poulsbo */
2546 { PCI_DEVICE(0x8086, 0x811b),
2547 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE |
2548 AZX_DCAPS_POSFIX_LPIB },
2549 /* Oaktrail */
2550 { PCI_DEVICE(0x8086, 0x080a),
2551 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2552 /* BayTrail */
2553 { PCI_DEVICE(0x8086, 0x0f04),
2554 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2555 /* Braswell */
2556 { PCI_DEVICE(0x8086, 0x2284),
2557 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2558 /* ICH6 */
2559 { PCI_DEVICE(0x8086, 0x2668),
2560 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2561 /* ICH7 */
2562 { PCI_DEVICE(0x8086, 0x27d8),
2563 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2564 /* ESB2 */
2565 { PCI_DEVICE(0x8086, 0x269a),
2566 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2567 /* ICH8 */
2568 { PCI_DEVICE(0x8086, 0x284b),
2569 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2570 /* ICH9 */
2571 { PCI_DEVICE(0x8086, 0x293e),
2572 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2573 /* ICH9 */
2574 { PCI_DEVICE(0x8086, 0x293f),
2575 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2576 /* ICH10 */
2577 { PCI_DEVICE(0x8086, 0x3a3e),
2578 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2579 /* ICH10 */
2580 { PCI_DEVICE(0x8086, 0x3a6e),
2581 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2582 /* Generic Intel */
2583 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2584 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2585 .class_mask = 0xffffff,
2586 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2587 /* ATI SB 450/600/700/800/900 */
2588 { PCI_DEVICE(0x1002, 0x437b),
2589 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2590 { PCI_DEVICE(0x1002, 0x4383),
2591 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2592 /* AMD Hudson */
2593 { PCI_DEVICE(0x1022, 0x780d),
2594 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2595 /* AMD, X370 & co */
2596 { PCI_DEVICE(0x1022, 0x1457),
2597 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2598 /* AMD, X570 & co */
2599 { PCI_DEVICE(0x1022, 0x1487),
2600 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2601 /* AMD Stoney */
2602 { PCI_DEVICE(0x1022, 0x157a),
2603 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2604 AZX_DCAPS_PM_RUNTIME },
2605 /* AMD Raven */
2606 { PCI_DEVICE(0x1022, 0x15e3),
2607 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2608 /* ATI HDMI */
2609 { PCI_DEVICE(0x1002, 0x0002),
2610 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2611 AZX_DCAPS_PM_RUNTIME },
2612 { PCI_DEVICE(0x1002, 0x1308),
2613 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2614 { PCI_DEVICE(0x1002, 0x157a),
2615 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2616 { PCI_DEVICE(0x1002, 0x15b3),
2617 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2618 { PCI_DEVICE(0x1002, 0x793b),
2619 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2620 { PCI_DEVICE(0x1002, 0x7919),
2621 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2622 { PCI_DEVICE(0x1002, 0x960f),
2623 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2624 { PCI_DEVICE(0x1002, 0x970f),
2625 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2626 { PCI_DEVICE(0x1002, 0x9840),
2627 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2628 { PCI_DEVICE(0x1002, 0xaa00),
2629 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2630 { PCI_DEVICE(0x1002, 0xaa08),
2631 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2632 { PCI_DEVICE(0x1002, 0xaa10),
2633 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2634 { PCI_DEVICE(0x1002, 0xaa18),
2635 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2636 { PCI_DEVICE(0x1002, 0xaa20),
2637 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2638 { PCI_DEVICE(0x1002, 0xaa28),
2639 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2640 { PCI_DEVICE(0x1002, 0xaa30),
2641 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2642 { PCI_DEVICE(0x1002, 0xaa38),
2643 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2644 { PCI_DEVICE(0x1002, 0xaa40),
2645 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2646 { PCI_DEVICE(0x1002, 0xaa48),
2647 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2648 { PCI_DEVICE(0x1002, 0xaa50),
2649 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2650 { PCI_DEVICE(0x1002, 0xaa58),
2651 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2652 { PCI_DEVICE(0x1002, 0xaa60),
2653 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2654 { PCI_DEVICE(0x1002, 0xaa68),
2655 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2656 { PCI_DEVICE(0x1002, 0xaa80),
2657 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2658 { PCI_DEVICE(0x1002, 0xaa88),
2659 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2660 { PCI_DEVICE(0x1002, 0xaa90),
2661 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2662 { PCI_DEVICE(0x1002, 0xaa98),
2663 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2664 { PCI_DEVICE(0x1002, 0x9902),
2665 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2666 { PCI_DEVICE(0x1002, 0xaaa0),
2667 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2668 { PCI_DEVICE(0x1002, 0xaaa8),
2669 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2670 { PCI_DEVICE(0x1002, 0xaab0),
2671 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2672 { PCI_DEVICE(0x1002, 0xaac0),
2673 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2674 AZX_DCAPS_PM_RUNTIME },
2675 { PCI_DEVICE(0x1002, 0xaac8),
2676 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2677 AZX_DCAPS_PM_RUNTIME },
2678 { PCI_DEVICE(0x1002, 0xaad8),
2679 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2680 AZX_DCAPS_PM_RUNTIME },
2681 { PCI_DEVICE(0x1002, 0xaae0),
2682 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2683 AZX_DCAPS_PM_RUNTIME },
2684 { PCI_DEVICE(0x1002, 0xaae8),
2685 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2686 AZX_DCAPS_PM_RUNTIME },
2687 { PCI_DEVICE(0x1002, 0xaaf0),
2688 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2689 AZX_DCAPS_PM_RUNTIME },
2690 { PCI_DEVICE(0x1002, 0xaaf8),
2691 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2692 AZX_DCAPS_PM_RUNTIME },
2693 { PCI_DEVICE(0x1002, 0xab00),
2694 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2695 AZX_DCAPS_PM_RUNTIME },
2696 { PCI_DEVICE(0x1002, 0xab08),
2697 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2698 AZX_DCAPS_PM_RUNTIME },
2699 { PCI_DEVICE(0x1002, 0xab10),
2700 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2701 AZX_DCAPS_PM_RUNTIME },
2702 { PCI_DEVICE(0x1002, 0xab18),
2703 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2704 AZX_DCAPS_PM_RUNTIME },
2705 { PCI_DEVICE(0x1002, 0xab20),
2706 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2707 AZX_DCAPS_PM_RUNTIME },
2708 { PCI_DEVICE(0x1002, 0xab28),
2709 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2710 AZX_DCAPS_PM_RUNTIME },
2711 { PCI_DEVICE(0x1002, 0xab30),
2712 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2713 AZX_DCAPS_PM_RUNTIME },
2714 { PCI_DEVICE(0x1002, 0xab38),
2715 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2716 AZX_DCAPS_PM_RUNTIME },
2717 /* GLENFLY */
2718 { PCI_DEVICE(0x6766, PCI_ANY_ID),
2719 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2720 .class_mask = 0xffffff,
2721 .driver_data = AZX_DRIVER_GFHDMI | AZX_DCAPS_POSFIX_LPIB |
2722 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT },
2723 /* VIA VT8251/VT8237A */
2724 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2725 /* VIA GFX VT7122/VX900 */
2726 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2727 /* VIA GFX VT6122/VX11 */
2728 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2729 /* SIS966 */
2730 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2731 /* ULI M5461 */
2732 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2733 /* NVIDIA MCP */
2734 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2735 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2736 .class_mask = 0xffffff,
2737 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2738 /* Teradici */
2739 { PCI_DEVICE(0x6549, 0x1200),
2740 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2741 { PCI_DEVICE(0x6549, 0x2200),
2742 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2743 /* Creative X-Fi (CA0110-IBG) */
2744 /* CTHDA chips */
2745 { PCI_DEVICE(0x1102, 0x0010),
2746 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2747 { PCI_DEVICE(0x1102, 0x0012),
2748 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2749 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2750 /* the following entry conflicts with snd-ctxfi driver,
2751 * as ctxfi driver mutates from HD-audio to native mode with
2752 * a special command sequence.
2753 */
2754 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2755 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2756 .class_mask = 0xffffff,
2757 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2758 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2759 #else
2760 /* this entry seems still valid -- i.e. without emu20kx chip */
2761 { PCI_DEVICE(0x1102, 0x0009),
2762 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2763 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2764 #endif
2765 /* CM8888 */
2766 { PCI_DEVICE(0x13f6, 0x5011),
2767 .driver_data = AZX_DRIVER_CMEDIA |
2768 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2769 /* Vortex86MX */
2770 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2771 /* VMware HDAudio */
2772 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2773 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2774 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2775 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2776 .class_mask = 0xffffff,
2777 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2778 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2779 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2780 .class_mask = 0xffffff,
2781 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2782 /* Zhaoxin */
2783 { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
2784 { 0, }
2785 };
2786 MODULE_DEVICE_TABLE(pci, azx_ids);
2787
2788 /* pci_driver definition */
2789 static struct pci_driver azx_driver = {
2790 .name = KBUILD_MODNAME,
2791 .id_table = azx_ids,
2792 .probe = azx_probe,
2793 .remove = azx_remove,
2794 .shutdown = azx_shutdown,
2795 .driver = {
2796 .pm = AZX_PM_OPS,
2797 },
2798 };
2799
2800 module_pci_driver(azx_driver);
2801