253 #define MODE    0x22  macro
2919 	write_reg(info, CHB + MODE, val);  in enable_auxclk()
3004 	val = read_reg(info, CHA + MODE) | BIT0;  in loopback_enable()
3005 	write_reg(info, CHA + MODE, val);  in loopback_enable()
3062 	write_reg(info, CHA + MODE, val);  in hdlc_mode()
3255 	clear_reg_bits(info, CHA + MODE, BIT3);  in rx_stop()
3272 	set_reg_bits(info, CHA + MODE, BIT3);  in rx_start()
3334 	write_reg(info, CHA + MODE, 0);  in reset_device()
3335 	write_reg(info, CHB + MODE, 0);  in reset_device()
3408 	write_reg(info, CHA + MODE, val);  in async_mode()
3532 	set_reg_bits(info, CHA + MODE, BIT3);  in async_mode()
3587 	val = read_reg(info, CHA + MODE);  in set_signals()
3599 	write_reg(info, CHA + MODE, val);  in set_signals()