38 	struct axxia_clk aclk;  member
41 #define to_axxia_pllclk(_aclk) container_of(_aclk, struct axxia_pllclk, aclk)
50 	struct axxia_clk *aclk = to_axxia_clk(hw);  in axxia_pllclk_recalc()  local
51 	struct axxia_pllclk *pll = to_axxia_pllclk(aclk);  in axxia_pllclk_recalc()
55 	regmap_read(aclk->regmap, pll->reg, &control);  in axxia_pllclk_recalc()
76 	struct axxia_clk aclk;  member
81 #define to_axxia_divclk(_aclk) container_of(_aclk, struct axxia_divclk, aclk)
89 	struct axxia_clk *aclk = to_axxia_clk(hw);  in axxia_divclk_recalc_rate()  local
90 	struct axxia_divclk *divclk = to_axxia_divclk(aclk);  in axxia_divclk_recalc_rate()
93 	regmap_read(aclk->regmap, divclk->reg, &ctrl);  in axxia_divclk_recalc_rate()
111 	struct axxia_clk aclk;  member
116 #define to_axxia_clkmux(_aclk) container_of(_aclk, struct axxia_clkmux, aclk)
123 	struct axxia_clk *aclk = to_axxia_clk(hw);  in axxia_clkmux_get_parent()  local
124 	struct axxia_clkmux *mux = to_axxia_clkmux(aclk);  in axxia_clkmux_get_parent()
127 	regmap_read(aclk->regmap, mux->reg, &ctrl);  in axxia_clkmux_get_parent()
143 	.aclk.hw.init = &(struct clk_init_data){
155 	.aclk.hw.init = &(struct clk_init_data){
167 	.aclk.hw.init = &(struct clk_init_data){
179 	.aclk.hw.init = &(struct clk_init_data){
191 	.aclk.hw.init = &(struct clk_init_data){
207 	.aclk.hw.init = &(struct clk_init_data){
221 	.aclk.hw.init = &(struct clk_init_data){
235 	.aclk.hw.init = &(struct clk_init_data){
249 	.aclk.hw.init = &(struct clk_init_data){
263 	.aclk.hw.init = &(struct clk_init_data){
277 	.aclk.hw.init = &(struct clk_init_data){
291 	.aclk.hw.init = &(struct clk_init_data){
305 	.aclk.hw.init = &(struct clk_init_data){
319 	.aclk.hw.init = &(struct clk_init_data){
337 	.aclk.hw.init = &(struct clk_init_data){
354 	.aclk.hw.init = &(struct clk_init_data){
371 	.aclk.hw.init = &(struct clk_init_data){
388 	.aclk.hw.init = &(struct clk_init_data){
405 	.aclk.hw.init = &(struct clk_init_data){
422 	.aclk.hw.init = &(struct clk_init_data){
439 	.aclk.hw.init = &(struct clk_init_data){
456 	.aclk.hw.init = &(struct clk_init_data){
471 	.aclk.hw.init = &(struct clk_init_data){
489 	[AXXIA_CLK_FAB_PLL]  = &clk_fab_pll.aclk,
490 	[AXXIA_CLK_CPU_PLL]  = &clk_cpu_pll.aclk,
491 	[AXXIA_CLK_SYS_PLL]  = &clk_sys_pll.aclk,
492 	[AXXIA_CLK_SM0_PLL]  = &clk_sm0_pll.aclk,
493 	[AXXIA_CLK_SM1_PLL]  = &clk_sm1_pll.aclk,
494 	[AXXIA_CLK_FAB_DIV]  = &clk_fab_div.aclk,
495 	[AXXIA_CLK_SYS_DIV]  = &clk_sys_div.aclk,
496 	[AXXIA_CLK_NRCP_DIV] = &clk_nrcp_div.aclk,
497 	[AXXIA_CLK_CPU0_DIV] = &clk_cpu0_div.aclk,
498 	[AXXIA_CLK_CPU1_DIV] = &clk_cpu1_div.aclk,
499 	[AXXIA_CLK_CPU2_DIV] = &clk_cpu2_div.aclk,
500 	[AXXIA_CLK_CPU3_DIV] = &clk_cpu3_div.aclk,
501 	[AXXIA_CLK_PER_DIV]  = &clk_per_div.aclk,
502 	[AXXIA_CLK_MMC_DIV]  = &clk_mmc_div.aclk,
503 	[AXXIA_CLK_FAB]      = &clk_fab_mux.aclk,
504 	[AXXIA_CLK_SYS]      = &clk_sys_mux.aclk,
505 	[AXXIA_CLK_NRCP]     = &clk_nrcp_mux.aclk,
506 	[AXXIA_CLK_CPU0]     = &clk_cpu0_mux.aclk,
507 	[AXXIA_CLK_CPU1]     = &clk_cpu1_mux.aclk,
508 	[AXXIA_CLK_CPU2]     = &clk_cpu2_mux.aclk,
509 	[AXXIA_CLK_CPU3]     = &clk_cpu3_mux.aclk,
510 	[AXXIA_CLK_PER]      = &clk_per_mux.aclk,
511 	[AXXIA_CLK_MMC]      = &clk_mmc_mux.aclk,