97 	unsigned long divf, divq, vco_freq, reg;  in clk_pll_recalc_rate()  local
104 	divq = (reg & HB_PLL_DIVQ_MASK) >> HB_PLL_DIVQ_SHIFT;  in clk_pll_recalc_rate()
107 	return vco_freq / (1 << divq);  in clk_pll_recalc_rate()
113 	u32 divq, divf;  in clk_pll_calc()  local
121 	for (divq = 1; divq <= 6; divq++) {  in clk_pll_calc()
122 		if ((rate * (1 << divq)) >= HB_PLL_VCO_MIN_FREQ)  in clk_pll_calc()
126 	vco_freq = rate * (1 << divq);  in clk_pll_calc()
130 	*pdivq = divq;  in clk_pll_calc()
137 	u32 divq, divf;  in clk_pll_round_rate()  local
140 	clk_pll_calc(rate, ref_freq, &divq, &divf);  in clk_pll_round_rate()
142 	return (ref_freq * (divf + 1)) / (1 << divq);  in clk_pll_round_rate()
149 	u32 divq, divf;  in clk_pll_set_rate()  local
152 	clk_pll_calc(rate, parent_rate, &divq, &divf);  in clk_pll_set_rate()
162 		reg |= (divf << HB_PLL_DIVF_SHIFT) | (divq << HB_PLL_DIVQ_SHIFT);  in clk_pll_set_rate()
175 		reg |= divq << HB_PLL_DIVQ_SHIFT;  in clk_pll_set_rate()