Lines Matching refs:GATE_INFRA0

769 #define GATE_INFRA0(_id, _name, _parent, _shift)	\  macro
806 	GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "pwrap_ulposc_sel", 0),
807 	GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", "pwrap_ulposc_sel", 1),
808 	GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md", "pwrap_ulposc_sel", 2),
809 	GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", "pwrap_ulposc_sel", 3),
810 	GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scpsys", "scp_sel", 4),
811 	GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej", "axi_sel", 5),
812 	GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6),
813 	GATE_INFRA0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 8),
814 	GATE_INFRA0(CLK_INFRA_GCE2, "infra_gce2", "axi_sel", 9),
815 	GATE_INFRA0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10),
816 	GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0", "i2c_sel", 11),
817 	GATE_INFRA0(CLK_INFRA_AP_DMA_PSEUDO, "infra_ap_dma_pseudo", "axi_sel", 12),
818 	GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2", "i2c_sel", 13),
819 	GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3", "i2c_sel", 14),
820 	GATE_INFRA0(CLK_INFRA_PWM_H, "infra_pwm_h", "axi_sel", 15),
821 	GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1", "pwm_sel", 16),
822 	GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2", "pwm_sel", 17),
823 	GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3", "pwm_sel", 18),
824 	GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4", "pwm_sel", 19),
825 	GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", "pwm_sel", 21),
826 	GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22),
827 	GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23),
828 	GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24),
829 	GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25),
830 	GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m", "axi_sel", 27),
831 	GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cq_dma_fpc", "axi_sel", 28),
832 	GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif", "axi_sel", 31),