79 	void __iomem *apmu_base;  in mmp2_clk_init()  local
88 	apmu_base = ioremap(apmu_phys, SZ_4K);  in mmp2_clk_init()
89 	if (!apmu_base) {  in mmp2_clk_init()
329 				apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock);  in mmp2_clk_init()
333 				CLK_SET_RATE_PARENT, apmu_base + APMU_SDH0,  in mmp2_clk_init()
337 	clk = mmp_clk_register_apmu("sdh0", "sdh_div", apmu_base + APMU_SDH0,  in mmp2_clk_init()
341 	clk = mmp_clk_register_apmu("sdh1", "sdh_div", apmu_base + APMU_SDH1,  in mmp2_clk_init()
345 	clk = mmp_clk_register_apmu("sdh2", "sdh_div", apmu_base + APMU_SDH2,  in mmp2_clk_init()
349 	clk = mmp_clk_register_apmu("sdh3", "sdh_div", apmu_base + APMU_SDH3,  in mmp2_clk_init()
353 	clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB,  in mmp2_clk_init()
360 				apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock);  in mmp2_clk_init()
364 				CLK_SET_RATE_PARENT, apmu_base + APMU_DISP0,  in mmp2_clk_init()
369 				apmu_base + APMU_DISP0, 0x1b, &clk_lock);  in mmp2_clk_init()
373 				apmu_base + APMU_DISP0, 15, 5, 0, &clk_lock);  in mmp2_clk_init()
377 				apmu_base + APMU_DISP0, 0x1024, &clk_lock);  in mmp2_clk_init()
383 				apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock);  in mmp2_clk_init()
387 				CLK_SET_RATE_PARENT, apmu_base + APMU_DISP1,  in mmp2_clk_init()
392 				apmu_base + APMU_DISP1, 0x1b, &clk_lock);  in mmp2_clk_init()
396 				apmu_base + APMU_CCIC0, 0x1800, &clk_lock);  in mmp2_clk_init()
402 				apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock);  in mmp2_clk_init()
406 				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,  in mmp2_clk_init()
411 				apmu_base + APMU_CCIC0, 0x1b, &clk_lock);  in mmp2_clk_init()
415 				apmu_base + APMU_CCIC0, 0x24, &clk_lock);  in mmp2_clk_init()
419 				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,  in mmp2_clk_init()
424 				apmu_base + APMU_CCIC0, 0x300, &clk_lock);  in mmp2_clk_init()
430 				apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock);  in mmp2_clk_init()
434 				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,  in mmp2_clk_init()
439 				apmu_base + APMU_CCIC1, 0x1b, &clk_lock);  in mmp2_clk_init()
443 				apmu_base + APMU_CCIC1, 0x24, &clk_lock);  in mmp2_clk_init()
447 				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,  in mmp2_clk_init()
452 				apmu_base + APMU_CCIC1, 0x300, &clk_lock);  in mmp2_clk_init()