29 	struct clk_mux		pll_mux;  member
193 	struct clk_mux *pll_mux = &pll->pll_mux;  in rockchip_rk3036_pll_set_params()  local
207 	cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);  in rockchip_rk3036_pll_set_params()
209 		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);  in rockchip_rk3036_pll_set_params()
243 		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);  in rockchip_rk3036_pll_set_params()
428 	struct clk_mux *pll_mux = &pll->pll_mux;  in rockchip_rk3066_pll_set_params()  local
440 	cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);  in rockchip_rk3066_pll_set_params()
442 		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);  in rockchip_rk3066_pll_set_params()
478 		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);  in rockchip_rk3066_pll_set_params()
675 	struct clk_mux *pll_mux = &pll->pll_mux;  in rockchip_rk3399_pll_set_params()  local
689 	cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);  in rockchip_rk3399_pll_set_params()
691 		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);  in rockchip_rk3399_pll_set_params()
727 		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);  in rockchip_rk3399_pll_set_params()
860 	struct clk_mux *pll_mux;  in rockchip_clk_register_pll()  local
879 	pll_mux = &pll->pll_mux;  in rockchip_clk_register_pll()
880 	pll_mux->reg = ctx->reg_base + mode_offset;  in rockchip_clk_register_pll()
881 	pll_mux->shift = mode_shift;  in rockchip_clk_register_pll()
883 		pll_mux->mask = PLL_RK3328_MODE_MASK;  in rockchip_clk_register_pll()
885 		pll_mux->mask = PLL_MODE_MASK;  in rockchip_clk_register_pll()
886 	pll_mux->flags = 0;  in rockchip_clk_register_pll()
887 	pll_mux->lock = &ctx->lock;  in rockchip_clk_register_pll()
888 	pll_mux->hw.init = &init;  in rockchip_clk_register_pll()
894 		pll_mux->flags |= CLK_MUX_HIWORD_MASK;  in rockchip_clk_register_pll()
910 	mux_clk = clk_register(NULL, &pll_mux->hw);  in rockchip_clk_register_pll()